I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design Engineer, I want to make sure that if another tool has the capability of doing Linting earlier in the flow. for example, does Xcelium, Genus or Confomal support linting. I have seen some contradicting information online regarding this topic, though I can't find anything related to Linting on any of these tools.

Thanks

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and reduces project schedules with optimized continuous integration.(read more)

At what stage in the design cycle do you start to think about the PCB material costs? What about the costs to assemble the PCB? Once a design becomes successful, should you then redesign it to achieve a scalable product? Placing components and routi...(read more)

OrCAD X is the next-generation integrated PCB design platform. It brings to you a powerful cloud-enabled design solution that includes design and library data management integrated with the proven PCB design and analysis product portfolio of Cad...(read more)

Explore Impacts of Finite Interconnect Impedance on PDN Characterization

Over the past few decades, many details have been worked out in the power distribution network (PDN) in the frequency and time domains. We have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior. We also have frequency- and time-domain test methods to measure the steady-state and transient behavior of the built-up systems.

All of these pieces in our current toolbox have their own assumptions, limitations, and artifacts, and they constantly raise the challenging question that designers need to answer: How to select the design process, simulation, measurement tools, and processes so that we get reasonable answers within a reasonable time frame with a reasonable budget.

Read this award-winning DesignCon 2024 paper titled “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.” Led by Samtec’s Istvan Novak and written with a team of nine authors from Cadence, Amazon, and Samtec, the paper discusses a series of continually evolving challenges with PDN requirements for cutting-edge designs.

Read the full paper now: “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.”

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.

When it comes to system integration, PCB designers need to collaborate with the signal analysis or integrity team to run pre-route or post-route analysis and modify constraints, floorplan, or topology based on the results. Allegro PCB Edito...(read more)

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

Cadence is super excited to announce SPB 23.1 release —Your freedom to design boldly!  

These tools help engineers build better PCBs faster with the new 3D engine and optimized interface.  

We have been hard at work to bring you this release and believe that it will help you take control of the PCB design process with the powerful new features in Allegro X APD like: 

• Packaging Support in 3DX Canvas 

• 3DX Wire DRCs 

• Aligning Components by Offset 

• Text Wizard Enhancements 

• Device File Reuse for Existing Components for Netlist and Logic Import 

Watch this space to know all about What’s New in SPB 23.1.  

Regards 

Team PCBTech 

Cadence Design System 

For individuals, small businesses, or teams, START YOUR FREE TRIAL. 

Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD).

The splash screen for Allegro X APD will appear as shown below, instead of showing APD+ 2023:

For the Windows Start menu in 23.1, it will display as Allegro X APD 2023 instead of APD+ 2023, as shown below

23.1 Start menu 

In the Product Choices window for 23.1, you will see Allegro X Advanced Package Designer in the place of Allegro Package Designer +, as shown below: 

23.1 product title

Have you heard that starting SPB 23.1, Allegro Package Designer Plus (APD+) will be renamed as Allegro X Advanced Package Designer (Allegro X APD)? 

Allegro X APD offers multiple new features and enhancements on topics like Via Structures, Wirebond, Etchback, Text Wizards, 3D Canvas, and more. 

This post presents the new 3DX Canvas introduced in SPB 23.1. This can be invoked from Allegro X APD (from the menu item View > 3DX Canvas). 

Some of the key benefits of the new canvas: 

• This canvas addresses the scale and complexity in large modern package designs. It provides highly efficient visual representation and implementation of packages. 
  
• The new architecture enables high-performance 3D incremental updates by utilizing GPU for fast rendering. 
  
  
• Real-time 3D incremental updates are supported, which means that the 3D view is in sync with all changes to the database. 
  
  
• The new canvas provides 3D visualization support for packaging objects such as wire bonds, ball, die bump/pillar geometries, die stacks, etch back, and plating bar. 
  
  
• This release also introduces the interactive measurement tool for a 3D view of packages. Once you open 3DX Canvas, press the Alt key and you can select the objects you want to measure. 
  
• 3DX Canvas provides new 3D DRC Bond Wire Clearances with Real 3D DRC Checks. True 3D DRC in Constraint Manager has been introduced. If you open Constraint Manager, there will be a new worksheet added. Following DRC checks are supported: 

  Wire to Wire 
  Wire to Finger 
  Wire to Shape 
  Wire to Cline 
  Wire to Component

Power and Ground rings are exposed rings of metal surrounding a die that supply power/ground to the die and create a low-impedance path for the current flow. These rings ensure stable power distribution and reduce noise. Allegro X Package Designer Plus has a utility called Power/Ground Ring Generator which lets you define and place one or more shapes in the form of a ring around a die.

 To run the PWR/GND Generator Wizard, go to Route > Power/Ground Ring Generator or type "pring wizard" in the APD command window to invoke the Wizard.

This Wizard lets you define and place one or more shapes in the form of a ring around a die. The Power/Ground Ring Wizard creates up to 12 rings (shapes) at a time. If you require more rings, you can run the Power/Ground Ring Wizard as many times as needed. This command displays a wizard in which you can specify:

• The number of rings to be generated
• The creation of the first ring as a die flag (Die flag is the boundary of the die like the power ring.)
  • If you create a die flag and the first ring is the same net as the flag, you can enter a negative distance to overlap the ring and the die flag.
• Multiple options for placement of the rings with respect to:
  • Origination point
  • Distance from the edge of the die
  • Distance from the nearest die pin on each die side
• The reference designator of the die with which the rings will be used
• The distance between rings
• The width of each ring
• The corner types on each ring (arc, chamfer, and right-angle)
• An assigned net name for each ring
• A label for each ring

The rings are basic in nature. For other shape geometries or split rings, choose Shape > Polygon or Shape > Compose/Decompose Shape from the menu in the design window.

Depending on the options selected, the Power/Ground Ring Wizard UI changes, representing how the rings will be created. Verify the Wizard settings to ensure that the rings are created as intended.

1. When the Power/Ground Ring Wizard appears, set the number of rings to 2, accept the other defaults, and click Next. You can set Create first ring as die flag to create a basic die flag.

         2. Define Ring 1 and the net associated with it.

              a) Browse and choose Vss in the Net Names dialog box.

            b) Click OK.

            c) Specify the label as VSS.

            d) Click Next.

             The first ring should appear in your design. It is associated with the proper net; in this case, VSS.

2. For the second ring, choose the net as Vdd and specify the label as VDD.
3. Click Next.
4. Click Finish in the Result Verification screen to complete the process.

The completed rings appear as shown below.

Now, when you click on Power and Ground Die Pin and add wirebonds, you will see that the wirebonds are placed directly on the Power and Ground rings.

When things go wrong with your package design flow, it can sometimes be difficult to understand the cause of the issue. This can be something like a die component is wrongly identified as a BGA, a via stack has an alignment issue, or there are duplicate bondwires. These are just a few examples of issues; there can be many more. When interactive messages and log files do not help determine the problem, the Package Design Integrity Check tool becomes very handy. This feature lets you run integrity checks, which ensures that the database is configured correctly. 

To invoke the command from Allegro X Advanced Package Designer, use the Tools > Package Design Integrity menu. 

Or type package integrity at the Command  prompt. 

The Package Design Integrity Checks dialog box includes all categories and checks currently registered for the currently running product. You can enable all these categories and checks or only the one that you want to run. This utility can fix errors automatically (where possible). Errors and warnings are written to the “package_design_check.log” file.  

The utility can also be extended with your own custom rules based on your specific flows and needs. 

Hi,

I need to design EPC8002 eGaN switch in cadence. Can someone provide me step by step guide on hoe to add EPC8002 into my cadence. I am working on BCD180.

Thank you 

Ihsan

Designers have long recognized the need to analyze the reliability of ICs. Two commonly used approaches for performing reliability analysis include calculating the change in device degradation and relying on safe operating checks in circuit simulators. 

With the advent of the ever-increasing use of ICs in mission-critical applications, the need for reliable reliability analysis has become of paramount importance. Over the years, you have been using reliability analysis in Virtuoso ADE Assembler and Virtuoso ADE Explorer to measure and review aging effects, such as device characteristic degradations, model parameter changes, self-heating effects, and so on.

Reliability analysis can be performed using two modes: Spectre native and RelXpert. The reliability analysis analyzes the effect of time on circuit performance drift and predicts the reliability of designs in terms of performance. In ADE Assembler, you can run the reliability simulation for fresh test (when time is zero), stress test (to generate degradation data), and aged test (at specific intervals, such as one year, three years, or 10 years). In the stress test, extreme environmental conditions are used to stress devices before aging analysis.

The following figure shows the reliability simulation flow.

The Reliability Options form has the following four tabs: 

• Basic: Enables you to specify analysis type, aging options, start and stop time of reliability simulation, and options related to device masking, degradation ratio, and lifetime calculation. 

• Modeling: Enables you to choose the modeling type you want to use during reliability simulation. 

• Degradation: Enables you to specify the options to print device and subcircuit degradation information into a .bt0 file. 

• Output: Enables you to specify the degradation reports to be generated and methods to filter degradation results in the reports.

While the Basic and the Output tabs are used by design engineers, the Modeling and the Degradation tabs are primarily used by model developers.

Reviewing degradation reports in text or XML formats can be a tiresome exercise because degradation data can be large and can contain a large number of instances due to advanced technology nodes and post-layout simulations. For you to work effectively and interactively with these reports, the new reliability report is based on the SQLite database, which adds the benefit of improved performance and capabilities of sorting and filtering reliability data using SQLite operators.

As they say, watching this in action might help you more than reading about it, so please take a look at our Training Bytes video channel, which offers many helpful videos on how to run Reliability Analysis in Virtuoso Studio.

All the related videos are linked together in a channel so that you can easily access and watch as many as you like.

Reliability Analysis in Virtuoso Studio

Want to Learn More?

For lab instructions and a downloadable design, enroll for the online training courses of your interest on

Reliability Analysis in Virtuoso Studio vIC23.1 (Online)

 Training is also available as "Blended" or "live" class.

Digital Badge Available

You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal.

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
• You will need an email address and host ID in order to sign up.
• If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Related Resources

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Niyati Singh

On behalf of the Cadence Training team

This blog explores how Virtuoso Studio Net Tracer can help you perform a design review.

We’ll use the net connectivity option, which allows the user to get a clean highlighted net. You can use the Net Tracer tool to highlight the nets. You can find the Net Tracer command under the connectivity pulldown menu in the layout window.

Trace manager and the ability to display different islands on the same net with other colors, you can identify and connect the unconnected islands as you wish.

The Net Tracer utility traces the nets in the physical view (layout). The trace is a highlighted net, which is a non-selectable object. The Net Tracer utility is available from Virtuoso Layout Suite XL onwards. You can use this utility based on your specific needs and preferences.

For a better understanding of the Net Tracer feature, let’s see one scenario between the circuit designer and layout engineer for a layout design review.

Circuit designer: Can we go through the routed input nets “inm” and “inp”?

Layout engineer: From the below layout view where they are highlighted using the XL connectivity, today I will use Net Tracer utility for the design review.

Circuit designer: I have never heard of this feature. Let's see how it works.

Layout engineer: Sure, now we turn on the Net Tracer toolbar using the below option.

You see the Net Tracer options form here:

As you can see on my screen, I have opened the layout view and engaged the Net Tracer utility.

Net Tracer allows shapes to be traced on a net in two tracing modes, namely, physical and logical, where shapes on the same net are physically or logically connected.

Physical tracing gathers all the shapes physically connected on the same net.

Logical tracing gathers all the shapes assigned to the same net. It highlights the net as in the source design (schematic). It will highlight shapes on the same net, even if they are isolated shapes that are not physically connected.

For this scenario, let us use physical tracing for input nets “inm” and “inp."

Highlighted nets are shown below:

Net “inm”                    Net “inp”                   Nets “inm” and “inp” 

Net Tracer has features like physical and logical tracing, preview, step-by-step mode, ease of tracing a net on a shape out of multiple underlying shapes, and so on.

Let us explore logical tracing for output nets “outm” and “outp”:

Here, you can see how to enable true color and halo before enabling logical tracing to identify the metal route. After enabling the true color halo, enable the logical trace.

Here, I am opening the trace manager to search “outm” and “outp” and click trace. That will trace the particular nets as shown.

Net Tracer has a preview feature, which is helpful in terms of the number of previewed objects. This preview capability hints at how the trace would appear when you create it. This useful feature in Virtuoso Studio highlights both completed and incomplete nets, helping the user better understand the status of the highlighted nets.

Circuit designer: Thanks for the design review. You have done good work. Net Tracer clearly shows both types of tracing, and it was even easy for the circuit designer to understand.

Layout engineer: Let me share the link to the Net Tracer RAK, where other layout engineers can explore many more amazing features of the Net Tracer.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
• You will need an email address and host ID to sign up.
• If you need help with registration, contact support@cadence.com.

To stay up to date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

For any questions, general feedback, or future blog topic suggestions, please leave a comment.

Become Cadence Certified

Cadence Training Services now offers digital badges for this training course. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding these digital badges to your email signature or any social media platform, such as Facebook or LinkedIn. To become Cadence Certified, you can find additional information here.

Related Resources

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Sandhya.

On behalf of the Cadence Training team

As the title suggests I am unable to perform design sync between OrCAD Capture and Allegro. When I add a layout and try to sync to it I am given ERROR(ORCAP-2426): Cannot run Design Sync because of errors. See session log for error details.

Session Log

[ORPCBFLOW] : Invoking ECO dialog.
INFO(ORNET-1176): Netlisting the design
INFO(ORNET-1178): Design Name:
C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN
Netlist Directory:
c:usersddoyledocumentscadenceoards emote power devicelayoutallegro
Configuration File:
C:CadenceSPB_17.4 ools/capture/allegro.cfg
pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
Spawning... pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
{ Using PSTWRITER 17.4.0 d001Dec-14-2021 at 09:00:49 }

INFO(ORCAP-36080): Scanning netlist files ...

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstchip.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstchip.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstxprt.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstxnet.dat
packaging the design view...
Exiting... pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
INFO(ORNET-1179): *** Done ***

This issue started to occur after I changed parts that exist on previously created PCBs. I changed the following leading up to this:

1. Added height in Allegro to many of my components using the Setup->Area->Package Height tool.

2. Changed the reference designator category in OrCAD Capture to TP for several components on board.

Any advice here would be most welcome. Thanks!

Hi All

I followed tutorial video below for using Design link

https://www.youtube.com/watch?v=f9JmFF8lqA0

and I followed the video with embedded board design file which should be same one on video

I did every set. but  at 2:55 of video, Steve have the tabs of both design names on top of Constraint Manager in video

but my one didn't exist them

which one would be different?

there was some comment on command windows but I think they would not be problem here

regard

Hi

I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell?  I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain.  I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again.  I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it.  Is there a way to "break" the features of XL like this?  I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.

Thanks

Chris

Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more)

Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more)

A constraint is a user-defined property, or a rule, applied to a physical object, such as a net, pin, or via in a design. There are a number of constraints that can be applied to an object based on its type and behavior. For example, you can define t...(read more)

By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more)

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more)

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

Which Analysis is Being Performed by Allegro in this Image?

A. Impedance

B. Coupling

C. Crosstalk

D. Return Path

E. Reflection

Simply answer by letter or include any reason to support your answer...

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

Hai Community,

What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24.

Can I get the grid matrix difference between these two tools?

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution, and Quantus Extraction Solution—Socionext achieved remarkable improvements.

Notably, the Tempus DSTA tool dramatically cut timing closure time by 73%, outperforming conventional single-machine STA methods. This achievement, combined with the synergistic use of Cadence's Certus Closure and Tempus Timing solutions, allowed Socionext to meet their ambitious three-day iteration target and double productivity. Additionally, integrating these solutions significantly decreased both human and machine resource needs, slashing memory and disk costs by up to 90% and halving engineering resources during the optimization and signoff phases.

For more on this collaboration, check out the "Designed with Cadence" success story video on Cadence's website and YouTube channel.

Also, don't miss the on-demand webinar "Fast, Accurate STA for Large-Scale Design Challenges," which provides a deeper dive into Socionext's breakthroughs and the innovative solutions that powered their success.

The world of electronics design thrives on efficient tools that bridge the gap between concept and silicon. Virtuoso Digital Implementation is a powerful ally for mixed-signal designs, which integrate both analog and digital components. This blog post will examine Virtuoso Digital Implementation's capabilities and explore how it can streamline your mixed-signal design workflow.

Virtuoso Digital Implementation in a Nutshell

Virtuoso Digital Implementation is a license package within the Cadence Virtuoso Design Platform. It offers a streamlined RTL-to-GDSII flow to implement smaller digital blocks within a mixed-signal design environment. Here's what makes Virtuoso Digital Implementation stand out:

• Focus on Small Digital Blocks: Optimized for digital blocks with an instance count of up to 50,000 (expandable to 150,000 with specific configurations), Virtuoso Digital Implementation is ideal for integrating digital logic into your analog-centric design.
• Leveraging Industry Leaders: Virtuoso Digital Implementation utilizes cut-down versions of the renowned Cadence Genus Synthesis Solution and Innovus Implementation System under the hood. This ensures you get access to proven technologies for logic optimization and place-and-route.
• Seamless Integration with the Virtuoso Environment: Virtuoso Digital Implementation's key advantage is its tight integration with the Virtuoso Layout Suite. You can launch the synthesis and place-and-route tools directly from the Virtuoso environment, eliminating the need to switch between platforms.

Benefits of Using Virtuoso Digital Implementation

 By incorporating Virtuoso Digital Implementation into your mixed-signal design flow, you can get several benefits:

• Simplified Workflow: Virtuoso Digital Implementation offers a centralized environment for both digital block implementation and layout editing within the Virtuoso environment. This reduces context switching and streamlines the design process.
• Faster Time-to-Market: Virtuoso Digital Implementation's streamlined workflow can significantly reduce design turnaround times, allowing you to get your product to market quicker.
• Improved Design Quality: Leveraging industry-leading synthesis and place-and-route engines from Cadence ensures high-quality digital block implementation within your mixed-signal design.

Who Should Consider Virtuoso Digital Implementation?

 Virtuoso Digital Implementation is a valuable tool for anyone working on mixed-signal designs with smaller digital blocks. It's particularly well-suited for:

• Analog IC designers who need to integrate digital logic into their designs.
• Circuit design teams working on mixed-signal applications like data converters, power management ICs, and RF transceivers.

Virtuoso Digital Implementation provides a compelling solution for designers working on mixed-signal projects. Its streamlined workflow, tight integration with the Virtuoso design platform, and access to proven digital design tools can significantly improve design efficiency and time-to-market. Virtuoso Digital Implementation is worth considering if you're looking to optimize your mixed-signal design flow.

I am here to help and guide you on how to learn more about Virtuoso Digital Implementation flow.

Welcome to Virtuoso Digital Implementation, an online course recently released. This course teaches implementing digital blocks using Cadence tools based on the Virtuoso Digital Implementation flow. Also, you can download a lab database after the lecture and get hands-on experience in each stage.

Want to Enroll in this Course?

We organize this Virtuoso Digital Implementation training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

• Log on to cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for Virtuoso Digital Implementation using the search bar.
• Select the course and click Enroll.

And don't forget to obtain your Digital Badge after completing the training!

Related Resources

Online Courses

• Cadence RTL-to-GDSII Flow v6.0
• Virtuoso Digital Implementation Training

Training Byte Videos

• How Do You Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus?

Happy Learning!

The traditional methods of power analysis lag by various shortcomings and challenges:

• Getting an accurate measure of RTL power consumption during design exploration
• Getting consistent power through the design progress from RTL to P&R.
• System-level verification tools are disconnected from the implementation tools that translate RTL to gates and wires.

The Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes, capacity, and high-quality estimates of gates and wires based on production implementation technology. The Cadence Joules RTL Power Solution is an RTL power analysis tool that provides a unified engine to compute gate netlist power and estimate RTL power. The Joules solution delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power.

Moreover, it integrates seamlessly with numerous Cadence platforms, eliminating compatibility and correlation issues! In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities.

Want to take a tour of this power estimation world? Gear up to attend the training class created just for you to dive deep into the entire flow and explore this exciting power estimation method/flow with hands-on labs in two days!

Training

In the Joules Power Calculator Training course, you will identify solutions and features for RTL power using Cadence Joules RTL Power Solution. You will set up and run the RTL power flow with Joules RTL Power Solution and identify Joules's Graphical User Interface (GUI) capabilities. The training also explores how you can estimate power using vectorless power, stimulus flow, RTL Stim to Gate flow, and replay flow, and also interfaces Joules with Cadence's Palladium Emulation Platform. You will estimate power at the chip level and understand how to navigate the design and data mining using Joules.

The training also covers power exploration features and how to analyze ideal power and ODC-driven sequential clock gating. You will identify low-activity registers at the clock gate. You will also identify techniques to analyze power, generate various reports, and analyze results through Joules GUI. The training covers multiple strategies to debug low stimulus annotation and how you can better correlate RTL power with signoff. You also identify Genus-Joules Integration. In addition, we ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

To start you on your exciting journey as an RTL power analysis expert, we have created a series of short channel lab videos on our Customer Support site: Lab Demo: Setting Up and Running Basic RTL Power Flow in Joules RTL Power Solution (Video). You can refer to each lab module's instructions in demo format. This will help accelerate your tool ramp-up and help you perform the lab steps more quickly if you are stuck. You might be a beginner in the RTL power analysis world, but we can help you sail through it smoothly.

What's Next?

Grab your badge after finishing the training and flaunt your expertise!

Related Training

• Genus Low-Power Synthesis Flow with IEEE 1801
• Low-Power Synthesis Flow with Genus Stylus Common UI

Related Blogs

• Do You Want to Flaunt Your Expertise? Grab the Digital Badge Today!
• Become Cadence Certified
• Let's Replay the Process of Power Estimation with the Power of 'x'
• Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit
• What's Inside Joules Graphical User Interface
• Joules – Power Exploration Capabilities

Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions.

Conformal ECO compares two designs and generates a functional patch that implements the changes between the two designs.

One major criterion for determining patch quality is whether the patch can meet timing closure. To determine this, you typically need to run the time-consuming process of incremental synthesis and place-and-route. Instead, Conformal can analyze path logic depth changes before and after ECO patch generation. This provides a faster way to evaluate timing impact in patch generation stages.

After the patch is created and applied, it is passed to Genus to optimize the patch.

During patch optimization, you can choose to do many things like:

• Keeping constants in the patch
• Allowing tie cell inversion
• Specifying tie cell types
• Preserve DFF cells and cell types in the patch
• Preserve all cells and nets in the patch
• Preserve clock buffer cell in the patch
• Turn on/off sequential constant and sequential merge in patch optimization
• Allowing phase mapping for DFFs
• Map to spare cells
• Force fix DRC before timing

What's Next?

Join the Conformal ECO course to:

• Explore the many options and capabilities of Conformal ECO
• Use Conformal Engineering Change Order (ECO) for flat and hierarchical designs
• Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology
• Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
• Run a postmask ECO using Conformal ECO GXL

Make sure you have experience with Conformal Equivalence Checker or completed the Conformal Equivalence Checking course before taking this course.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore.

Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner.

As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power.

Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts.

Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer.

We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals.

We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them.

In addition, we’ll talk about basic debug rules and methods to analyze failures.

Sounds Interesting?

Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024!

For more details and registration, please contact Training Germany.

If you would like to have an instructor-led training session in another region please contact your local training department.

Become Cadence Certified

Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn.

Related Training

Innovus Block Implementation with Stylus Common UI

Related Training Bytes

Cerebrus Primitives (Video) 

How to Reuse Cerebrus (Video) 

Cerebrus - Verifying Distribution Script (Video)

How to distribute Cerebrus Scenarios (Video) 

Cerebrus Web Interface Monitor and Control (Video) 

How to Setup Cerebrus for a Successful Run (Video) 

Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) 

Cerebrus Cost Functions (Video) 

Related Blogs

Training Insights: Cadence Cerebrus Webinar Recording Now Available!

Keep Up with the Revolution—Cadence Cerebrus Training

New to Equivalence Checking? Restart from the Basic Concepts

Training Insights - Free Online Courses on Cadence Learning and Support Portal

Training Insights – Important Facts You Should know About Our Cadence Learning and Support Portal

To provide high-quality medical care to its population — around 30% of whom are 65 or older — Japan is pursuing sovereign AI initiatives supporting nearly every aspect of healthcare. AI tools trained on country-specific data and local compute infrastructure are supercharging the abilities of Japan’s clinicians and researchers so they can care for patients, Read Article

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

Government is scoping the market for potential interest in the design and construction of a new Gozo hospital, a process abandoned when the Steward Health Care concession was terminated

ADB sought to understand what improving transport meant for the community. Prior to project design, consultations were conducted with residents in Ulaanbaatar’s ger areas. Design decisions were tested back to ensure that mobility pain points were addressed.

to design cars like a pro

Two types of fusion reactor called tokamaks and stellarators both have drawbacks – but a new design combining parts from both could offer the best of both worlds

Title: Scientists Design Skin Patch That Takes Ultrasound Images
Category: Health News
Created: 7/29/2022 12:00:00 AM
Last Editorial Review: 7/29/2022 12:00:00 AM

Purpose Dental professionals are exposed to hazardous noise levels on a daily basis in clinical practice. The purpose of this study was to compare the hearing status of dental hygienists who utilize ultrasonic scalers in the workplace compared to age-matched control participants (non-dental hygienists) who were not exposed to ultrasonic noise.Methods A convenience sample of nineteen dental hygienists (experimental) and nineteen non-dental hygienists (control) was recruited for this study. A matched pairs design was utilized; participants in each group were matched based on age and gender to eliminate confounding variables. The testing procedure consisted of an audiologist performing a series of auditory tests including otoacoustic emissions test, pure-tone audiometry, and tympanometry on the experimental and control groups.Results In the right ear, there were notable differences from 1000 Hz – 10,000 Hz and in the left ear from 6000 Hz – 10,000 Hz, with higher hearing thresholds in the experimental group of dental hygienists. While 56% of the univariate tests conducted on how many days were worked per week showed statistical significance, the regression line slope indicated those that worked more days had better hearing statuses. The variables for years in practice for dental hygienists, how many of those years were full-time employment, and how many years the dental hygienist had used an ultrasonic scaling device, also had many significant univariate tests for the experimental group only. These variables were more likely to serve as proxies representing true noise exposure. The paired t-test between the groups demonstrated statistically significant differences between the experimental and control group at 9000 Hz in both ears.Conclusion While results from this study demonstrated various qualitative differences in hearing status of the control group (non-dental hygienists) and experimental group (dental hygienists), age was found to be the most critical variable. Furthermore, this data demonstrated differences in hearing status based on various frequencies between dental hygienists and age-matched controls that should be further explored with a larger population.