As organizations harness the power of data, they can unlock new possibilities and drive transformative initiatives. Katragadda's insights make it abundantly clear that data is the cornerstone of any AI strategy.

Charlotte Pipe’s large diameter fittings include injection-molded and fabricated fittings produced by experienced fabricators with the latest technology available.

PITTSBURGH, Feb. 22, 2024 — Ansys and Intel Foundry have collaborated to provide multiphysics signoff solutions for Intel’s innovative 2.5D chip assembly technology, which uses EMIB technology to connect the […]

The post Ansys, Intel Foundry Collaborate on Multiphysics Analysis Solution for EMIB 2.5D Assembly Tech appeared first on HPCwire.

With competition heating up in the foundry business – India this week approved three new semiconductor plants involving Tata Group and CG Power,, and is looking to achieve dominance in the industry – existing foundries have to up their game. Chief among them is Intel, which has been trying to recover from historical missteps that […]

OpenAI is working with Broadcom and TSMC to build its first in-house chip designed to support its artificial intelligence systems, per sources

I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. 

Inside Cadence, we maintain a database that shows which foundries support which process for which products.  This means that we can quickly give you an answer if you are considering using a new process or foundry, and you want to know whether Assura is supported.  Your friendly local Cadence physical verification AE has access to this information and should be able to answer your questions about rule deck support. 

Our Assura R&D team is constantly working with the foundries to help update existing rule decks and create new ones.  But with all due respect to our foundry partners, their field support teams are not always aware of the latest efforts on rule deck creation and support. 

Of course, it's important to check the status of Assura support with your foundry.  This has the added benefit to Cadence that it lets them know that you're using Assura.  But please also double-check with your Cadence AE, who can ping me to make sure that you're getting the latest information. 

Increasing energy efficiency in Europe is vital to achieving a sustainable economy and tackling climate change. However, new research has shown that lack of capital and concerns about costs of disruption are major barriers to implementing energy efficiency measures in the foundry industry.

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A foundry mixture for making molds used for molding cast metal parts includes foundry sand, a non-aqueous binder, and a cleaning agent that includes calcium oxide. Residual foundry mixture remaining on the cast part after removal from the mold is removed by electrolytic cleaning of the cast part.

See how to develop and deploy advanced Cloud Foundry applications in the IBM Cloud. Doug Tidwell shows you how to create a globally available app that uses a cloud-hosted NoSQL database.

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

Semiconductor designers have long been making test chips to validate test structures, memory bit cells, larger memory blocks, and precision analog circuits like current mirrors, PLLs, temperature sensors, and high-speed I/Os. This has been done at 90nm, 65nm, 40nm, 32nm, 28nm, etc., so having test chips at 16nm, 7nm, or finer geometries should not be a surprise. Still, as costs rise, there is debate about whether those chips are over-used given advancements in tooling, or whether they should be utilized even more, with more advanced diagnostics built into them.

Modern EDA tools are very good. You can simulate and validate almost anything with certain degree of accuracy and correctness. The key to having good and accurate tools and accurate results (for simulation) is the quality of the foundry data provided. The key to having good designs (layouts) is that the DRC deck must be of high quality and accurate and must catch all the things you are not supposed to do in the layout. Most of the challenges in advanced node is in the FEOL where semiconductor physics and lithography play outsize roles. Issues that were not an issue at more mature nodes can manifest themselves as big problems at 7nm or 5nm. Process variation across the wafer and variation across a large die also present problems that were of no consequence in more mature nodes.

The real questions to be asked are as follows:

What is the role of test chips in SoC designs?

1. Do all hard IP require test chips for validation?
2. Are test chips more important at advanced nodes compared to more mature nodes?
3. Is the importance of test chip validation relative to the type of IP protocols?
4. What are the risks if I do not validate in silicon?

In complex SoC designs, there are many high-performance protocols such as LPDDR4/4x PHY, PCIe4 PHY, USB3.0 PHY, 56G/112G SerDes, etc. Each one of these IP are very complex in and by itself. If there is any chance of failure that is not detected prior to SoC (tapeout) integration, the cost of retrofit is huge. This is why the common practice is to validate each one of these complex IP in silicon before committing to use such IP in chip integration. The test chips are used to validate that the IP are properly designed and meet the functional specifications of the protocols. They are also used to validate if sufficient margins are designed into the IP to mitigate variances due to process tolerances. All high-performance hard IP go through this test chip/silicon validation process. Oftentimes, marginality is detected at this stage. In advanced nodes, it is also important to have the test chips built under different process corners. This is intended to simulate process variations in production wafers so as to maximize yields. Advanced protocols such as 112G, GDDR6, HBM2, and PCIe4 are incredibly complex and sensitive to process variations. It is almost impossible to design these circuits and try to guarantee their performance without going through the test chip route.

Besides validating performance of the IP protocols, test silicon is also used to validate robustness of ESD structures, sensitivity to latch up, and performance degradation over wide temperature ranges. All these items are more critical in advanced nodes than more mature modes. Test chips are vehicles to guarantee design integrity in bite-size chunks. It is better to deal with any potential issues in smaller blocks than to try to fix them in the final integrated SoC.

Test chips will continue to play a vital role in helping IP and SoC teams lower the risk of their designs, and assuring optimal quality and performance in the foreseeable future. They are not going away!

To read more, please visit https://semiengineering.com/test-chips-play-larger-role-at-advanced-nodes/

Puppet, the Portland-based infrastructure automation company, today announced that it has named former Cloud Foundry Foundation executive director Abby Kearns as its new CTO. Current Puppet CTO Deepak Giridharagopal will remain in his role and focus on R&D and leading new projects, while Kearns will focus on expanding the company’s product portfolio and communicating with […]

The Cloud Foundry Foundation (CFF) just went through a major leadership change, with executive director Abby Kearns stepping down after five years (and becoming a CTO at Puppet) and the CFF’s CTO Chip Childers stepping into the top leadership role in the organization. For the most part, though, these changes are only accelerating some of […]