Company Renowned for ‘Headset’ Innovation Cuts Time and Cost with SolidWorks Design and Simulation Software

Re-Design a Greener Airport Chair

Design team to create a “Hot Rod Baby Buggy” with help of the SolidWorks community

User Group Community Continues to Innovate and Elevate Jeremy Singley’s Design to the Next Level

Three Grand Prize Winners in Commercial and Education Fields Go Green with Airport Chair Redesign

20th Release of Leading CAD Software Provides More than 200 New Functions to Community

Episode Showcases Performance of Straitline Components’ Custom Hydraulic Brake Line Detangler in JumpShip Competition

Team Improves Solar Car Aerodynamics by 30 Percent, Reduces Weight by 200 Pounds

World-Class Sports Car Manufacturer Reduces Number of Prototypes by Half for Newly Redesigned, Hand-crafted D8 GTO

-- Crowdsourced video design series produces stroller that makes dads proud --

SOLIDWORKS Sustainability integrates analyses at the beginning of the product development process

FISHER/UNITECH Provides Tools to Create a Collapsible, Detachable Roof That Can Be Pulled Over a Motorcycle in a Few Seconds

Latest Release of Leading 3D Design Solution Enables Faster Model Creation, Optimized Performance, Enhanced Collaboration

Partnership with 3DVision Technologies Reduces Materials and Manufacturing Costs

ModernTech Teaches Bo-Dyn How to Find Hundredths of a Second for a Golden Repeat

MARE’s BATFish improved speed, size and savings of oceanographic surveys with SolidWorks design technology

Leading Measurement Technology Manufacturer Increases Product Quality and Reduce Costs

Conference Profiles Customers’ Innovation and Unveils New Offering

Apple's 2024 Mac mini stashes the power button underneath, a bold move that executives say aligns with user habits, even if it's left some fans scratching their heads.

Schools are not preparing students to enter an increasingly diverse world, writes high school senior Zoë Jenkins.

The battle stems from Varsity Brands' efforts to gain copyright protection for the design of stripes, chevrons, zigzags, and color blocks that are on its uniforms.

As a kid, Eli R. Rush fell in love with roller coasters. As an adult, he’s turned that passion into a livelihood. The Pennsylvania College of Technology alumnus is a designer for a renowned manufacturer and builder of coasters.

Penn State Hazleton Benefiting THON, the campus’ THON chapter, will host a designer purse and gift card bingo on Sunday, Oct. 20. Doors open at 1 p.m. and games will start at 2 p.m. in the Dr. Thomas M. Caccese Gymnasium in the Physical Education Building. The event is open to the public. 

"When the day came to administer the first test I had designed," writes Brandon Lewis, "my heart sank."

WILMINGTON – The Delaware Department of Services for Children, Youth and Their Families is sharing the agency’s newly redesigned website. Launched Thursday, July 29, the website redesign of kids.delaware.gov was in coordination with the Department’s rebranding over the last year, which has included a new, updated logo. Throughout this process, DSCYF worked with the Department […]

Apple unveiled its first mixed-reality headset Vision Pro at WWDC last year. Rumours about its successor have been circulating online for a while, and now Bloomberg's Mark Gurman has suggested the launch timeline for the next generation Apple Vision Pro. Gurman claims that the upcoming model will have a similar design as the current model.

Honor Magic 7 RSR Porsche Design will join the Honor Magic 7 series soon. As we await the formal launch of the handset, its key specifications have surfaced online. The Honor Magic 7 RSR Porsche Design is tipped to feature a 6.8-inch display with 1.5K resolution and a triple rear camera unit comprising a 200-megapixel periscope telephoto sensor.

Vivo Y300 5G will launch soon in India, the Chinese tech brand announced on Tuesday. Vivo has not revealed the launch date of the new Y series phone, but has shared an image on the social media platform showing its rear design. The Vivo Y300 appears to have a dual rear camera unit. It is expected to debut as a mid-range smartphone with upgrades over last year's Vivo Y200.

Oppo is said to be working on the Reno 13 series. While the brand is yet to announce the China launch date, a report has surfaced online suggesting the India launch timeline of the Oppo Reno 13 series. The new lineup is expected to come with at least two offerings, namely the Oppo Reno 13 and the Reno 13 Pro. Additionally, an alleged render of the Oppo Reno 13 has leaked on Weibo showcasing an iPhone-style rear design.

DOVER, Del. – The Delaware Division of Small Business launched SizeUpDelaware this week, making powerful market research and business intelligence available to small businesses to help them succeed. Small business owners in Delaware can now access industry-specific and hyperlocal information to help them grow and make smarter decisions using Big Data analysis. The research is individually […]

High Visibility Enforcement Against Impaired Driving Scheduled for March 11-21 in Maryland and Delaware Along US 13 and US 113 DOVER, DE (March 12, 2021) – This year St. Patrick’s Day may look a little different as Delaware continues to stress social distancing and COVID-19 precautions. But for those planning to celebrate with family and friends, […]

Google's Gmail update went live this week. Here's what marketers need to know

NA

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...(read more)

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

Hi,

Is there any way to instruct the tool to reduce the low metals effort and route more on top layers? 

Hi all, 

I have made a custom cell in Innovus that I will be instantiating into a bigger block, which I will also be using Innovus to do the Place & Route. 

I understand that I can generate a *.lef file and a *.lib file using Innovus. However, I need to also create a *.db file (these format of files are often used in DC Compiler synthesis tool). 

Is there a way to create the *.db file from Innovus? Or, is there a tool that I can use to create this *.db file? 

Thank you for your time. 

A new Python library has been written to facilitate an interface between Python and AWR software using a command structure that adheres more closely to Python coding conventions. This library is labeled "pyawr-utils" and it is installed using the standard Python pip command. Comprehensive documentation for installing and using pyawr-utils is available.(read more)

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog covers the user interface (UI) and simulation considerations designers should note prior to starting a design.(read more)

Cadence AWR Design Environment Software Featured in Multiple Training Course Options: Live and Virtual Starting in October(read more)

The Cadence AWR Design Environment V22.1 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.(read more)

AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a combination of optimization methods, switching back and forth between methods to efficiently find the lowest optimization error function cost. The optimization algorithm automatically determines when to switch to a different optimization method, making this a superior method over manual selection of algorithms. This method is particularly robust in regards to finding the global minima without getting stuck in a local minima well.(read more)

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog, part 2, covers the layout and component library considerations designers should note prior to starting a design.(read more)

A training webinar on Microwave Office will be given June 27, 2023. The emphasis will be on EM simulation.(read more)

A recording of a training webinar on Microwave Office is available. Topics show the design environment, with special emphasis placed on electromagnetic (EM) simulation. Normal 0 false false false EN-US JA X-NONE ...(read more)

By David Vye, Senior Product Marketing Manager, AWR, Cadence When designing multi-octave high-power amplifiers, it is a challenge to achieve both broadband gain and power matching using a combination of lumped and distributed techniques. One approach...(read more)

Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..

I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes the transmission gate alongside standard cells?

Could you provide guidance or a methodology for integrating custom cells, like the transmission gate, into the synthesis flow for accurate analysis?