Hello Community,

Is there any simple way how i can get the coordinates of all the shapes in a layout view?

Currently i'm flattening the layout, getting all the lpps from CV and using setof to get all the shapes of a layer and looping through them to get the coordinates.

Is there a way to do it without having to flatten the layout view and shapes merged or any other elegant way to do it if we flatten it?

Also, dbWriteSkill doesn't give output how i desired

Thanks,

Shankar

Hello,

I would like to create a button for my form that prompts the user to click on a cellview and draw a rectangle bounding box, exactly like the one used in the Area and Density Calculator. Can someone please help me with this?

Thanks!

Beto

Hi,

I want to define a procedure that with @key, and I also want to restrict the variable's datatype, I tried with folloing but I received error in CIW

procedure(tt(handler @key str1 str2 "ssS")
  printf("handler: %L " handler)
)

tt('test)

The error is like: *Error* tt: argument for keyword ?str1 should be a symbol (type template = "ssS") at line 11 of file

Thanks,

James

A new Python library has been written to facilitate an interface between Python and AWR software using a command structure that adheres more closely to Python coding conventions. This library is labeled "pyawr-utils" and it is installed using the standard Python pip command. Comprehensive documentation for installing and using pyawr-utils is available.(read more)

Thermal analysis with the Cadence Celsius Thermal Solver integrated within the AWR Microwave Office circuit simulator gives designers an understanding of device operating temperatures related to power dissipation. That temperature information can be introduced into an electrothermal model to predict the impact on RF performance.(read more)

AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a combination of optimization methods, switching back and forth between methods to efficiently find the lowest optimization error function cost. The optimization algorithm automatically determines when to switch to a different optimization method, making this a superior method over manual selection of algorithms. This method is particularly robust in regards to finding the global minima without getting stuck in a local minima well.(read more)

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing everything from III-V 5G chips, to RF systems in board and package technologies. These types of designs require close interaction between the schematic and its layout. A new Training Byte demonstrates how the schematic-layout connections is built into Microwave Office.(read more)

Hi Cadence, 

I use simvision 20.09-s007 but my computer screen resolution is very high. As a result, the texts are too small. 

In ~/.simvision/Xdefaults I changed that number to 16, from 12. But the signal names in the waveform traces don't reflect the change. 

Simvision*Font: -adobe-helvetica-medium-r-normal--16-*-*-*-*-*-*-*

Other .font changes seem to reflect on the simvision correctly, except the signal names. 

How do I fix that? I dont mind a single variable to change all the texts fonts to 16. 

Thank you!

PS: I found the answer with another post. I change Preference/Waveform/Display/Signal Height. 

I am scripting gds streamin using 'strmin', which works fine so far.

But, as it apparently doesn't have an option to specify where the cds.lib file is, I have to run it from the directory where the cds.lib file is, or I guess I could create a dummy one to source that one.

Is there a way to tell strmin where the cds.lib file is?

Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..

Hello,

I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help 

 -submit waveform loadsignals -using "Waveform 2" FB1.svwf but it gives me the below error

-submit waveform new -reuse -name Waveforms

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more)

The automotive industry revolutionized the definition of a vehicle in terms of safety, comfort, enhanced autonomy, and internet connectivity. With this trend, the automotive industry rapidly adopted automotive Ethernet such as 10Base-T1, 100Base-T1, and in some cases, 1000Base-T1. 

Faster Speed (than CAN-FD), Scalability, embedded security protocols (like MacSec), cost and energy efficiency, and simple yet redundant network made Ethernet an obvious choice over CAN(FD) and FlexRay.  

Ethernet 10Base-T1 

10BASE-T1S is defined under IEEE with 802.3cg. The S in 10BASE-T1S stands for a short distance. 10BASE-T1S uses a multidrop topology, where each node connects to a single cable. Multidrop topology eliminates the need for switches and, as a result, fewer cables/less cost. The primary goal of 10BASE-T1S is a deterministic transmission on a collision-free multidrop network. 10BASE-T1S cables use a pair of twisted wires. As per IEEE, at least eight nodes can connect to each, but more connections are feasible.    

The Physical Layer Collision Avoidance [PLCA] protocol ensures that it uses the entire 10 Mbps bandwidth. In 10BaseTs, Reconciliation Sublayer provides optional Physical Layer Collision Avoidance (PLCA) capabilities among participating stations. Using PLCA-enabled Physical Layers in CSMA/CD half-duplex shared-medium networks can provide enhanced bandwidth and improved access latency under heavily loaded traffic conditions. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). 10BASE-T1S also supports an arbitration scheme that guarantees consistent node access to the media within a predefined time.  

The 10BASE-T1S PHY is intended to cover the low-speed/low-cost applications in the industrial and automotive environment. A large number of pins (16) required by the MII interface is one of the significant cost factors that must be addressed to fulfill this objective. The 10BASE-T1S "Transceiver" solution is suited for embedded systems where the digital portion of the PHY is fully integrated, e.g., into an MCU or an Ethernet switch core, leaving only the analog portion (the transceiver) into a separate IC. 

Ethernet 100Base-T1/1000Base-T1 

100Base-T1 and 1000Base-T1 can be used for audio/video information. With Higher bandwidth capacity, 100Base-T1/ 1000Base-T1 paired with AVB (Audio video bridging) can be used for car infotainment systems. 100Base-T1/1000Base-T1 paired with time-sensitive networking [TSN] protocol can be used to fulfill the automotive industry's mission-critical, time-sensitive, and deterministic latency needs. 

 PTP Over MacSec  

With today's automotive network, all the Electronic Control Units connected require timing accuracy and network synchronization, Precision Time Protocol (PTP), defined in IEEE 1588, provides synchronized clocks throughout a network.  While maintaining the timing accuracy for mission-critical applications, protecting the vehicle network from vulnerable threats is mandatory, and PTP over MacSec provides the consolidated solution.  

With the availability of the Cadence Verification IP for 10/100/1000BaseT1 and TSN, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. The 10/100/1000GBaseT1 and TSN provide a full-stack solution, including support to the PHY, MAC, and TSN layers with a comprehensive coverage model and protocol checkers. Ethernet BaseT1 and TSN VIP covers all features required for complete coverage verification closure. More details are available in the Ethernet Verification IP portfolio. 

Krunal 

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more)

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and reduces project schedules with optimized continuous integration.(read more)

OrCAD X is the next-generation integrated PCB design platform. It brings to you a powerful cloud-enabled design solution that includes design and library data management integrated with the proven PCB design and analysis product portfolio of Cad...(read more)

Introduction

Multiphysics is an integral part of the concepts around digital twins. In this post, I want to discuss the mechanical aspects of multiphysics in system simulations, which are critical for 3D-IC, multi-die, and chiplet design.

The physical world in which we live is growing ever more electrified. Think of the transformation that the cell phone has brought into our lives, as has the present-day migration to electronic vehicles (EVs). These products are not only feats of electronic engineering but of mechanical as well, as the electronics find themselves in new and novel forms such as foldable phones and flying cars (eVOTLs). Here, engineering domains must co-exist and collaborate to bring about the best end products possible.

Start with the electronics—chips, chiplets, IC packaging, PCB, and modules. But now put these into a new form factor that can be dropped or submerged in water or accelerated along a highway. What about drop testing, aerodynamics, and aeroacoustics? These largely computational fluid dynamics (CFD) and/or mechanical multiphysics phenomena must also be accounted for. And then how does the drop testing impact the electrical performance? The world of electronics and its vast array of end products is pushing us beyond pure electrical engineering to be more broadly minded and develop not only heterogeneous products but heterogeneous engineering teams as well.

Cadence's Unique Expertise

It's at this crossroad of complexity and electronic proliferation that Cadence shines. Let's take, for example, the latest push for higher-performing high-bandwidth memory (HBM) devices and AI data center expansion. These technologies are growing from several layers to 12, and I can't emphasize enough the importance of teamwork and integrated solutions in tackling the challenges of advanced packaging technologies and how collaboration is shaping the future of semiconductor innovation and paving the way for cutting-edge developments in the industry.

These layered electronics are powered, and power creates heat. Heat needs to be understood, and thus, the thermal integrity issues uncovered along the way must be addressed. However, electronic thermal issues are just the first domino in a chain of interdependencies. What about the thermal stress and warpage that can be caused by the powering of these stacked devices? How does that then lend to mechanical stress and even material fatigue as the temperature cycles from high to low and back through the use of the electronic device? This is just one example in a long list of many...

Cadence Multiphysics Analysis Offerings

The confluence of electrical, mechanical, and CFD is exactly why Cadence expanded into multiphysics at a significant rate starting in 2019 with the announcement of the Clarity 3D Solver and Celsius Thermal Solver products for electromagnetic (EM) and thermal multiphysics system simulations. Recent acquisitions of Numeca, Pointwise, and Cascade (now branded within Cadence as the Fidelity CFD Platform) as well as Future Facilities (now the Cadence Reality Digital Twin product line) are all adding CFD expertise. The recent addition of Beta CAE brings mechanical multiphysics to the suite of solutions available from Cadence. The full breadth of these multiphysics system analyses, spanning EM, thermal, signal integrity/power integrity (SI/PI), CFD, and now mechanical, creates a platform for digital twinning across a wide array of applications. You can learn more by viewing Cadence's Reality Digital Twin platform launch on the keynote stage at NVIDIA's GTC in March, as well as this Designed with Cadence video: NV5, NVIDIA, and Cadence Collaboration Optimizes Data Centers.

Conclusion

Ever more sophisticated electronic designs are in demand to fulfill the needs of tomorrow's technologies, driving a convergence of electrical and mechanical aspects of multiphysics in system simulations. To successfully produce the exciting new products of the future, both domains must be able to collaborate effectively and efficiently. Cadence is fully committed to developing and providing our customers with the software products they need to enable this electrical/mechanical evolution. From EM, to thermal, to SI/PI, CFD, and mechanical, Cadence is enabling digital twinning across a wide array of applications that are forging pathways to the future.

For more information on Cadence's multiphysics system analysis offerings, visit our webpage and download our brochure.

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

Starting from SPB23.1, a new option, Allow DRCs to surrounding metal, has been added in the Etch-Back form to allow DRCs to the surrounding objects. form to allow DRCs to the surrounding objects.

The Allow DRCs to surrounding metal option lets you see and adjust objects instead of the current behavior, which sacrifices the width of the mask for the trace.

• When this option is turned off, it maintains the EB mask to another object clearance.
• When this option is enabled, it keeps the EB mask to the EM trace edge clearance and shows a DRC if the EB mask to another object spacing is out of rule.

Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup?   

Starting SPB 23.1, a handy feature Transmission Line Calculator, is built into Allegro X Advanced Package Designer (Allegro X APD). This feature will require either an SiP Layout license or can be accessed through SiP Layout Bundle. 

From the Analyze dropdown menu in the 23.1 Allegro X APD toolbar, you can choose Transmission Line Calculator. 

You can use this calculator to help decide constraints and stackup for laminate-based PCB or Packages. You can calculate the correct stackup material and width/spacing to meet any requirements that may be later entered in a constraint. This is truly a calculated number and not a true field solver. 

The different types of calculations that the Transmission Line Calculator can provide are Microstrip, Embedded microstrip, Stripline, CPW (Coplanar), FGCPW (frequency-dependent Coplanar), Asymmetric stripline, Coupled microstrip (Differential Pair), Coupled stripline (Differential Pair), and Dual striplines. 

This feature is important for customers relying on fabricators/spreadsheets to provide this information or need to test a quick spacing/width as per the impedance value. 

Let us know your comments on this new feature in 23.1 Allegro X APD. 

At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net, and it is required to push the new net to all its connected objects. At times, you might update the die or copy routing to other components, when a portion of routing gets the wrong net.

To propagate the net of the pin to all its physically connected objects, Allegro X APD uses the standalone command, Push Connectivity.

You can call the command through Logic > Push Connectivity.

Alternately, you can use the push connectivity command at the command line. Once the command is active, it lets you select pins or symbols that will be used to push net connectivity to all connected objects.

Presently, dynamic shapes and filled rectangles are not considered as part of connectivity. Static shapes are supported.

hello, help me!

There are many change in the bump design. I want to design bump by APD.

The bump(die) is a stagger , create it by die generator. 

Because，the pin is not isometric. In order to RDL routing, so the bump is not isometric.

I move the symbol pin in APD symbol edit（as show in the picture）,  and selected symbol RBM write device file, write library symbol.

Export the bga text( bga text out) ,But the bump is not modified, the bump is still stagger.

Can you help me!

pitch2> pitch1

thanks

The vision manager is good tool for routing check. but no quickly or effective  tool to fix or optimize this  problems to be optimized.

For example, parallel Gap less than preferred, min seg/Arc length,uncoupled diff-pair segs，and so on.

I only know use spread between voids to fix the non-optimized segs. in fact it is inefficient.

the parallel gap less than preferred is only to slice evry trace, its inefficient.

If i set the paraller gap less than 50um, Is there any tool to quickly fix these problems（gap less than 50um）?

For other problems，i can use tool to quickly fix the min seg/Arc length，uncoupled diff pair segs，accoding to select by polygon or select  by windows.

By default, a dielectric must separate each pair of conductor layers in the cross-section of a design. In rare cases, this does not represent the real, manufactured substrate.

If your design requires you to have conductor layers that are not separated by a dielectric (such as, for half-etch designs), there is a variable that needs to be set in Allegro X APD. You must set this by enabling the variable icp_allow_adjacent_conductors. This entry, and its location in the User Preferences Editor, are shown in the following image.

The Objects on adjacent conductor layers do not electrically connect together, automatically. A via must be used to establish the inter-layer connections.

When enabling this option, it is recommended to exercise caution because excluding dielectric layers from your cross-section can lead to inaccurate calculations, including the calculations for signal integrity and via heights. It is important that your cross-section accurately reflect the finished product to ensure the most accurate results possible. Any dielectric layers present in the manufactured part need to be in the cross-section for accurate extraction, 3D viewing, and so on.

Let us know your comments on the various designs that would require adjacent conductor layers.

When working on a complex design, it is common to have very many net ratlines. Quantities like 1000 ratlines are possible. It can result in a cluttered view while routing. Therefore, it is useful to make all other ratlines invisible while routing interactively. You would like to make all ratlines visible again when each route action is completed.

You can easily do this by enabling the Auto-blank other rats option during routing. When enabled, all rats other than the primary ones are suppressed during the Add Connect command.

In SoC development, the verification cycle is a crucial phase that ensures products meet their specifications and function correctly. However, the complexity of modern SoC projects, with their constant data flow, multiple validation teams working in parallel, and tight schedules, presents significant challenges. This article explores these challenges and introduces Verisium Manager as a solution that embodies the 'One Tool Fits All' concept. This means that Verisium Manager is designed to handle all aspects of the verification process for SoC development, from planning to coverage analysis to regression testing, thereby addressing the complex needs of SoC verification.

The Hurdles in Traditional Validation Cycles

 A typical validation process involves planning, coverage analysis, and regression testing. This complexity is compounded by using separate tools for each activity, leading to multiple control environments, APIs, and databases, not to mention the array of tool owners. Such fragmentation results in constant data transfer and translation between systems, from the planning tool to the coverage analysis tool and then to the regression testing tool. This continuous movement of data causes delays, system instability, poor user experiences, and, ultimately, a dip in the quality of the validation process.

The use of multiple platforms leads to inefficiency and reduced productivity. What's needed is a unified system that can streamline the workflow, simplify the verification process, and enhance its effectiveness.

Envisioning the Ideal Solution: Verisium Manager

 The cornerstone of an efficient validation cycle is integration and simplicity. The ideal solution is a singular platform that consolidates planning, coverage analysis, and regression management into one smooth, unified process. Verisium Manager emerges as this much-needed solution, encompassing all the functionalities necessary to streamline the validation process. Its comprehensive nature instills confidence in its ability to handle all aspects of the verification cycle. It can be fully customized to address and enforce any validation methodology and can facilitate smooth integration into any customer environment.

Features that stand out in Verisium Manager include: 

• Unified Workflow: It acts as a single cockpit from which all activities are orchestrated, ensuring the validation teams' work is uninterrupted and seamlessly integrated.
• Customization and Integration: Verisium Manager supports customizing test-plan structures and mapping results per project, ensuring a perfect fit for various project requirements. Its ability to smoothly integrate into the project's environment and compute platforms is unparalleled.
• Support for Continuous Updates and Migration: The tool accommodates constant updates to project data and supports the migration of legacy data, ensuring that no historical data is lost in the transition to a new system.

Addressing Project-Specific Needs

 Verisium Manager recognizes diversity in different projects and offers project-specific solutions, including:

 Enforcing Project Test-Plan Structures and Attributes: It supports and enforces each project's unique test-plan structure and mapping guidelines.

• Unified Data Views and Measurements: Verisium Manager promotes a unified view of data across all teams and enforces unified measurements, ensuring consistency and clarity in the validation process.
• Enabling Project-Specific Actions and Integrations: The tool is designed to support project-specific actions directly from its graphical user interface and allows for smooth integration with in-house databases, dashboards, and the project execution stack.

Verisium Manager is the epitome of efficiency in software/hardware validation. Its differentiating features, such as support for customization, unified data view, and comprehensive coverage and regression requirements, make it an indispensable tool for any validation team looking to elevate their workflow.

As a verification engineer, you’re surely looking for ways to automate the debugging process. Have you developed your own scripts to ease specific debugging steps that tools don’t offer? Working with scripts locally and manually is challenging—so is reusing and organizing them. What if there was a way to create your own app with the required functionality and register it with the tool? The answer to that question is “Yes!” The Verisium Debug Python App Store lets you instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. Join me, Principal Education Application Engineer Bhairava Prasad, for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps, learn about them, install or uninstall them, and even customize existing apps. Date and Time Wednesday, November 20, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within one hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Like this topic? Take this opportunity and register for the free online course related to this webinar topic: Verisium Debug Training To view our complete training offerings, visit the Cadence Training website Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. Related Courses Xcelium Simulator Training Course | Cadence Related Blogs Unveiling the Capabilities of Verisium Manager for Optimized Operations - Verification - Cadence Blogs - Cadence Community Verisium SimAI: SoC Verification with Unprecedented Coverage Maximization - Corporate News - Cadence Blogs - Cadence Community Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput - Verification - Cadence Blogs - Cadence Community Related Training Bytes Introducing Verisium Debug (Video) (cadence.com) Introduction to UVM Debug of Verisium Debug (Video) (cadence.com) Verisium Debug Customized Apps with Python API Please see course learning maps a visual representation of courses and course relationships. Regional course catalogs may be viewed here . *If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help .

This post was contributed by Liliko Uchida, application engineer at Cadence. Being a “Woman in STEM” is a phrase that has long been used to describe the holistic experience shared by thousands of women globally, yet it still makes us feel isolated. Partially due to the statistics of gender population in the STEM workforce and the remainder due to our own internal obstacles, being a woman in STEM continues to be a challenge. While many of us know the should-do’s and should-be’s of taking on this unique role objectively, we struggle to implement them. After all, our perseverance as engineers, mathematicians, businesswomen, programmers, and scientists is largely affected by subjectivity. The UMass Lowell Women’s Leadership Conference 2024 aimed to tackle this problem by uniting hundreds of women with shared experiences under one roof. Not only did the conference provide us with the knowledge necessary to persevere, but it also gave us the tools that will allow us to thrive and act upon the facts we already know. It is my hope that through this blog post, I can share some of my main takeaways from this special day. Be Confident This is one of the most palpable pieces of advice we always hear. Yet so many of us struggle to build this confidence because we don’t know how. Featured speaker Nicole Kalil defined confidence as “complete trust in oneself”.”One way to build this self-trust is by getting to know yourself on a deeper level. By creating a true inner connection, we begin to see ourselves as a whole instead of hyper-focusing on our shortcomings frequently illusioned by imposter syndrome. In one of the sessions, we were asked to introduce ourselves to our neighbors, not by what we do for work, but by who we are as a person. Even if this opportunity does not arise every day, this practice can be done simply by listing characteristics of yourself that define who you are. Who do you care for? How do you show them? What are your life goals oriented towards? How do you observe others’ behavior around you, and what does that say about how you make them feel? Getting to know you beneath the surface and allowing yourself to be seen for who you are is critical in building internal confidence. With practice, this self-reassurance will grow independent of external factors. Take Risks “Sometimes, you have to put your foot in the elevator” - Barb Vlacich, Keynote Speaker When opportunities arise, the only thing you can do to have a chance is to try. Without putting your foot in the elevator, the doors will close, becoming a missed opportunity. Similarly, several of the conference’s speakers also emphasized that the answer to every unasked question will always be a no. Even if you are not ready to full-send a negotiation, ask for a raise, or respectfully disagree with a co-worker’s opinion, start by getting comfortable asking uncomfortable questions. Just one discomfort a day will help in building an immunity to the anxiety that comes with taking risks, typically driven by our self-doubt. Another interesting point that stood out from the conference was the statistics of self-assessed qualifications between men and women. During the negotiation panel, it was revealed that men typically feel they only need 60% of the qualifications under a job description to apply, whereas women often feel they need close to 100%. These numbers alone demonstrate how the pure mental habits of men continue to funnel them into STEM and not women. The next time you seek a new opportunity, assess yourself based on the 60% and use it as a checklist threshold. If more women are able to pursue STEM careers using these numbers, the more likely we will begin to populate these roles. Build Your Genuine Network “ The essence of communication lies in the mutual exchange of ideas and emotions. And when the listener isn’t invested, it undermines the entire purpose of the conversation. Why are you having it anyway?” This is a quote from episode 186 of Julie Brown’s podcast This Sh!t Works called “The 5 Steps to Being an Active Listener”. Julie Brown is a Networking Coach, author, and podcast host who guided an energetic and candid conversation about networking and building a personal brand for women. Networking is often misunderstood as putting your name and qualifications out on the table for as many people to pick up your cards. While making these things known is important, they are not what nurtures effective connections. The key to cultivating your genuine network is to activate a sincere interest in the people you meet. Become the proactive receiver of the confidence exercise discussed above. When you meet someone new, what can you take away from them as a person, not an employee? By making people feel heard, even through the little conversations, you can begin to develop more meaningful connections that resonate. And, with practice, the sometimes inherent need to overcompensate by defining yourself with your resume will slowly fade. It was a wonderful opportunity to attend the UML Women’s Leadership Conference with four other inspiring Cadence women. Not only was the conference a motivating learning experience, but it was also a wonderful opportunity for us to bond together as women and feel supported by each other. The most eye-opening part of the day was seeing just how many women alike were sitting under the same roof. The conclusion of the event led me to feel proud to be an engineer, proud to be at Cadence, and most importantly, proud to be a woman. Learn more about life at Cadence .

On November 5, 2024, the Cadence Bangalore Toastmasters Club celebrated a significant milestone by hosting its 50th meeting. Established in December 2020, the club was created to provide a supportive environment for individuals looking to improve their communication and leadership skills. Over the years, the club has evolved into a vibrant community filled with success stories of personal development and newfound confidence. A testament to the club's dedication is its achievement of the "Select Distinguished Club" status during the 2023-2024 program year. By fulfilling 7 out of 10 distinguished goals, the club highlighted its commitment to excellence—a success driven by its vibrant members' relentless focus and perseverance. The strategic insight gained from regular Toastmasters committee meetings and the influential "Moments of Truth" sessions held in 2023 and 2024 are key to this success. Our club members have consistently demonstrated strong performance in various speech contests, with notable achievements across multiple levels. In 2023, members excelled in Evaluation and Table Topics contests, reaching the district level while advancing to the Division Level in the International Speech Contest. Continuing their success into 2024, members again qualified for area-level contests, securing third-place positions in the Evaluation and Table Topics categories, highlighting the club's dedication and competitive spirit. The 50th meeting was based on the theme of serendipity. It was not only a milestone celebration but also a vibrant festival of achievements and growth. The day buzzed with energy as activities like a spirited Treasure Hunt injected enthusiasm and camaraderie among attendees. Distinguished guests, including Kripa Venkitachalam and Madhavi Rao, enriched the occasion with inspiring speeches. Madhavi reignited the club's spirit, while Kripa's discourse on the Growth Mindset and the "Power of Yet" encouraged members to pursue continuous self-improvement. The Cadence Bangalore Toastmasters Club is enthusiastic about its promising future and is committed to creating an environment that promotes personal and professional growth. Many members are close to completing their Toastmasters levels and pathways, and this term, a new group of approximately 30 individuals has joined, bringing the total membership to 52. This vibrant community is just beginning its journey and is eager to reach new milestones together through mutual support and a shared commitment to excellence. The transformations experienced by many club members are truly compelling. They often share how the club has significantly improved their communication skills and boosted their confidence. One member recalls, "Before joining, I found public speaking intimidating. Now, I embrace every opportunity to share my ideas." Another member highlights how the club's supportive environment helped him overcome his fear of public speaking, propelling his career to new heights. This culture of constructive feedback and continuous improvement has inspired countless members to pursue their dreams with renewed determination and optimism. The Cadence Bangalore Toastmasters Club's journey is a living testament to the power of community and the potential within each of us to grow and achieve greatness. As the club continues to evolve and inspire, it serves as a beacon for those aspiring to transform their skills and seize their moment in the spotlight. Learn more about life at Cadence.

hi,

     I save the waveform file of the oscilloscope as CSV file format.

     Now, I need to use this waveform file as the source of the low-pass filter .

     I searched and read the PSPICE help documents, and did not find any  methods. 

     How to realize it?

     Are there any reference documents or examples?

     Thanks!

When the Arduino Mega2560 is added to the first serial port, the dynamic memory is 2000 bytes, and when the second serial serial is added, the dynamic memory is 4000 bytes. Now I need to add the third Serial serial port. The dynamic memory is 6000 bytes. Due to the many variables in the program itself, the dynamic memory is not enough. Please help me how to save the dynamic memory?

use the DBO function DboLib_RepalceCache to do the job of "Replace cache" 

in order to easy the job ,  type the code below . the code is a wrapper of the function metioned above

set lStatus [DboState]
set lSession $::DboSession_s_pDboSession
DboSession -this $lSession
set lDesignsIter [$lSession NewDesignsIter $lStatus]
set lDesign [$lDesignsIter NextDesign $lStatus]
set lNullObj NULL

set oldLibName [DboTclHelper_sMakeCString "E:\PROJECT_WORKLIB.OLB"]
set newLibName [DboTclHelper_sMakeCString "E:\MCU_PARTS_LIB.OLB"]

#DboLib_ReplaceCache wrapper
proc ReplaceCacheByName {partName} {
    global oldLibName
    global newLibName
    global lDesign
    set lPartStr [DboTclHelper_sMakeCString $partName]
    #set lNewStr [DboTclHelper_sMakeCString $newName]
    $lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1
}

then use the tcl command like below to do the real job :

ReplaceCacheByName "CL10B104KB8NNNC_C12"

This is the 15th installment of The Rationalist, my column for the Times of India.

It’s election season, and promises are raining down on voters like rose petals on naïve newlyweds. Earlier this week, the Congress party announced a minimum income guarantee for the poor. This Friday, the Modi government released a budget full of sops. As the days go by, the promises will get bolder, and you might feel important that so much attention is being given to you. Well, the joke is on you.

Every election, HL Mencken once said, is “an advance auction sale of stolen goods.” A bunch of competing mafias fight to rule over you for the next five years. You decide who wins, on the basis of who can bribe you better with your own money. This is an absurd situation, which I tried to express in a limerick I wrote for this page a couple of years ago:

POLITICS: A neta who loves currency notes/ Told me what his line of work denotes./ ‘It is kind of funny./ We steal people’s money/And use some of it to buy their votes.’

We’re the dupes here, and we pay far more to keep this circus going than this circus costs. It would be okay if the parties, once they came to power, provided good governance. But voters have given up on that, and now only want patronage and handouts. That leads to one of the biggest problems in Indian politics: We are stuck in an equilibrium where all good politics is bad economics, and vice versa.

For example, the minimum guarantee for the poor is good politics, because the optics are great. It’s basically Garibi Hatao: that slogan made Indira Gandhi a political juggernaut in the 1970s, at the same time that she unleashed a series of economic policies that kept millions of people in garibi for decades longer than they should have been.

This time, the Congress has released no details, and keeping it vague makes sense because I find it hard to see how it can make economic sense. Depending on how they define ‘poor’, how much income they offer and what the cost is, the plan will either be ineffective or unworkable.

The Modi government’s interim budget announced a handout for poor farmers that seemed rather pointless. Given our agricultural distress, offering a poor farmer 500 bucks a month seems almost like mockery.

Such condescending handouts solve nothing. The poor want jobs and opportunities. Those come with growth, which requires structural reforms. Structural reforms don’t sound sexy as election promises. Handouts do.

A classic example is farm loan waivers. We have reached a stage in our politics where every party has to promise them to assuage farmers, who are a strong vote bank everywhere. You can’t blame farmers for wanting them – they are a necessary anaesthetic. But no government has yet made a serious attempt at tackling the root causes of our agricultural crisis.

Why is it that Good Politics in India is always Bad Economics? Let me put forth some possible reasons. One, voters tend to think in zero-sum ways, as if the pie is fixed, and the only way to bring people out of poverty is to redistribute. The truth is that trade is a positive-sum game, and nations can only be lifted out of poverty when the whole pie grows. But this is unintuitive.

Two, Indian politics revolves around identity and patronage. The spoils of power are limited – that is indeed a zero-sum game – so you’re likely to vote for whoever can look after the interests of your in-group rather than care about the economy as a whole.

Three, voters tend to stay uninformed for good reasons, because of what Public Choice economists call Rational Ignorance. A single vote is unlikely to make a difference in an election, so why put in the effort to understand the nuances of economics and governance? Just ask, what is in it for me, and go with whatever seems to be the best answer.

Four, Politicians have a short-term horizon, geared towards winning the next election. A good policy that may take years to play out is unattractive. A policy that will win them votes in the short term is preferable.

Sadly, no Indian party has shown a willingness to aim for the long term. The Congress has produced new Gandhis, but not new ideas. And while the BJP did make some solid promises in 2014, they did not walk that talk, and have proved to be, as Arun Shourie once called them, UPA + Cow. Even the Congress is adopting the cow, in fact, so maybe the BJP will add Temple to that mix?

Benjamin Franklin once said, “Democracy is two wolves and a lamb voting on what to have for lunch.” This election season, my friends, the people of India are on the menu. You have been deveined and deboned, marinated with rhetoric, seasoned with narrative – now enter the oven and vote.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 18th installment of The Rationalist, my column for the Times of India.

The man who gave us our national anthem, Rabindranath Tagore, once wrote that nationalism was “a great menace.” He went on to say, “It is the particular thing which for years has been at the bottom of India’s troubles.”

Not just India’s, but the world’s: In his book The Open Society and its Enemies, published in 1945 as Adolf Hitler was defeated, Karl Popper ripped into nationalism, with all its “appeals to our tribal instincts, to passion and to prejudice, and to our nostalgic desire to be relieved from the strain of individual responsibility which it attempts to replace by a collective or group responsibility.”

Nationalism is resurgent today, stomping across the globe hand-in-hand with populism. In India, too, it is tearing us apart. But must nationalism always be a bad thing? A provocative new book by the Israeli thinker Yael Tamir argues otherwise.

In her book Why Nationalism, Tamir makes the following arguments. One, nation-states are here to stay. Two, the state needs the nation to be viable. Three, people need nationalism for the sense of community and belonging it gives them. Four, therefore, we need to build a better nationalism, which brings people together instead of driving them apart.

The first point needs no elaboration. We are a globalised world, but we are also trapped by geography and circumstance. “Only 3.3 percent of the world’s population,” Tamir points out, “lives outside their country of birth.” Nutopia, the borderless state dreamed up by John Lennon and Yoko Ono, is not happening anytime soon.

If the only thing that citizens of a state have in common is geographical circumstance, it is not enough. If the state is a necessary construct, a nation is its necessary justification. “Political institutions crave to form long-term political bonding,” writes Tamir, “and for that matter they must create a community that is neither momentary nor meaningless.” Nationalism, she says, “endows the state with intimate feelings linking the past, the present, and the future.”

More pertinently, Tamir argues, people need nationalism. I am a humanist with a belief in individual rights, but Tamir says that this is not enough. “The term ‘human’ is a far too thin mode of delineation,” she writes. “Individuals need to rely on ‘thick identities’ to make their lives meaningful.” This involves a shared past, a common culture and distinctive values.

Tamir also points out that there is a “strong correlation between social class and political preferences.” The privileged elites can afford to be globalists, but those less well off are inevitably drawn to other narratives that enrich their lives. “Rather than seeing nationalism as the last refuge of the scoundrel,” writes Tamir, “we should start thinking of nationalism as the last hope of the needy.”

Tamir’s book bases its arguments on the West, but the argument holds in India as well. In a country with so much poverty, is it any wonder that nationalism is on the rise? The cosmopolitan, globe-trotting elites don’t have daily realities to escape, but how are those less fortunate to find meaning in their lives?

I have one question, though. Why is our nationalism so exclusionary when our nation is so inclusive?

In the nationalism that our ruling party promotes, there are some communities who belong here, and others who don’t. (And even among those who ‘belong’, they exploit divisions.) In their us-vs-them vision of the world, some religions are foreign, some values are foreign, even some culinary traditions are foreign – and therefore frowned upon. But the India I know and love is just the opposite of that.

We embrace influences from all over. Our language, our food, our clothes, our music, our cinema have absorbed so many diverse influences that to pretend they come from a single legit source is absurd. (Even the elegant churidar-kurtas our prime minister wears have an Islamic origin.) As an example, take the recent film Gully Boy: its style of music, the clothes its protagonists wear, even the attitudes in the film would have seemed alien to us a few decades ago. And yet, could there be a truer portrait of young India?

This inclusiveness, this joyous khichdi that we are, is what makes our nation a model for the rest of the world. No nation embraces all other nations as ours does. My India celebrates differences, and I do as well. I wear my kurta with jeans, I listen to ghazals, I eat dhansak and kababs, and I dream in the Indian language called English. This is my nationalism.

Those who try to divide us, therefore, are the true anti-nationals. We must reclaim nationalism from them.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 20th installment of The Rationalist, my column for the Times of India.

Amit Shah’s induction into the union cabinet is such an interesting moment. Even partisans who oppose the BJP, as I do, would admit that Shah is a political genius. Under his leadership, the BJP has become an electoral behemoth in the most complicated political landscape in the world. The big question that now arises is this: can Shah do for India what he did for the BJP?

This raises a perplexing question: in the last five years, as the BJP has flourished, India has languished. And yet, the leadership of both the party and the nation are more or less the same. Then why hasn’t the ability to manage the party translated to governing the country?

I would argue that there are two reasons for this. One, the skills required in those two tasks are different. Two, so are the incentives in play.

Let’s look at the skills first. Managing a party like the BJP is, in some ways, like managing a large multinational company. Shah is a master at top-down planning and micro-management. How he went about winning the 2014 elections, described in detail in Prashant Jha’s book How the BJP Wins, should be a Harvard Business School case study. The book describes how he fixed the BJP’s ground game in Uttar Pradesh, picking teams for 147,000 booths in Uttar Pradesh, monitoring them, and keeping them accountable.

Shah looked at the market segmentation in UP, and hit upon his now famous “60% formula”. He realised he could not deliver the votes of Muslims, Yadavs and Jatavs, who were 40% of the population. So he focussed on wooing the other 60%, including non-Yadav OBCs and non-Jatav Dalits. He carried out versions of these caste reconfigurations across states, and according to Jha, covered “over 5 lakh kilometres” between 2014 and 2017, consolidating market share in every state in this country. He nurtured “a pool of a thousand new OBC and Dalit leaders”, going well beyond the posturing of other parties.

That so many Dalits and OBCs voted for the BJP in 2019 is astonishing. Shah went past Mandal politics, managing to subsume previously antagonistic castes and sub-castes into a broad Hindutva identity. And as the BJP increased its depth, it expanded its breadth as well. What it has done in West Bengal, wiping out the Left and weakening Mamata Banerjee, is jaw-dropping. With hindsight, it may one day seem inevitable, but only a madman could have conceived it, and only a genius could have executed it.

Good man to be Home Minister then, eh? Not quite. A country is not like a large company or even a political party. It is much too complex to be managed from the top down, and a control freak is bound to flounder. The approach needed is very different.

Some tasks of governance, it is true, are tailor-made for efficient managers. Building infrastructure, taking care of roads and power, building toilets (even without an underlying drainage system) and PR campaigns can all be executed by good managers. But the deeper tasks of making an economy flourish require a different approach. They need a light touch, not a heavy hand.

The 20th century is full of cautionary tales that show that economies cannot be centrally planned from the top down. Examples of that ‘fatal conceit’, to use my hero Friedrich Hayek’s term, include the Soviet Union, Mao’s China, and even the lady Modi most reminds me of, Indira Gandhi.

The task of the state, when it comes to the economy, is to administer a strong rule of law, and to make sure it is applied equally. No special favours to cronies or special interest groups. Just unleash the natural creativity of the people, and don’t try to micro-manage.

Sadly, the BJP’s impulse, like that of most governments of the past, is a statist one. India should have a small state that does a few things well. Instead, we have a large state that does many things badly, and acts as a parasite on its people.

As it happens, the few things that we should do well are all right up Shah’s managerial alley. For example, the rule of law is effectively absent in India today, especially for the poor. As Home Minister, Shah could fix this if he applied the same zeal to governing India as he did to growing the BJP. But will he?

And here we come to the question of incentives. What drives Amit Shah: maximising power, or serving the nation? What is good for the country will often coincide with what is good for the party – but not always. When they diverge, which path will Shah choose? So much rests on that.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Designers have long recognized the need to analyze the reliability of ICs. Two commonly used approaches for performing reliability analysis include calculating the change in device degradation and relying on safe operating checks in circuit simulators. 

With the advent of the ever-increasing use of ICs in mission-critical applications, the need for reliable reliability analysis has become of paramount importance. Over the years, you have been using reliability analysis in Virtuoso ADE Assembler and Virtuoso ADE Explorer to measure and review aging effects, such as device characteristic degradations, model parameter changes, self-heating effects, and so on.

Reliability analysis can be performed using two modes: Spectre native and RelXpert. The reliability analysis analyzes the effect of time on circuit performance drift and predicts the reliability of designs in terms of performance. In ADE Assembler, you can run the reliability simulation for fresh test (when time is zero), stress test (to generate degradation data), and aged test (at specific intervals, such as one year, three years, or 10 years). In the stress test, extreme environmental conditions are used to stress devices before aging analysis.

The following figure shows the reliability simulation flow.

The Reliability Options form has the following four tabs: 

• Basic: Enables you to specify analysis type, aging options, start and stop time of reliability simulation, and options related to device masking, degradation ratio, and lifetime calculation. 

• Modeling: Enables you to choose the modeling type you want to use during reliability simulation. 

• Degradation: Enables you to specify the options to print device and subcircuit degradation information into a .bt0 file. 

• Output: Enables you to specify the degradation reports to be generated and methods to filter degradation results in the reports.

While the Basic and the Output tabs are used by design engineers, the Modeling and the Degradation tabs are primarily used by model developers.

Reviewing degradation reports in text or XML formats can be a tiresome exercise because degradation data can be large and can contain a large number of instances due to advanced technology nodes and post-layout simulations. For you to work effectively and interactively with these reports, the new reliability report is based on the SQLite database, which adds the benefit of improved performance and capabilities of sorting and filtering reliability data using SQLite operators.

As they say, watching this in action might help you more than reading about it, so please take a look at our Training Bytes video channel, which offers many helpful videos on how to run Reliability Analysis in Virtuoso Studio.

All the related videos are linked together in a channel so that you can easily access and watch as many as you like.

Reliability Analysis in Virtuoso Studio

Want to Learn More?

For lab instructions and a downloadable design, enroll for the online training courses of your interest on

Reliability Analysis in Virtuoso Studio vIC23.1 (Online)

 Training is also available as "Blended" or "live" class.

Digital Badge Available

You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal.

Note: Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning and Support Portal.

Do You Have Access to the Cadence Support Portal?

If not, follow the steps below to create your account.

• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
• You will need an email address and host ID in order to sign up.
• If you need help with registration, contact support@cadence.com.

To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

Related Resources

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Niyati Singh

On behalf of the Cadence Training team

At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work.

Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources.

Adrian's excitement soared when he discovered a game-changing solution: Doc Assistant. The cloud-based help viewer, Doc Assistant, ships with all Cadence tools, enabling Adrian to access help resources offline from any machine equipped with the software. This meant Adrian could continue his research and work seamlessly, irrespective of internet availability!

Meeting Cadence users and customers at such events has given us the opportunity to showcase how they can benefit from the diverse features that Doc Assistant offers.

With that note, welcome back to our Doc Assistant A-Z blog series! In Part 1, we explored key features and benefits that our innovative viewer brings to the table. Today, in Part 2, we'll dive deeper into the advanced functionalities and customization options that make Doc Assistant indispensable for its users.

Whether you're looking to streamline your workflow or enhance your user experience, this blog will provide the insights you need to fully leverage the capabilities of our documentation viewer. Let’s get started!

What Makes Doc Assistant Stand Out?

Here are a few (more) cool features of Doc Assistant!

That's not all. We have more coming your way. Until next time, take care and stay tuned for our next edition!

Want to Know More?

For any questions or general feedback, write to docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

-Priya Sriram, on behalf of the Doc Assistant Team

Read this blog to know more about the innovation behind Universal Connect Modules (UCM).(read more)

Welcome back to the Doc Assistant A-Z blog series!

Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting.

Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying the tool and feature changes across multiple releases. He shared with me that he has been using Doc Assistant’s capabilities to help him achieve this.

Ralf explained that he utilizes Doc Assistant to open and compare documents from different releases side-by-side, seamlessly tracking updates across multiple releases and verifying those updates in his Cadence tools. Additionally, in Doc Assistant’s online mode, he compares documents across previous tool versions, ensuring a thorough review of any changes. Finally, he was happy to share with me that Doc Assistant features have helped him significantly reduce the time he spends on identifying such changes.

You, of course, can also achieve such productivity gains using several Doc Assistant features designed to help simplify such tasks!

In previous editions of this blog series, we looked at some key features and benefits of Doc Assistant. If you've missed these editions, I would highly recommend that you read them:

• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 1
• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 2
  

In this third installment, we're diving into some more of Doc Assistant's key capabilities.

To learn more about how to use the above features, check out the Doc Assistant User Guide.

These are just a few of the productivity gain features in Doc Assistant. We’ll cover more in the next blog in the series.

Want to Know More?

If you have any feedback on Doc Assistant or would like to request more information or a demo, please contact docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

- Priya Sriram, on behalf of the Doc Assistant Team

The default position of the pin number is incorrect.

How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?

I'm completely new to Cadence. I've been able to run a very simple simulation with the -gui option. Simvision opens, I add the variables to the waveform viewer, and press run. All is good.

I don't understand the flow when using the -nogui option. It appears that the simulation runs and returns control to the OS. When I launch Simvision, is there a database or file that I can open to display the already-simulated data?

My command is of the form:

xrun -gui -64bit -sv -access +rwc -top tb_top.sv <src files>

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

Hi, I'm using the xcelium simulator to simulate a testbench, in which I first stimulate my design to do something (part "A") and then do a direct follow-up test on the design (part "B").

I need two things from this testbench: the results of the test (part "B", passed/failed) and coverage information, but the coverage information should only include part A and explicitly not part B.

I could do the following: run the testbench with part A and B, get the "passed/failed" result of the test and then follow up another simulator run with another testbench, that only includes part A and get the coverage information from that simulation run.

Is there a way to force xcelium to give me the coverage information of only a part of the simulation? Ideally, I would like to write the verilog code of my testbench to look something like this:

• do A
• dump coverage information
• do B

But maybe there is another way to tell xcelium to consider only part of the testbench for the coverage information. I did have a look at the manual, but was not able to find something useful for this problem. Any ideas?

I am running simulation in gui mode using Indago and every time there is UVM_ERROR occur simulation stops. I have to resume it manually. is there any way to disable this feature. 

When posting code to the forums, copy from a text editor such as notepad, not from word or Outlook. Be sure to click the HTML tab BEFORE you paste your text.

Click on the "html" mode tab on your "reply" dialog box. Then wrap your text with like this:

pasted text

NOTE: Do not put a space in the I have done that here so it will show up as text. Also, be sure to click the HTML tab BEFORE you paste your text. This is how it will look when coded correctly pasted text

Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more)

By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more)

The Allegro PCB Editor Basic Techniques course provides all the essential training required to start working with Allegro® PCB Editor. The course covers all the design tasks, including padstack and symbol creation, logic import, constraints setup...(read more)

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro