DOVER, Del. (September 4, 2024) – The Delaware Office of Highway Safety (OHS), Delaware State Police, and local law enforcement are partnering to conduct a Driving Under the Influence (DUI) Checkpoint on Friday, September 6, 2024, in the Milford area. This is the first DUI Checkpoint in Delaware since 2019. The use of checkpoints was […]

DOVER, Del. (September 13, 2024) – The Delaware Office of Highway Safety (OHS), Delaware State Police, and local law enforcement partnered to conduct a Driving Under the Influence (DUI) Checkpoint on Friday, September 6, 2024, in the Milford area from 10:00 p.m. – 2:00 a.m.   Checkpoint Results: Total cars through checkpoint: 340 DUI arrests: […]

On Saturday, October 5, 2024 at 10:30am, the Delaware Public Archives will present a new offering, “Tales from the Vaults,” that will present four unique spooky stories culled from the collections of the Delaware Public Archives. “We’re excited to share this special thematic Saturday event to the public,” said Stephen Marz, State Archivist and Delaware […]

On August 11, 2011 Governor Jack Markell signed House Bill 123, which proclaimed the month of October to be Disability History and Awareness Month in Delaware.  The bill encourages all schools during the month of October to provide instruction and events focusing on disability history, individuals with disabilities and the disability rights movement.  The Governor’s […]

DEPARTMENT OF JUSTICE: Fraud and Consumer Protection Division

Read the in depth Review of ZOTAC GAMING GeForce RTX 3080 Ti AMP Holo Graphics Card PC Components. Know detailed info about ZOTAC GAMING GeForce RTX 3080 Ti AMP Holo Graphics Card configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of NVIDIA GeForce RTX 3070 Ti Graphics Card PC Components. Know detailed info about NVIDIA GeForce RTX 3070 Ti Graphics Card configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Xiaomi 11i Hypercharge 5G Mobile Phones. Know detailed info about Xiaomi 11i Hypercharge 5G configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of NVIDIA GeForce RTX 4090 Graphics Card PC Components. Know detailed info about NVIDIA GeForce RTX 4090 Graphics Card configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of GIGABYTE GeForce RTX 4070 Ti AERO OC 12G Graphics Card PC Components. Know detailed info about GIGABYTE GeForce RTX 4070 Ti AERO OC 12G Graphics Card configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of NVIDIA GeForce RTX 4070 Graphics Card PC Components. Know detailed info about NVIDIA GeForce RTX 4070 Graphics Card configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router Networking. Know detailed info about TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

NA

The International Institute of Forecasters and SAS® are funding two $10,000 grants to support research on forecasting. Per the announcement: For the eighteenth year, the IIF, in collaboration with SAS®, is proud to announce financial support for research on improving forecasting methods and business forecasting practice. The award for this year will be [...]

The post SAS/IIF Research Grants (proposals due October 1) appeared first on The Business Forecasting Deal.

Having the right data analytics platform can help law enforcement solve crimes faster.

The post 5 technology considerations for law enforcement appeared first on The Data Roundtable.

Xiaomi has recently shown off a demo for their HyperConnect feature, allowing users to share files with Apple users.

The post Xiaomi plays nice with Apple with its new HyperConnect feature appeared first on Phandroid.

IFTTT (If This Than That), a web-based software that automates and connects over 600 online services/software raised a $24M Series C led by Salesforce. Other investors include IBM and the Chamberlain Group and Fenox Venture Capital.

The latest round brings IFTTT’s funding to $63M and it will use the funding proceeds to provide integration for enterprise and IoT services and hiring. In IFTTT’s platform, applets are code/script users need to deploy to integrate two or more services (such Google Drive’s integration with Twitter/Facebook).

Investment in IFTTT reveals that Salesforce is consolidating its presence in enterprise IoT space. It also acquired Mulesoft, an integration platform that rivals Microsoft’s BizTalk.

IBM’s investment in IFTTT is also noteworthy as the former is pushing its IBM Watson IoT platform. The following statement also shows its keen interest in IFTTT.

Other recent investments in IoT companies include $30M Series B of Armis and Myriota's $15M for its IoT satellite-based connectivity platform.

For latest IoT funding and product news, please visit our IoT news section.

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

[spotlight] Highly effective treatments for HIV have existed since the mid-1990s. But while these treatments keep people healthy, we do not yet have a safe and scalable way to completely rid the body of the virus. In this Spotlight special briefing, Elri Voigt takes stock of where we are in the decades-long search for an HIV cure.

Hi everyone. 

I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence skills.

I have some digital decision logic. Some are combinational logic, some are sequential logic that I would like to import or generate random input combination to the inputs of my decision logic to get the maximum, minimum, and average delay power dissipation and area when feeding the different input combination.

My logic has 8-bit, 16-bit, and 32-bit input. The imported data tends to be decimal numbers.

I would like to ask you:

- which tool(s) are the most appropriate to import and feed the different combination to my decision logic?

- which tool is the most appropriate to synthesis with different number of input? - I have used Genus Synthesis Solution so far. However with my skill right now I can only let Genus synthesize my Verilog code one setup at a time. I'm not sure if I there is anyway I can feed a lot of input at a time and get those results (min, max, average of delay, power dissipation and area)

- which language or scripts I should pick up to use and achieve these results?

-where can I find information to solve my problem? which information shall I look for?

Thank you so much for your time!!

Best Regards

Hi All,

I'm using a code (abConvertPolygonToPath.ils) that I found in other posts to convert a rect object to a path object inside a pcell code, but when I try to run a DRC, the layout export fails due to a warning message, here is the log message

*WARNING* (DB-270001): Pcell evaluation for 18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout has the following error(s):

*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" abConvertPolygonToPath))

ERROR (XOASIS-231): Pcell evaluation failed for '18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout' because the Pcell SKILL code contains either a syntax error or an unsupported XOasis function. Check the standard output or the Virtuoso log file for more information. Cadence recommends correcting the Pcell SKILL code to resolve the issue. However, to ignore these errors and continue the translation, you may use the 'ignorePcellEvalFail' option.

INFO (XOASIS-282): Translation Failed. '1' error(s) and '3' warning(s) found.

And when compile the code I get the following message:

*WARNING* defgeneric function already defined - abConvertPolygonToPath

I will aprreciate any help in how to waive this error, or fix it.

Thank you

This document resolved my first query,

Article (11638952) Title: How to output power and ground nets to GDS
URL: support.cadence.com/.../ArticleAttachmentPortal

but now I have 20 power and 20 ground

below is my code

------------------------------------------------
variable GND "vss1" "vss2" "vss3" ... "vss20"
variable VDD "vdd1" "vdd2" "vdd3" ... "vdd20"

select_net M1 GND -outputlayer GND_M1
select_net M2 GND -outputlayer GND_M2
...
select_net AP GND -outputlayer GND_AP

select_net M1 VDD -outputlayer VDD_M1
select_net M2 VDD -outputlayer VDD_M2
...
select_net AP VDD -outputlayer VDD_AP

rule GND{

copy GND_M1
copy GND_M2
...
copy GND_AP}

rule VDD{

copy VDD_M1
copy VDD_M2
...
copy VDD_AP}
------------------------------------------------

I want 20 GND and 20 VDD are separately to highlight,
like this

Can DRC command use for-loop(skill or Tcl) to split the rule?
or how can I do to split it? 
I don't really want to repeat the rule 40 times..haha😅 (use Pegasus 22.21)

Good morning,
I dug up an old project from 2005 and I should open the schematic to check some things.
This is the schematic of a XILINX XC95108-pq160 CPLD which the XILINX ISE 6.1 software then translated and compiled, to generate a JEDEC file to burn CPLD.

My problem is that I can't open schematics with the versions of Orcad Schematic Entry that I have.
Can anyone help me understand which version of Orcad Schematic Entry I need to install to see these files?

I shared the files on:
drive.google.com/.../view

Thank you very much

Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..

OrCAD X is the next-generation integrated PCB design platform. It brings to you a powerful cloud-enabled design solution that includes design and library data management integrated with the proven PCB design and analysis product portfolio of Cad...(read more)

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.

The OrCAD X and Allegro X 24.1 release is now available at Cadence Downloads. This blog post provides links to access the release and describes some major changes and new features.   OrCAD X /Allegro X 24.1 (SPB241) Here is a representative li...(read more)

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

Live Doc is an advanced automated PCB documentation generation tool integrated with OrCAD X Presto designed to streamline the creation of PCB documentation. By automating the generation of PCB fabrication and assembly drawings, Live Doc significantly...(read more)

Starting from SPB23.1, a new option, Allow DRCs to surrounding metal, has been added in the Etch-Back form to allow DRCs to the surrounding objects. form to allow DRCs to the surrounding objects.

The Allow DRCs to surrounding metal option lets you see and adjust objects instead of the current behavior, which sacrifices the width of the mask for the trace.

• When this option is turned off, it maintains the EB mask to another object clearance.
• When this option is enabled, it keeps the EB mask to the EM trace edge clearance and shows a DRC if the EB mask to another object spacing is out of rule.

hi,

     I save the waveform file of the oscilloscope as CSV file format.

     Now, I need to use this waveform file as the source of the low-pass filter .

     I searched and read the PSPICE help documents, and did not find any  methods. 

     How to realize it?

     Are there any reference documents or examples?

     Thanks!

Hi,

i am compiling firmware under Windows transfer the binaries and the sources to Linux to simulate/debug there. The problem is that the paths in the DWARF debug info of the .elf file are the absolute Windows paths as set by the compiler so they are useless under Linux. Is it possible to configure mappings of these paths to the Linux paths when simulating/debugging like with e.g. GDB (https://sourceware.org/gdb/current/onlinedocs/gdb/Source-Path.html#index-set-substitute_002dpath)?

thx,

Peter

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

Hi,

So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. 
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.

Thank you all.

Hi,

I have a monitor plugged to my laptop using a HDMI to USB adapter. When using this adapter, Allegro runs very slowly. It seems that it is not using my video card.

Is this a known issue with a workaround I can try?

Thanks,

Michael

Hello..

I'm updating part in part editor in orcad capture, and I wonder how to align pin numbers using menu or tcl/tk command.

Please, let me know. Thank you.

Hi All

I am looking for the functions which are different about OrCAD Professional and Allegro tier.

is there any resource?

regard

The default position of the pin number is incorrect.

I have managed to convert our old schematic and PCD file to from Layout 16.2 to 17.4

I have exported the footprints and moved them to the correct lib directory. 

I get no DRC errors and I can build a new netlist file. The problem is I can't get the PCB editor to update using the new netlist and get the following error:

I cannot figure out how to fix the Name is too long error. 

(---------------------------------------------------------------------)

(                                                                     )

(    Allegro Netrev Import Logic                                      )

(                                                                     )

(    Drawing          : 70055R2.brd                                   )

(    Software Version : 17.4S023                                      )

(    Date/Time        : Tue Dec 14 18:54:25 2021                      )

(                                                                     )

(---------------------------------------------------------------------)

------ Directives ------------

Ripup etch:                  Yes

Ripup delete first segment:  No

Ripup retain bondwire:       No

Ripup symbols:               IfSame

Missing symbol has error:    No

DRC update:                  Yes

Schematic directory:         'C:/AFS/70055 PCB Test 2'

Design Directory:            'C:/AFS/70055 PCB Test 2'

Old design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'

New design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'

CmdLine: netrev -$ -i C:/AFS/70055 PCB Test 2 -x -u -t -y 2 -h -z -q netrev_constraint_report.xml C:/AFS/70055 PCB Test 2/#Taaaaae57776.tmp

------ Preparing to read pst files ------

Starting to read C:/AFS/70055 PCB Test 2/pstchip.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstchip.dat (00:00:00.02)

Starting to read C:/AFS/70055 PCB Test 2/pstxprt.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstxprt.dat (00:00:00.00)

Starting to read C:/AFS/70055 PCB Test 2/pstxnet.dat 

   Finished reading C:/AFS/70055 PCB Test 2/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------

#1   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#2   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_S' has library errors. Unable to transfer to Allegro.

#3   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#4   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW' has library errors. Unable to transfer to Allegro.

#5   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW' has library errors. Unable to transfer to Allegro.

#6   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_DP' has library errors. Unable to transfer to Allegro.

#7   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB15_DSUBVPTM15_CONNECTOR DB15': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB15_DSUBVPTM15_CONNE' has library errors. Unable to transfer to Allegro.

#8   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB9_DSUBVPTM9_CONNECTOR DB9': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB9_DSUBVPTM9_CONNECT' has library errors. Unable to transfer to Allegro.

#9   ERROR(SPMHNI-175): Netrev error detected.

ERROR(SPMHDB-195): Error processing 'M6': Text line is outside of the extents..

------ Library Paths ------

MODULEPATH =  . 

           C:/Cadence/SPB_17.4/share/local/pcb/modules 

PSMPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_17.4/share/local/pcb/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

PADPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_17.4/share/local/pcb/padstacks 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 

           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

------ Summary Statistics ------

#10  Run stopped because errors were detected

netrev run on Dec 14 18:54:25 2021

   DESIGN NAME : '70055R2'

   PACKAGING ON Nov  2 2021 14:32:04

   COMPILE 'logic'

   CHECK_PIN_NAMES OFF

   CROSS_REFERENCE OFF

   FEEDBACK OFF

   INCREMENTAL OFF

   INTERFACE_TYPE PHYSICAL

   MAX_ERRORS 500

   MERGE_MINIMUM 5

   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'

   NET_NAME_LENGTH 24

   OVERSIGHTS ON

   REPLACE_CHECK OFF

   SINGLE_NODE_NETS ON

   SPLIT_MINIMUM 0

   SUPPRESS   20

   WARNINGS ON

 10 errors detected

 No oversight detected

 No warning detected

cpu time      0:00:27

elapsed time  0:00:00

When using Shape > Create Bounding Shape on an arc, the outer side works well, but on the inner side it just draws a straight line from the begging to the end of the curve.  Is anyone aware of a fix for this?

I'm attaching  a picture as an example, it works great on lines.

Hello All,

I'm a novice to this forum and probably this subject has been already discussed here.

My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.

However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.

Does anybody have opinion on this issue?

Many thanks,

Pavel

hello,

We have a number of workstations with version 17.2 that work on a floating license server

We want to know if it can be upgraded to version 17.4

If so, should the floating license server be upgraded as well?

In addition, how can you know where the license was purchased from?

Thanks!

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

Hi,

I'm searching for a way to get a quick overview of too low cpk-values after a montecarlo sim. The non-MC results have the spec and thus the easy/understandable red/green/(yellow) colorcoding, but for MC sims I don't get a highlight for high variations inside the limits.

Is this possible (besides copying each expression into avg()+3*std()) and ..-..)?

It would be really handy to scan through finished sims...

(My final application is then to export the table for my reports and documentation...)

Regards,

leo

Hi

I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell?  I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain.  I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again.  I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it.  Is there a way to "break" the features of XL like this?  I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.

Thanks

Chris

Hi,

Current and valid TCAs for Functional Safety are readily available at the FuSa "one-stop shop".

But I have not been able to find any archive repository for access to the obsoleted versions.

I would need to have also v1.4 of Xcelum TCA to investigate exact changes wrt previous projects.

Anyone knows how to find it?

Best regards,  Lars