How do we purge/remove the duplicated vias in the same location of the PCB editor? These vias are not the one stacked and they are just blind vias running in internal layers 12-14. I find there is an additional copy of the blind via at the same location. Not sure what caused this issue.

Hi All

I am looking for the functions which are different about OrCAD Professional and Allegro tier.

is there any resource?

regard

Hello. I am using Cadence 17.4 tools. When I open a package symbol (.dra) or board file (.brd) in Allegro that was created in an older version of the tool I get a message like this one (as expected):

"The design created using release 17.2 will be updated for compatibility with the current software..."

If I create a symbol or board file from scratch in the 17.4 tool then open it later, I get the same message. (always referring to version 17.2 which is the previous version I was using here).

So far this has not caused me any problems, but I would like to understand why it is doing this in case I have something setup incorrectly.

I only have version 17.4 installed. I am not exporting to a downrev version when I save (i.e. not using File->Export->Downrev design…) and in User Preferences->Drawing I don’t have anything selected for database_compatibility_mode. What else might I check?

FYI here is the tool version information that I see after selecting Help->About Symbol:

OrCAD PCB Designer Standard 17.4-2019 S012 [10/26/2020] Windows SPB 64-bit Edition

Thanks -Jason

Hello All,

I'm a novice to this forum and probably this subject has been already discussed here.

My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.

However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.

Does anybody have opinion on this issue?

Many thanks,

Pavel

How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?

Hi,

I'm searching for a way to get a quick overview of too low cpk-values after a montecarlo sim. The non-MC results have the spec and thus the easy/understandable red/green/(yellow) colorcoding, but for MC sims I don't get a highlight for high variations inside the limits.

Is this possible (besides copying each expression into avg()+3*std()) and ..-..)?

It would be really handy to scan through finished sims...

(My final application is then to export the table for my reports and documentation...)

Regards,

leo

Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly.

I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below:

I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps.

Thanks and regards

Anubhav Agarwal

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

First time user of JasperGold. Chip level verif. I want to prove that an arbiter and a buffer are connected. I want to use the connectivity app to do that.

I see from the user guide, that I should provide a connectivity map, but i have no idea how to construct one.
The training videos said use this command: check_conn -generate_template jasper_template.xlsm -xlsm
But that did nothing, or at least it did not produce a file that i could find

[<embedded>] % check_conn -generate_template jasper_template.xlsm -xlsm
ERROR (ESW104): Invalid command formation.
Problem occurs with "-generate_template -xlsm".

And even if it did, I don't even know what's in the file, and whether it contains the two ips I'm trying to check.

I'm hoping someone can give me a bit of a boost here with some knowledge.

Hi,

Current and valid TCAs for Functional Safety are readily available at the FuSa "one-stop shop".

But I have not been able to find any archive repository for access to the obsoleted versions.

I would need to have also v1.4 of Xcelum TCA to investigate exact changes wrt previous projects.

Anyone knows how to find it?

Best regards,  Lars

Please include a brief summary of how to use it.

Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
. There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

Please contact me for any help.
Regards ANil

Join this insightful on-demand webinar event "SI/PI Simulation and Measurement Correlation Forum" available through Signal Integrity Journal that features industry expert presentations ranging from chip to package to complex board designs.(read more)

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2022.1 HF2 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2022.1 HF2 release, see the README.txt file in the installation hierarchy.(read more)

The silkscreen layer plays a crucial role in the assembly, repair, and testing of a PCB. You can add a variety of information to this layer, such as the location of the components, polarity, component orientation, on-off switches, LEDs, and testpoint...(read more)

The Allegro PCB Editor Basic Techniques course provides all the essential training required to start working with Allegro® PCB Editor. The course covers all the design tasks, including padstack and symbol creation, logic import, constraints setup...(read more)

Hi,
My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2
I plot an eye diagram using a built in function. I want to see the data-dependent jitter. I want to measure the eye diagram edges at zero crossing (width of that diamond part) shown in the pic by vertical and horizontal markers. I can put a marker and read the numbers there and get what I want. But now I want to run Monte Carlo and I can't do this for all samples. I wish I could write an expression for this. Unfortunately, I see that the function "cross" is not working on the eye diagram. Basically, when I send the eye diagram data to a table, I see that it actually is just the prbs data and not the eye diagram data. Is there a hack that can help me achieve my goal which is: having an expression to measure the edges of the eye diagram at zero crossing?
There is a script that Andrew wrote (https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11395772). This is a good script but it puts all edges on top of each other. I want to distinguish the two edges. In the attached pic (two-period eye diagram) you can see what I mean by the two edges (diamond shapes). I want to measure each of the two and take the maximum. Having all the edges on top of each other won't give me what I want. All edges together will lso include DCD. I purely want to measure DDJ. DCD is measured separately. I have very little experience with writing scripts and could not modify Andrew's script.
Your help is much appreciated. Thank you.

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more)

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this blog.(read more)

I want to make an opening in the solder mask right above a trace that is acting like a guard ring. Do I really need to go and buy the Allegro Productivity Toolbox add-on for using the Cross-Copy tool for a basic operation like that??

/F

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

A more appropriate title for this blog could be “All Vehicles with ADAS Need the Midas Functional Safety Platform”.

EVs tend to have advanced driving assistance systems (ADAS) because they’re newer, but not all vehicles with ADAS are EVs!

Certifying Advanced Driver Assistance Systems (ADAS) is a multifaceted process involving rigorous testing, validation, and regulatory compliance to ensure safety and reliability.
As ADAS technologies become increasingly sophisticated, the certification process is evolving to meet these challenges.

The ISO26262 standard provides the requirements to be met to attain safety certification for digital designs.

One of the key aspects of ADAS certification is functional safety. This includes:

• Ensuring the system operates as intended under all conditions, including failures.
• Adherence to standards like ISO26262.
• Rigorous testing to identify potential hazards and mitigate risks.

The Midas Safety Platform provides early-phase exploration of functional safety architectures and leverages native chip design data to perform accurate safety analysis efficiently.

The platform is a unified solution available across Cadence products, and with its modular architecture, it supports both embedded and standalone usage with the Cadence flow.

After extracting the design information, an output Midas database file contains the isolated DUT and provides the design components and their fault tolerances to various tools in the flow.

Conformal can easily verify design transformations that include necessary components like TMR for safety.

In these videos, we explore how to create reports for both Transient and Permanent faults.

Creating Detailed FMEDA in Midas (Video)

Creating Architectural FMEDA in Midas (Video) 

Also, read this blog post for additional motivation: What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

What Next?

Join the Midas Safety Platform Introduction and the Functional Safety Implementation and Verification with Midas trainings and learn more about:

• Setting up and defining the USF file
• Using the Midas Safety Platform to create functional safety reports, and
• Midas integration with the Genus  Synthesis Solution, Innovus  Implementation System, and Conformal Equivalence Checker tools to implement functional safety

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

If you want to make sure you are always the first to know about anything new in training, then you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Singapore has retained its place at the top of fDi's Asia-Pacific Cities of the Future ranking, with Shanghai and Tokyo completing the top three list. 

Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders.

Kenya’s cabinet secretary for the national treasury and planning, Ukur Yatani, discusses the country’s agenda of fiscal reforms and the importance of constructing an east-west Africa highway.

The UN Sustainable Development Goals aim to end global poverty, but poorer countries are struggling to hit them. More help from richer countries is crucial, writes Mazdak Rafaty.

What if the coronavirus lasts until the end of the year? Lawrence Yeo has a bleak forecast.

Authorities in the US, the EU and across the developed world are stepping up efforts to scrutinise foreign investment on the grounds of both national security and tech sovereignty.

London is crowned best major city in Europe in fDi's FDI Strategy category, with Glasgow, Vilnius, Reykjavik and Galway also winning out.

Serbia’s technology cluster is gaining momentum and attracting FDI, for both its software and hardware expertise.

Despite its thriving automotive sector, Gothenburg is vulnerable to global economic pressures. However, local authorities are confident that their strategies will see the city ride out the uncertainties related to Brexit and the US-China trade wars.

Passion Capital's Eileen Burbidge talks to fDi about what fintech companies should consider when expanding internationally, and why London will always be a key market in the sector.

FDI levels have already fallen throughout Iran's main sphere of influence in the region. 

Announced greenfield projects into China plummeted in early 2020 with the US and Europe taking the lion's share of global foreign investment. 

AstraZeneca will set up a R&D centre and an AI innovation centre in Shanghai, as well as create a $1bn fund that would invest in healthcare start-ups.

Asia outstrips the world for tourist arrivals and is still experiencing growth. Constant maintenance and upgrade are essential to maintain this lead.

German chemical giant BASF has begun construction of its $10bn mega project in southern China, which will be the country’s first wholly foreign-owned chemical complex. 

China's coronavirus outbreak is having a seismic effect in Asia and beyond, writes Lawrence Yeo.

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 

Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf.

Up to 18 countries across Latin America have joined China’s new Belt and Road Initiative, hoping to boost their infrastructure development and investment.  

Marcelo Eduardo Arze García, Bolivia’s vice minister of tourism, tells Sebastian Shehadi why tourists are turning their attention to one of South America's less explored destinations. 

The UAE followed Singapore’s swift reaction to combat Covid-19, to preserve the health of its citizens. Now moves are in place to tackle the country’s economic wellbeing.

The coronavirus pandemic could change human behaviour more permanently in future.

Once the powerhouse of the industrial US, the rust belt states have revived their economies with the help of foreign investment. 

Consulting firms in the Middle East are likely to take a hit in 2020 due to the coronavirus, after two strong years.

The pandemic is likely to hit the Middle East’s more fragile countries hardest.