On September 2 (3pm UTC / 11am EDT), I'll be joining Jonathon Karelse, CEO of NorthFind Management, for an interactive "fireside chat" on the application of Behavioral Economics in demand planning. This is part of the Foresight Webinar Series, and registration is free. Since we first met at an Institute [...]

The post Behavioral economics in demand planning (webinar September 2) appeared first on The Business Forecasting Deal.

Fight back against sophisticated money launderers with these 3 techniques.

The post 3 techniques to improve AML transaction monitoring strategies appeared first on The Data Roundtable.

Abdul Ghafoor Noorani, eminent constitutional expert, lawyer and author, died today at the age of 93. A noted scholar on Jammu and Kashmir, his absence is being felt in the Union Territory, where many are mourning him.

An Indian-origin real estate developer and film producer has purchased 'Friends' star Matthew Perry's Los Angeles home.

1. Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
2. Mahavatar First Poster: Vicky Kaushal Takes On The Role Of "The Eternal Warrior Of Dharma"- Parashurama  NDTV Movies
3. Vicky Kaushal drops powerful FIRST LOOK as Lord Parashurama for ‘Mahavatar’  TOI Etimes
4. entertainment News Live Today November 13, 2024: Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
5. Vicky Kaushal to play Chiranjeevi Parashurama in Amar Kaushik’s Mahavatar  India Today

1. Stock market today: Trade setup for Nifty 50 to Q2 results today; five stocks to buy or sell on Wednesday — Nov 13 | Stock Market News  Mint
2. Sensex, Nifty50 decline for 5th straight session; now down over 9% from peak  Mint
3. Indices trade with deep cuts; auto shares decline for 5th day  Business Standard
4. Stock Market LIVE Updates: Nifty at 23,700, Sensex tanks 520 pts; auto, metal, realty major drag  Moneycontrol
5. GIFT Nifty down 45 points; here's the trading setup for today's session  The Economic Times

1. Has AIMIM’s Owaisi, the dark horse in Maharashtra elections, played a winning move?  Hindustan Times
2. Video | Maharashtra Election Will Throw Up Fractured Mandate: A Owaisi's Party Leader  NDTV
3. Owaisi backs Maratha reservation ahead of Maharashtra Assembly polls  India Today
4. Need to fight unitedly by Muslims, Maratha and Dalits: Barrister Owaisi.  Etemaad
5. No one can say Uddhav Thackrey won't go back to BJP: AIMIM  The Times of India

Xiaomi has recently shown off a demo for their HyperConnect feature, allowing users to share files with Apple users.

The post Xiaomi plays nice with Apple with its new HyperConnect feature appeared first on Phandroid.

The iPad Mini 7 is an impressive tablet, but there are some compromises that might be a deterrent for potential buyers.

The post iPad Mini (2024) Review: Imperfect, but Impressive appeared first on Phandroid.

If you're an iPhone user, then you might want to check the Chrome app for new updates.

The post Google Adds Some Nifty Features for Chrome on iOS Devices appeared first on Phandroid.

In a unique online romance scam, a man in Tianjin, China, fell victim to a bizarre "marriage bed burning" ritual, costing him Rs 11 lakh.

Atlas Biomed's website is no longer active and the phone number listed is dead as well.

A guidance has been issued to the wealthier students with a list of actions they need to follow to create an inclusive environment.

The $20 Merry Multiplier scratch-off ticket she chose turned out to be a $250,000 top prize winner.

Smart baby monitor company Nanit raised a $14M Series B round led by Jerusalem Venture Partners (JVP). Other investors that participated include existing investors Upfront Ventures, RRE Ventures, Vulcan Capital and Vaal Investment Partners. The latest investment brings total equity funding of Nanit to $30M.

Nanit announced it will use the funding proceeds to expand its team of computer vision and machine learning engineers and grow its sales in Europe and Canada.

Nanit’s baby monitor helps new parents oversee nursery conditions as it has built-in temperature and humidity sensors. The camera lets parents remotely monitor baby’s crib whereas sound and motion are detected via smart sensors.

The monitor’s insights can be accessed via an accompanying mobile app. Nanit charges $10 per month for its premium package.

The key use cases of Nanit’s baby monitoring technology include sleep insights, behavioral analysis, expert guidance, and nightly video summaries. The company currently sells its smart monitors via its website.

[SAnews.gov.za] Twenty-three people in Gauteng have died as a result of food borne-related poisoning after consuming food from spaza shops.

[State Department] U.S. Ambassador-at-Large to Monitor and Combat Trafficking in Persons Cindy Dyer will travel to Madagascar November 13-16 and South Africa November 17-21.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

Hello,

When I draw a Fluid Guard Ring in Virtuoso, the layout is not visible, and instead, "do_something=nil" appears.

When I check the details with Q, it shows the same information as a regular NFGR guard ring, and Ctrl+F also displays the instance name, just like with a regular NFGR. 

Additionally, the Pcells of Fluid Guard Rings from previous projects appear broken. 

The version I’m currently using is not different from the one used in the past. Even when I access the same version as the one used during the project, the Pcells still appear broken.

These two issues are occurring, and I’m not sure what to check. I would greatly appreciate it if you could assist me in resolving this issue.

//

Hello Community,

I have encountered an issue that is a mystery to me and hope somebody could give me a clue about what is happening in Cadence and maybe even a solution?

I am running a test scripted in a SKILL file that sequentially opens two different projects with MC analyses and in between I get an error message box and also multiple logs in CIW with exactly the same text.

Both projects run a simulation with a call like this:

historyName = maeRunSimulation(?session sessionName ?waitUntilDone t)

After this the script closes the current project, opens the next project and executes the same line with maeRunSimulation() for the second project. Then immediately this error message happens, and also is logged repeatedly in the CIW window

The message box looks like this:

The logs I get in CIW:

nil
hiCancelProgressBox(_axlNetlistCreateProgressBar)
nil
hiCancelProgressBox(_axlUILoadForm)
nil
when(dwindow('axlDataViewessWindow1) hiMapWindow(dwindow('axlDataViewessWindow1)))
t
when(dwindow('axlRunSummaryessWindow1) hiMapWindow(dwindow('axlRunSummaryessWindow1)))
t
ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.
You can only modify an ADE Assembler session that is active.
Perhaps the session name was misspelled or has not yet been created.
Verify the session name matches an existing ADE Assembler session.

1>
ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.
You can only modify an ADE Assembler session that is active.
Perhaps the session name was misspelled or has not yet been created.
Verify the session name matches an existing ADE Assembler session.

*WARNING* hiDisplayAppDBox: modal dbox 'adexlMessageDialog' is already displayed!
ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.
You can only modify an ADE Assembler session that is active.
Perhaps the session name was misspelled or has not yet been created.
Verify the session name matches an existing ADE Assembler session.

*WARNING* hiDisplayAppDBox: modal dbox 'adexlMessageDialog' is already displayed!
ERROR (ASSEMBLER-1600): Cannot find an active session named fnxSession0.
You can only modify an ADE Assembler session that is active.
Perhaps the session name was misspelled or has not yet been created.
Verify the session name matches an existing ADE Assembler session.

Hi All,

I'm using a code (abConvertPolygonToPath.ils) that I found in other posts to convert a rect object to a path object inside a pcell code, but when I try to run a DRC, the layout export fails due to a warning message, here is the log message

*WARNING* (DB-270001): Pcell evaluation for 18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout has the following error(s):

*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" abConvertPolygonToPath))

ERROR (XOASIS-231): Pcell evaluation failed for '18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout' because the Pcell SKILL code contains either a syntax error or an unsupported XOasis function. Check the standard output or the Virtuoso log file for more information. Cadence recommends correcting the Pcell SKILL code to resolve the issue. However, to ignore these errors and continue the translation, you may use the 'ignorePcellEvalFail' option.

INFO (XOASIS-282): Translation Failed. '1' error(s) and '3' warning(s) found.

And when compile the code I get the following message:

*WARNING* defgeneric function already defined - abConvertPolygonToPath

I will aprreciate any help in how to waive this error, or fix it.

Thank you

Hi Team,

I am using the following command in my SKILL script to flatten the hierarchical layouts, it's working fine for all the instances and mosaics but not for techLib via's please help me with the command to use for flattening the techLib via.

dbFlattenInst( inst 2 nil)

dbFlattenInst( inst1 2 t t nil nil t t)

Regards,

MT.

Cadence AWR Design Environment Software Featured in Multiple Training Course Options: Live and Virtual Starting in October(read more)

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing everything from III-V 5G chips, to RF systems in board and package technologies. These types of designs require close interaction between the schematic and its layout. A new Training Byte demonstrates how the schematic-layout connections is built into Microwave Office.(read more)

Data sets are a powerful and easy-to-use feature in Microwave Office. Data can be effortlessly be swapped in graphs, and circuit schematics.(read more)

A training webinar on Microwave Office will be given June 27, 2023. The emphasis will be on EM simulation.(read more)

A recording of a training webinar on Microwave Office is available. Topics show the design environment, with special emphasis placed on electromagnetic (EM) simulation. Normal 0 false false false EN-US JA X-NONE ...(read more)

By David Vye, Senior Product Marketing Manager, AWR, Cadence When designing multi-octave high-power amplifiers, it is a challenge to achieve both broadband gain and power matching using a combination of lumped and distributed techniques. One approach...(read more)

New online training course for AXIEM EM Simulator in AWR Microwave Office is available.(read more)

Hello All:

I am looking for help on the following, as I am new to Cadence tools [I have to use Cadence Innovus for Physical Design after Logic Synthesis using Synopsys Design Compiler, using Nangate 45 nm Open Cell Library]: while using Cadence Innovus, I would need to select a few specific nets to be routed through a specific metal layer. How can I do this on Innovus [are there any command(s)]? Also, would writing and sourcing a .tcl script [containing the command(s)] on the Innovus terminal after the Placement Stage of Physical Design be fine for this?

Secondly, is there a way in Innovus to manipulate layout components, such as changing some pin placements, wire directions (say for example, wire direction changed to facing east from west, etc.) or moving specific closely placed cells around (without violating timing constraints of course) using any command(s)/.tcl script? If so, would pin placement changes and constraining some closely placed cells to be moved apart be done after Floorplanning/Powerplanning (that is, prior to Placement) and the wire direction changes be done after Routing? 

While making the necessary changes, could I use the usual Innovus commands to perform Physical Design of the remaining nets/wires/pins/cells, etc., or would anything need modification for the remaining components as well?

I would finally need to dump the entire design containing all of this in a .def file.

I tried looking up but could only find matter on Virtuoso and SKILL scripting, but I'd be using Innovus GUI/terminal with Nangate 45 nm Open Cell Library. I know this is a lot, but I would greatly appreciate your help. Thanks in advance.

Riya

Hi Cadence & forumers, 

I am running a conformal LEC with a flattened netlist against RTL. 

The run hang for 5 days at the "analyze abort" step which is automatically launched by the compare. 

The netlist is flattened at some levels so hierarchical flow which I tried didn't help much. The flattened/highly optimized netlist is from customer and the ultimate goal. How shall I proceed now? 

On the a side note, a test run with a hierarchical netlist from a simple DC "compile -map_effort medium" command finished after 1 day or so. 

Thank you! 

// Command: vpx compare -verbose -ABORT_Print -NONEQ_Print -TIMEstamp
// Starting multithreaded comparison ...
Comparing 241112 points in parallel.

// Multithreading Overhead: 38% Gates: 8501606/6168138
// Multithreaded processing completed.
================================================================================
Compared points PO DFF DLAT BBOX CUT Total
--------------------------------------------------------------------------------
Equivalent 1025 241638 30 75 21 242789
--------------------------------------------------------------------------------
Abort 0 124 0 0 0 124
================================================================================
Compare results of instance/output/pin equivalences and/or sequential merge
================================================================================
Compared points DFF Total
--------------------------------------------------------------------------------
Equivalent 204 204
================================================================================
// Warning: 512 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison
// Resolving aborts by analyze abort...

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized. 

The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral.  

The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.” 

Operation of PTP: 

To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent. 

The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages.  

To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay. 

The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized. 

Advantages of PTP: 

1. It provides accurate time stamping. 
2. It is a well-known clock synchronization protocol. 
3. It provides intensified security inside the premises. 
4. It provides the possibility of setting coordinated actions and synchronized communication. 

There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS. 

Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 

At what stage in the design cycle do you start to think about the PCB material costs? What about the costs to assemble the PCB? Once a design becomes successful, should you then redesign it to achieve a scalable product? Placing components and routi...(read more)

Introduction

Multiphysics is an integral part of the concepts around digital twins. In this post, I want to discuss the mechanical aspects of multiphysics in system simulations, which are critical for 3D-IC, multi-die, and chiplet design.

The physical world in which we live is growing ever more electrified. Think of the transformation that the cell phone has brought into our lives, as has the present-day migration to electronic vehicles (EVs). These products are not only feats of electronic engineering but of mechanical as well, as the electronics find themselves in new and novel forms such as foldable phones and flying cars (eVOTLs). Here, engineering domains must co-exist and collaborate to bring about the best end products possible.

Start with the electronics—chips, chiplets, IC packaging, PCB, and modules. But now put these into a new form factor that can be dropped or submerged in water or accelerated along a highway. What about drop testing, aerodynamics, and aeroacoustics? These largely computational fluid dynamics (CFD) and/or mechanical multiphysics phenomena must also be accounted for. And then how does the drop testing impact the electrical performance? The world of electronics and its vast array of end products is pushing us beyond pure electrical engineering to be more broadly minded and develop not only heterogeneous products but heterogeneous engineering teams as well.

Cadence's Unique Expertise

It's at this crossroad of complexity and electronic proliferation that Cadence shines. Let's take, for example, the latest push for higher-performing high-bandwidth memory (HBM) devices and AI data center expansion. These technologies are growing from several layers to 12, and I can't emphasize enough the importance of teamwork and integrated solutions in tackling the challenges of advanced packaging technologies and how collaboration is shaping the future of semiconductor innovation and paving the way for cutting-edge developments in the industry.

These layered electronics are powered, and power creates heat. Heat needs to be understood, and thus, the thermal integrity issues uncovered along the way must be addressed. However, electronic thermal issues are just the first domino in a chain of interdependencies. What about the thermal stress and warpage that can be caused by the powering of these stacked devices? How does that then lend to mechanical stress and even material fatigue as the temperature cycles from high to low and back through the use of the electronic device? This is just one example in a long list of many...

Cadence Multiphysics Analysis Offerings

The confluence of electrical, mechanical, and CFD is exactly why Cadence expanded into multiphysics at a significant rate starting in 2019 with the announcement of the Clarity 3D Solver and Celsius Thermal Solver products for electromagnetic (EM) and thermal multiphysics system simulations. Recent acquisitions of Numeca, Pointwise, and Cascade (now branded within Cadence as the Fidelity CFD Platform) as well as Future Facilities (now the Cadence Reality Digital Twin product line) are all adding CFD expertise. The recent addition of Beta CAE brings mechanical multiphysics to the suite of solutions available from Cadence. The full breadth of these multiphysics system analyses, spanning EM, thermal, signal integrity/power integrity (SI/PI), CFD, and now mechanical, creates a platform for digital twinning across a wide array of applications. You can learn more by viewing Cadence's Reality Digital Twin platform launch on the keynote stage at NVIDIA's GTC in March, as well as this Designed with Cadence video: NV5, NVIDIA, and Cadence Collaboration Optimizes Data Centers.

Conclusion

Ever more sophisticated electronic designs are in demand to fulfill the needs of tomorrow's technologies, driving a convergence of electrical and mechanical aspects of multiphysics in system simulations. To successfully produce the exciting new products of the future, both domains must be able to collaborate effectively and efficiently. Cadence is fully committed to developing and providing our customers with the software products they need to enable this electrical/mechanical evolution. From EM, to thermal, to SI/PI, CFD, and mechanical, Cadence is enabling digital twinning across a wide array of applications that are forging pathways to the future.

For more information on Cadence's multiphysics system analysis offerings, visit our webpage and download our brochure.

Community engagement is a dynamic concept that does not adhere to a singular, universal approach. Its various forms, methods, and objectives can vary significantly depending on the specific context, goals, and desired outcomes. Whether you seek assis...(read more)

Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available.

Follow these steps to Align Components using Offset Mode:

1. Set Application Mode to Placement Edit.
2. Drag the components that need to be aligned and right-click and choose Align Components.
3. Now, in the Options tab, you will notice Spacing Section with Equal Offset. You can equally and individually offset the components by using the +/- buttons for increment or decrement.

The Cadence Palladium Emulation Platform is a hardware system that implements the design, accelerating its execution and verification. Itoffers the highest performance and fastest bring-up times for pre-silicon validation of billion-gate designs, using a custom processor built by Cadence.

This Palladium Introduction course is based on the Palladium 23.03 ISR4 version and covers the following modules:

• Introduction
• Palladium flow
• Running a design on the Palladium system

This course starts with an “Introduction” module that explains Palladium and other verification platforms to show its place in the big picture. It also compares Palladium with Protium and simulation and discusses its usage and limitations.

The “Palladium Flow” module includes two stages at a high level, which are Compile and Run. Then, it covers these stages in detail. First, it covers the ICE compile flow and IXCOM compile flow steps in detail. Then it explains Run, which is common for both ICE and IXCOM modes.

The third module, “Running Design on the Palladium System,” covers all the items required for running your design on the Palladium system, including:

• Software stack requirements
• Basic concepts required to understand the flow
• Compute machine requirements

In addition, this course contains labs for both the ICE and IXCOM flows with detailed steps to exercise the features provided by the Palladium system. The lab explains a practical example of multiple counters and exercising their signals for force, monitor, and deposit features, along with frequency calculation using a real-time clock. The course is available on the Cadence support page:

There is also a Digital Badge available. You will find the Badge exam opportunity when you enroll in the Online training or after you have taken the training as "live" training.

For questions and inquiries, or issues with registration, reach out to us at Cadence Training. Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offerings, visit the Cadence Training website.

Related Training Bytes

• Palladium: What Are Verification Platforms
• Palladium: What Is Processor Based Emulation
• Palladium: Comparing Emulation (Z2) and Prototyping (X2)
• Palladium: What Are ICE and IXCOM Compile Flow
• Palladium: How to Process a Design to Run on Palladium
• Palladium: XCOM Compile Flow (TB+RTL to Palladium Database)
• Palladium: ICE Compile Flow (RTL to Palladium Database)
• Palladium: Legacy ICE Compile Flow
• Palladium: Cadence Software Releases for Palladium and Protium Flow
• Palladium: Setting of PATHs for Using Palladium
• Palladium: Z2 Hardware Structure (Blade and Boards)
• Palladium: What Is Sourceless and Loadless nets
• Palladium: Design Clocks
• Palladium: Step Count and Step Clock
• Palladium: Steps for Running the Design on Palladium Z2

Related Courses

• Verilog Language and Application Training
• SystemVerilog for Design and Verification
• Xcelium Simulator

Related Blogs

• Training Insights – A New Free Online Course on the Protium System for Beginner and Advanced Users
• It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!
• Training Insights - Free Online Courses on Cadence Learning and Support Portal

Cadence Protium prototyping platforms rapidly bring up an SoC or system prototype and provide a pre-silicon platform for early software development, SoC verification, system validation, and hardware regressions. In this Training W ebinar, we will explore debugging using Save/Restart on Protium X2 . This feature saves execution time and lets you focus on actual debugging. The system state can be saved before the bug appears and restartS directly from there without spending time in initial execution. We’ll cover key concepts and applications, explore Save/Restart performance metrics, and provide examples to help you understand the concepts. Agenda: The key concepts of debugging using save/restart Capabilities, limitations, and performance metrics Some examples to enable and use save/restart on the Protium X2 system Date and Time Thursday, November 7, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enrol to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within 1 hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Want to See More Webinars? You can find recordings of all past webinars here Like This Topic? Take this opportunity and register for the free online course related to this webinar topic: Protium Introduction Training The course includes slides with audio and downloadable lab exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training. Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. To view our complete training offerings, visit the Cadence Training website . Related Courses Protium Introduction Training Course | Cadence Palladium Introduction Training Course | Cadence Related Blogs Training Insights – A New Free Online Course on the Protium System for Beginner and Advanced Users Training Insights – Palladium Emulation Course for Beginner and Advanced Users Related Training Bytes Protium Flow Steps for Running Design on Protium System ICE and IXCOM mode comparison ICE compile flow IXCOM compile flow PATH settings for using Protium System Please see the course learning maps for a visual representation of courses and course relationships. Regional course catalogs may be viewed here

Allegro X System Capture offers a complete ecosystem for library development. This post introduces the latest DE-HDL Library Development using System Capture course in which you learn how to create different library objects. As a librarian, you often work with numerous libraries. Your tasks include creating or modifying symbols for libraries. To use Allegro X System Capture to create a library, you can follow the steps in the following flowchart: Let’s go through each step in detail. Setting the CDS_SITE Variable Before you start library development for a new project, set the CDS_SITE system environment variable. This step is required to access libraries and other configuration files. Creating a Project in Allegro X System Capture The next step is to create a project in Allegro X System Capture. Adding a Library to the Project Symbol development consists of creating symbol graphics, electrical data, and properties used by different tools in the PCB design flow. To add a library to a project, first create a library in the Libraries pane of the Project e xplorer. Creating Library Symbols The library development process supports the creation of various types of symbols. Creating a Symbol with Multiple Views You can generate multiple views of the same symbol using the Duplicate command. For example, a discrete symbol, such as a resistor, can have multiple views, as shown in the following image: Creating a Split Symbol For advanced designs, you often need to create library symbols and break them into multiple sections to support the design process. When a symbol shows all the logical pins in the physical package, it is called a single-section or flat symbol. Many large ICs have several pins and the symbols need to fit on a single schematic page. One workaround is to use vector pin names on a symbol to reduce its size, although manufacturers prefer schematics that show each pin. You can divide these high-pin count devices into smaller pieces, where each piece is a separate version of the part. Such parts are referred to as split parts or multi-section symbols. For multi-section symbols, you can create two types of split parts—symmetrical and asymmetrical. Symmetrical Split Symbols A symmetrical split symbol has only one symbol graphic, which holds two or more identical logic symbols, each with its own unique physical pin numbers. You can create a symmetrical split symbol using the Duplicate Section icon in the canvas window. Each symbol section contains the same set of pins but different pin numbers, as shown in the following image: Asymmetrical Split Symbols An asymmetrical split symbol is a symbol whose physical package contains one or more unique schematic symbols. You can create an asymmetrical split symbol by clicking the New Section icon in the canvas window. Asymmetrical symbols have a unique set of logical pins, as shown in the following image: Creating Symbols Using the Spreadsheet Interface To simplify the development of large symbols, Allegro X System Capture has a Spreadsheet Interface . You can copy from a spreadsheet into the interface. This saves time and helps minimize errors introduced by manual entry. In conclusion, the DE-HDL library development using Allegro X System Capture course involves several critical steps and supports various symbol creation techniques. This course helps librarians create and modify symbols effortlessly and deepens their understanding of library development within Allegro X System Capture. To learn more about this topic, enroll in the DE-HDL Library Development using Allegro X System Capture course on the Cadence Support portal . Click the training byte link now or visit Cadence Support and search for training bytes under Video Library. If you find the post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design: DE-HDL Library Development using Allegro X System Capture (Online). You can become Cadence Certified once you complete the course. Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise. To find out more, see the blog post Take a Cadence Masterclass and Get a Badge . You might also be interested in the training Learning Map that guides you through recommended course flows as well as tool experience and knowledge-level training modules. To find information on how to get an account on the Cadence Learning and Support portal, see here . SUBSCRIBE to the Cadence training newsletter to be updated about upcoming training, webinars, and much more. If you have any questions about courses, schedules, online training, blended/virtual live training, or public, or onsite live training, reach out to us at Cadence Training .

As a verification engineer, you’re surely looking for ways to automate the debugging process. Have you developed your own scripts to ease specific debugging steps that tools don’t offer? Working with scripts locally and manually is challenging—so is reusing and organizing them. What if there was a way to create your own app with the required functionality and register it with the tool? The answer to that question is “Yes!” The Verisium Debug Python App Store lets you instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. Join me, Principal Education Application Engineer Bhairava Prasad, for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps, learn about them, install or uninstall them, and even customize existing apps. Date and Time Wednesday, November 20, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within one hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Like this topic? Take this opportunity and register for the free online course related to this webinar topic: Verisium Debug Training To view our complete training offerings, visit the Cadence Training website Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. Related Courses Xcelium Simulator Training Course | Cadence Related Blogs Unveiling the Capabilities of Verisium Manager for Optimized Operations - Verification - Cadence Blogs - Cadence Community Verisium SimAI: SoC Verification with Unprecedented Coverage Maximization - Corporate News - Cadence Blogs - Cadence Community Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput - Verification - Cadence Blogs - Cadence Community Related Training Bytes Introducing Verisium Debug (Video) (cadence.com) Introduction to UVM Debug of Verisium Debug (Video) (cadence.com) Verisium Debug Customized Apps with Python API Please see course learning maps a visual representation of courses and course relationships. Regional course catalogs may be viewed here . *If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help .

Hearing is one of the most essential senses for engaging with the world. It enables us to converse, appreciate music, and remain alert to our surroundings. Hearing loss is a prevalent issue affecting millions of individuals globally and disconnecting them from a world where sound is vital to others and the environment. The World Health Organization (WHO) reports that over 5% of the global population requires hearing rehabilitation, a striking statistic highlighting this issue's pervasive nature. Technology has transformed audiology, evolving from simple ear trumpets to sophisticated modern hearing aids. This advancement began with the invention of the transistor, paving the way for devices that are fully wearable inside or behind the ear. Although hearing aids have been available for many years, historically, access to these critical devices has been insufficient, resulting in numerous individuals lacking the necessary support. However, recent advances in hearing aid technology promise improved acoustic experiences, employing modern techniques like binaural processing and neural networks. These innovations demand sophisticated architecture to balance high memory needs with low power consumption in a user-friendly design. Cadence is at the forefront of this technological evolution, offering tools and IP solutions that enhance the accessibility, efficiency, and impact of hearing aids, paving the way for a more inclusive future. This blog explores how Cadence's advanced DSPs are transforming hearing aid design and making them more accessible, efficient, and impactful. Hearing Aids: A Testament to Human Ingenuity The transition from analo g to digital technology in the late 20th century further transformed hearing aids, offering superior sound quality, customization, and the ability to connect to various electronic devices, thus enhancing the user experience markedly. Today's hearing aids are highly effective, versatile, and nearly invisible, a significant advancement from early attempts to address hearing loss. They also feature advanced noise cancellation and connectivity options, allowing users to integrate seamlessly into the digital world. This progression not only highlights the industry's commitment to improving user experience and accessibility but also offers a glimpse into a future where hearing loss is no longer a barrier. Challenges Despite advancements and sophistication, there are several challenges related to hearing aid design and adoption. Users demand smaller, more discreet devices that don't sacrifice performance. While the shift towards sleeker designs is aesthetically pleasing, it introduces substantial complexities in product design. Designers face the challenges of integrating essential components, such as batteries and peripherals, into increasingly compact spaces. Power consumption remains a critical concern, as these devices must remain operational throughout the day. Leveraging neural networks to enhance the signal-to-noise ratio (SNR) for better quality demands additional memory capacity. Consequently, there is a pressing need for flexible, low-power architectures that incorporate all necessary memory and peripherals without compromising the device’s compact size. Adopting AI for adjusting hearing aid volume to fit an individual's specific auditory requirements is a significant challenge and demands more memory and effort. Besides this, reliability and cost are significant challenges for manufacturers. Cadence's Role in Transforming Hearing Aids In hearing aid development, the capacity to evaluate the energy efficiency of SoCs across different frequencies in real time is crucial. These applications demand cohesive, energy-efficient solutions that can uphold high performance. The Cadence Tensilica HiFi and Fusion F1 DSP family emphasize minimal power usage while providing robust performance, ideally suited for a wide range of audio and voice applications. The Cadence Tensilica HiFi DSP family, a high-performance audio technology with AI acceleration and advanced DSP capability, offers feature-rich audio, speech, and imaging for wearables, automotive, home entertainment, digital assistants, and ASR. The Tensilica HiFi DSP family accelerates innovation with its comprehensive instruction set and supports fixed- and floating-point data types. Simplifying software development, it offers C/C++ programming, an auto-vectorizing compiler, and a rich DSP software library through the Cadence Tensilica Xplorer development environment. With the flexibility to customize and enhance performance through additional instructions and better I/O bandwidth, the Tensilica HiFi and Fusion DSP families offer a robust, low-energy audio solution compatible across an expansive software ecosystem for various applications and devices. Conclusion Technological advancements are driving hearing aid evolution; the future of hearing aids lies in further miniaturization and functionality enhancement. Cadence's ongoing innovations aim to improve signal processing and noise reduction, even in challenging environments. The integration of neural networks promises more apparent sound transmission and greater adaptability. Cadence is working on improving how these devices process signals and reduce noise and has initiated a collaborative venture with distinguished entities like GlobalFoundries (GF), Hoerzentrum Oldenburg gGmbH, and Leibniz University Hannover. This collaboration has borne fruit in the form of the industry's first binaural hearing aid system-on-chip (SoC) prototype, the Smart Hearing Aid Processor ( SmartHeAP ). Learn More Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology Cadence Extends Battery Life and Improves User Experience for Next-Generation Hearables, Wearables and Always-On Devices Advancing the Future of Hearing Aids with Cadence Bluetooth LE Audio, Hearing Aids, and Mindtree

Hey, is it suitable to post here? I wanted a small yet robust amp for practicing while I travel. I wanted something that would fit in my pocket yet still be loud enough to hear.

Presented here is a amplifier based upon the LM386 Audio Amplifier.

There is a standard circuit in the data sheet that is an excellent place to start.

Materials needed:
1 - HM359 project box
1 - 668-1237 speaker
1 - BS6I battery conn
1 - CP1-3515 stereo jack
1 - SC1316 stereo jack
2 - 450-1742 knob
1 - 679-1856 switch
1- 3mm LED
1 - 10 ohm 1/4W resistor
1 - 10uF ceramic cap
1 - .05 uF ceramic cap
1 - 420 uF electrolytic cap
1 - 8 ohm resistor
2 - 51AADB24 10K pot
1 - HM1252 circuit board
1 - LM386N-4 amplifier

Wire and Solder
Step 1: Prep the enclosure

Careful planning is required the first time you free build a circuit. The circuit board has solder pads but not traces. You will have to use thin wire to make the connections for the circuit to work.

Begin by laying out the components on the circuit board that will need to pass through the enclosure. This enclosure has a removable top panel which will be used for the volume, gain and 1/4 inch stereo jack.

Space is limited to check for fit before drilling.

All drilling of the plastic should be done with a step drill bit. This will make the cleanest holes without breaking the plastic.

Lay out the pots a few spaces back but still in line with the desired position. mark the center of each pot shaft then drill with a step drill tot he tightest fitting hole size. Make a center mark between the pot holes then drill for the stereo jack

On the inside of the top cover position and mark where the speaker will go.

Make a template on grid paper the same size as the speaker.

Tape the template to the inside of the cover as shown then use a step bit to drill holes on the center of every square in the grid. This will form the speaker grille. clean up the holes.

Step 2: place the major components

Solder the pots to the circuit board as shown. then place the stereo jack(note in order to get the final fit I had to trim and modify the stereo jack housing a little)

Next, position and solder the switch on the circuit board and mark a space on the top cover that will need to be cut for the switch opening. Use a small file to cut the opening.

Use a sharp knife to bevel the edges of the switch hole to allow for easier operation.

Drill a hole in the side of the upper case for the headphone jack and fasten it in place. ( I had to recess the hole a bit for the retaining nut to grab)

Step 3: Build the circuit

The speaker is held in place by using 2 small brackets that come with the serial cable connector hood. ( I had a bunch around that would never be used)

Refer the the circuit shown from the datasheet and the datasheet for the LM386. The basic circuit only has the volume control while the datasheet shows how to add a gain control across pins 1 and 8 of the amplifier.

The speaker is wired in series with the headphone jack. The headphone jack has internal switches that shut the speaker off when the phones are plugged in.

I chose to use a chip socket for the amplifier which make prototyping easier since you do not have to worry about solder heating as much.

Carefully lay the circuit out on the board and begin wiring components together. I added a second pot and cap in series between pins 1 and 8 of the amp to be able to manually set the gain in addition to volume.

Check you connections with a multimeter before adding the amplifier.

I chose to add a LED indicator for power. This was done by using one side of switch contacts from the battery. The LED is in series with a 220 ohm resistor.

Assemble the case and insert the battery.

Step 4: Final notes

If the speaker is noisy while the headphones work normally, try reversing the speaker connections. If it does not correct the issue, connect a 8 ohm resistor across the speaker contacts.

You may have to place an insulating layer between the speaker and the place where the stereo jack comes through to prevent contact. This will be noted by a loud buzz.

You may have to add some foam in the battery compartment to stop the battery from banging around.

For reference, I've also read an article about amplifiers: http://www.apogeeweb.net/article/60.html

Thanks for reading!
​

Hi, all.

When I use vavlog to compile verilog rtl, it will recognize IO width mismatch problem as a fatal error.

How to turn the error into warning?

VCS can use -error=noIOPCWM to ingore the error.

Is vavlog has similar arguments?