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he Delaware Department of Agriculture (DDA) announced beginning October 15, 2024, the cost of fecal analysis testing performed by the Poultry and Animal Health Section will increase to $3.00 per sample. The Poultry and Animal Health Section will begin offering livestock fecal sample analysis using the McMaster technique for relevant livestock species, and the current qualitative fecal float testing will still be performed as appropriate by species.

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The International Institute of Forecasters and SAS® are funding two $10,000 grants to support research on forecasting. Per the announcement: For the eighteenth year, the IIF, in collaboration with SAS®, is proud to announce financial support for research on improving forecasting methods and business forecasting practice. The award for this year will be [...]

The post SAS/IIF Research Grants (proposals due October 1) appeared first on The Business Forecasting Deal.

A previous article about how to display missing values in SAS prompted a comment about special missing values in ODS tables in SAS. Did you know that statistical tables in SAS include special missing values to represent certain situations in statistical analyses? This article explains how to interpret four special [...]

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A Delhi government report has attributed nearly 24 per cent of the total about 89,000 deaths registered in the national capital in 2023 to infectious and parasitic diseases like cholera, diarrhoea, tuberculosis and hepatitis B, among others.

Zomato witnesses approximately 400,000 cancelled orders monthly which prompted it to launch the initiative.

i want to read from text file two values  on two ports , i wrote  that  code, and i have that error that shown in the image below . and also the data in text file is shown as screenshot

module read_file (a,b);

electrical a,b;
integer in_file_0,data_value, valid, count0,int_value;

analog begin
@(initial_step) begin
in_file_0 = $fopen("/home/hh1667/ee610/my_library/read_file/data2.txt","r");

valid = $fscanf (in_file_0, "%b,%b" ,int_value,count0);
end

V(a) <+ int_value;
V(b) <+ count0;

end

endmodule

We are looking for suitable tools that could be used for RTL design, IP-XACT based  integration (third party IP) and RTL design verification ( SV / UVM based methodology).

Request to share details on the different Cadence tools that is most suitable for these activities.

This document resolved my first query,

Article (11638952) Title: How to output power and ground nets to GDS
URL: support.cadence.com/.../ArticleAttachmentPortal

but now I have 20 power and 20 ground

below is my code

------------------------------------------------
variable GND "vss1" "vss2" "vss3" ... "vss20"
variable VDD "vdd1" "vdd2" "vdd3" ... "vdd20"

select_net M1 GND -outputlayer GND_M1
select_net M2 GND -outputlayer GND_M2
...
select_net AP GND -outputlayer GND_AP

select_net M1 VDD -outputlayer VDD_M1
select_net M2 VDD -outputlayer VDD_M2
...
select_net AP VDD -outputlayer VDD_AP

rule GND{

copy GND_M1
copy GND_M2
...
copy GND_AP}

rule VDD{

copy VDD_M1
copy VDD_M2
...
copy VDD_AP}
------------------------------------------------

I want 20 GND and 20 VDD are separately to highlight,
like this

Can DRC command use for-loop(skill or Tcl) to split the rule?
or how can I do to split it? 
I don't really want to repeat the rule 40 times..haha😅 (use Pegasus 22.21)

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more)

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

Hi ,

  FIrst of all , I hope I have posted my query in the right place . I am expecting software support/suggestions for the below issue.

   I am working on LTE which use USB interface and the Host Controller is USB 2.0 . The BSP is from NXP which supports Cadence USB 3.0 Host controller and with USB 3.0 supported cadence driver.NXP had used the   USB 3.0 host controller for USB type C based device.

  Cadence USB 3.0 based device driver seems to be backward compatible for USB 2.0 host controller .Since basic LTE functionalities seems to be working fine I continued to use the same driver in Linux 4.14.62 

  But I am facing a kernel warning of unhandled interrupt and the crash log points to cdns_irq function as shown below  The crash/kerenel warning is very random and not occuring all the time.

.691533] irq 36: nobody cared (try booting with the "irqpoll" option)

[ 1.698242] CPU: 0 PID: 87 Comm: kworker/0:1 Not tainted 4.9.88 #24

[ 1.704509] Hardware name: Freescale i.MX8QXP MEK (DT)

[ 1.709659] Workqueue: pm pm_runtime_work

[ 1.713675] Call trace:

[ 1.716123] [<ffff0000080897d0>] dump_backtrace+0x0/0x1b0

[ 1.721523] [<ffff000008089994>] show_stack+0x14/0x20

[ 1.726582] [<ffff0000083daff0>] dump_stack+0x94/0xb4

[ 1.731638] [<ffff00000810f064>] __report_bad_irq+0x34/0xf0

[ 1.737212] [<ffff00000810f4ec>] note_interrupt+0x2e4/0x330

[ 1.742790] [<ffff00000810c594>] handle_irq_event_percpu+0x44/0x58

[ 1.748974] [<ffff00000810c5f0>] handle_irq_event+0x48/0x78

[ 1.754553] [<ffff0000081100a8>] handle_fasteoi_irq+0xc0/0x1b0

[ 1.760390] [<ffff00000810b584>] generic_handle_irq+0x24/0x38

[ 1.766141] [<ffff00000810bbe4>] __handle_domain_irq+0x5c/0xb8

[ 1.771979] [<ffff000008081798>] gic_handle_irq+0x70/0x15c

1.807416] 7a40: 00000000000002ba ffff80002645bf00 00000000fa83b2da 0000000001fe116e

[ 1.815252] 7a60: ffff000088bf7c47 ffffffffffffffff 00000000000003f8 ffff0000085c47b8

[ 1.823088] 7a80: 0000000000000010 ffff800026484600 0000000000000001 ffff8000266e9718

[ 1.830925] 7aa0: ffff00000b8b0008 ffff800026784280 ffff00000b8b000c ffff00000b8d8018

[ 1.838760] 7ac0: 0000000000000001 ffff000008b76000 0000000000000000 ffff800026497b20

[ 1.846596] 7ae0: ffff00000810bd24 ffff800026497b20 ffff000008851d18 0000000000000145

[ 1.854433] 7b00: ffff000008b8d6c0 ffff0000081102d8 ffffffffffffffff ffff00000810dda8

[ 1.862268] [<ffff000008082eec>] el1_irq+0xac/0x120

[ 1.867155] [<ffff000008851d18>] _raw_spin_unlock_irqrestore+0x18/0x48

[ 1.873684] [<ffff00000810bd24>] __irq_put_desc_unlock+0x1c/0x48

[ 1.879695] [<ffff00000810de10>] enable_irq+0x48/0x70

[ 1.884756] [<ffff0000085ba8f8>] cdns3_enter_suspend+0x1f0/0x440

[ 1.890764] [<ffff0000085baca0>] cdns3_runtime_suspend+0x48/0x88

[ 1.896776] [<ffff0000084cf398>] pm_generic_runtime_suspend+0x28/0x40

[ 1.903223] [<ffff0000084dc3e8>] genpd_runtime_suspend+0x88/0x1d8

[ 1.909320] [<ffff0000084d0e08>] __rpm_callback+0x70/0x98

[ 1.914724] [<ffff0000084d0e50>] rpm_callback+0x20/0x88

[ 1.919954] [<ffff0000084d1b2c>] rpm_suspend+0xf4/0x4c8

[ 1.925184] [<ffff0000084d20fc>] rpm_idle+0x124/0x168

[ 1.930240] [<ffff0000084d26c0>] pm_runtime_work+0xa0/0xb8

[ 1.935732] [<ffff0000080dc1dc>] process_one_work+0x1dc/0x380

[ 1.941481] [<ffff0000080dc3c8>] worker_thread+0x48/0x4d0

[ 1.946885] [<ffff0000080e2408>] kthread+0xf8/0x100
[ 1.957080] handlers:

[ 1.959350] [<ffff0000085ba668>] cdns3_irq

[ 1.963449] Disabling IRQ #36

 Kindly provide a solution to solve this issue.

Thanks & Regards,

Anjali

Hello everyone. In recent days, I'm having a weird problem with sound output on my Windows 10 PC. In fact, I can't control the loudness of it. So is there any possibility of PCB of sound card being damaged?

Hi 

I have a Xtensa compiler issue that the compilation for switch case would be optimized in some patterns and leads to unexpected result. I cross-checked the assembly code and found that such compiler optimization seems to be similar to the tree-switch-conversion feature in GCC compiler

• https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html
  -ftree-switch-conversion
      Perform conversion of simple initializations in a switch to initializations from a scalar array. This flag is enabled by default at -O2 and highe

Unfortunately I don't find any similar compiler option(like -fno-tree-switch-conversion) in Xtensa compiler(XCC) to enable/disable such feature and such feature seems like enabled in XCC by default even if I'm using -O0 for the least optimization.

I'm wondering if there's any possible solution to permanently disable such feature in XCC?

PS: The release version of XCC compiler I'm using is RD-2012.5

Thanks!

Hi,

I'm looking to download Tensilica SDK for evaluation, but I can't get past the registration form:

Read on to know about the Operating Point Parameters Summary window that gives you a one-stop view of the categorized and tabulated details on all operating point parameters in your design. This window improves your review cycle with its many benefits.(read more)

Hi All

I followed tutorial video below for using Design link

https://www.youtube.com/watch?v=f9JmFF8lqA0

and I followed the video with embedded board design file which should be same one on video

I did every set. but  at 2:55 of video, Steve have the tabs of both design names on top of Constraint Manager in video

but my one didn't exist them

which one would be different?

there was some comment on command windows but I think they would not be problem here

regard

hello:

i use the command "net logic" to change/assign the net name of the pins but the command can be used for only one pin at a time.

is there a way to change/assign the same net name on 100 pins all at once?

i have a daisy chain design so i need to assign one net name for 100s of pins.

========

thank you david, i was able to do it.

i am writing this section because i can not reply to your comment.

Hi,

I found that under the Dark Theme of PCB Environment Editor 17.4,

the window background is not all dark, resulting in unclear text display。

As shown in the figure below：

Hi,

I have a LEF file with simple definitions of pad design which uses M8, M9, and AP layers. However, I failed to import the design with CIW > Import > LEF... as I encountered "ERROR: (OALEFDEF-90019): Ignoring the line 30 in the layer map file ... as it contains a syntax error. Each entry in the layer map file must have two values, LEFLayerName and OALayerNumber separated by a blank space." All lines in the file report the same OALEFDEF-90019 error.

The tech.layermap file looks like this:


# techLayer       techPurpose     stream# dataType

ref drawing 0 0
DNW drawing 1 0
PW drawing 2 0

Hello

i did a sp-Analysis and now i want to extract the maximum value of the s11 trace and the corresponding frequency.

I already tried ymax() in the calculator but i am suspecting it only works on transient Signals.

We are trying to run compilation, elab and sim with command xrun -r -u alu, where alu is one of the units to execute. we are getting the following errors.

1) xmsim: *E,DLMKDF: Unable to add default DEFINE std       /home/xxxx/Cad/xcelium/tools/inca/files/STD.
    xmsim: *E,DLMKDF: Unable to add default DEFINE synopsys  /home/xxxx/Cad/xcelium/tools/inca/files/SYNOPSYS

2) xmsim: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.

What is the purpose of hdl.var

3) xmsim: *F,NOSNAP: Snapshot 'alu' does not exist in the libraries.

I cannot see in log files, which libraries is it referring to??

Any one request you to help on how to debug these.

The two macros below introduce new syntax for adding definitions to more than one 'when' determinant value at the same time. The first macro overloads 'extend' keyword and the second is the equivalent for 'when' keyword.

A use example:

extend [HUGE, BIG] packet {
    // definitions that pertain to these subtypes
};

The above code would be expanded in the following (naive) way:

extend HUGE packet {
    // definitions that pertain to these subtypes
};
extend BIG packet {
    // definitions that pertain to these subtypes
};


The macros code:

define 'statement>
       "extend ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%sextend %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

define 'struct_member>
       "when ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%swhen %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more)

The Allegro PCB Editor Basic Techniques course provides all the essential training required to start working with Allegro® PCB Editor. The course covers all the design tasks, including padstack and symbol creation, logic import, constraints setup...(read more)

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

I get multiple results at the same frequency in a 3-tone simulation.

I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz.

At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ).

Which of the values do I have to use to determine the correct IP3?

Is there an option to merge these results?

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

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