WILMINGTON, Del. – First Spouse Tracey Quillen Carney, with the Delaware Department of Education and Delaware Readiness Teams, kicked off Kindergarten Registration at the Claymont Public Library on Wednesday, October 9. “I’ve been the honorary chair of the Kindergarten Registration Campaign for almost eight years because it is important to make navigating this milestone as […]

The State of Delaware took a significant step towards a cleaner transportation future today, celebrating its receipt of 14.3 million thanks to the U.S. Environmental Protection Agency’s (EPA) “Climate Pollution Reduction Grant” (CPRG) program. This grant, the result of the Federal Inflation Reduction Act and the Biden-Harris Administration’s Investing in America agenda, will be used to […]

Additionally, Workplace Safety Program eligibility changes will help more companies stay safe and save money Insurance Commissioner Trinidad Navarro announced today that workers’ compensation insurance rates will decrease for the eighth year in a row, effective December 1. The voluntary market is expected to decrease average loss costs by 8.4%, and the residual market will […]

Governor John Carney and Delaware Secretary of Agriculture Michael T. Scuse, along with members of the General Assembly, the Aglands Preservation Board of Trustees, and other agricultural advocates, joined together at Shadybrook Farms, home of the Cartanza family, to unveil a new farm sign celebrating Delaware’s Agricultural Lands Preservation Program.

Revenue Announces New HSCA Rate Effective January 2025 Statewide, DE (October 28, 2024) – Division of Revenue Director Kathy Revel today announced that businesses subject to the Hazardous Substance Cleanup Act (HSCA) will see an increase in last year’s rate from 0.675% to 1.120%. The new tax rate will go into effect on January 1, […]

WILMINGTON, Del. – As the first year of grantmaking comes to a close, Co-Chairs Attorney General Kathy Jennings and Lt. Governor Bethany Hall-Long shared the results of the third-party report from independent contractor Social Contract with recommendations to maximize the impact of the governing body overseeing Delaware’s opioid settlement funds.     The report, Enhancing Use […]

Attorney General Kathy Jennings today joined a coalition of 50 states and territories announcing two significant cooperation agreements and settlements with Heritage Pharmaceuticals and Apotex totaling $49.1 million to resolve allegations that both companies engaged in widespread, long-running conspiracies to artificially inflate and manipulate prices, reduce competition, and unreasonably restrain trade with regard to numerous generic prescription […]

DOVER, Del. – Governor Carney joined Lieutenant Governor Bethany Hall-Long, Department of Transportation Secretary Nicole Majeski, Department of Natural Resources and Environmental Control Secretary Shawn Garvin, elected officials and advocates on Friday afternoon to outline investments in the state’s electric vehicle infrastructure. With a combination of state and federal funding, charging stations for electric vehicles will be […]

The DE529 Education Savings Plan, Delaware’s tax-advantaged program designed to help pay for higher education expenses, received “Silver” status from Morningstar, the country’s most widely cited and influential investment plan rating group. This is the second consecutive year DE529 received the rating after being upgraded from “Bronze” status in 2023. “With higher education costs remaining […]

The Delaware Department of Transportation (DelDOT) announces that Moody’s Investors Service, Inc. has assigned an Aaa rating to the Delaware Transportation Authority, their highest rating, and S&P Global Ratings assigned its second highest rating of AA+ long-term rating to the department’s $150.5 million series 2024 transportation system senior revenue bond sale that will be issued […]

DEPARTMENT OF STATE: Division of Professional Regulation

DEPARTMENT OF STATE: Office of the Alcoholic Beverage Control Commissioner

Read the in depth Review of Resident Evil: Operation Raccoon City Gaming. Know detailed info about Resident Evil: Operation Raccoon City configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Beyerdynamic T1 (3rd Generation) Audio Video. Know detailed info about Beyerdynamic T1 (3rd Generation) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of xPUD - Firefox powered Operating System Software. Know detailed info about xPUD - Firefox powered Operating System configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of iPad Mini 2021 (6th Generation) Tablets. Know detailed info about iPad Mini 2021 (6th Generation) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Apple iPad (10th generation) Tablets. Know detailed info about Apple iPad (10th generation) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Apple AirPods Pro (2nd generation) Audio Video. Know detailed info about Apple AirPods Pro (2nd generation) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Learn why integrating EHR data with pharmacy and claims data improves patient care.

The post Closing data gaps to promote integrated health care appeared first on The Data Roundtable.

Fight back against sophisticated money launderers with these 3 techniques.

The post 3 techniques to improve AML transaction monitoring strategies appeared first on The Data Roundtable.

Having the right data analytics platform can help law enforcement solve crimes faster.

The post 5 technology considerations for law enforcement appeared first on The Data Roundtable.

BJP MP from South Delhi Ramvir Singh Bidhuri on Tuesday inaugurated a newly constructed stretch of a 12-lane national highway connecting Mithapur Chowk to the Mumbai-Baroda highway in the Badarpur area.

Ratan Naval Tata, the business titan and global icon who led the Tata behemoth from thirty countries to over a hundred since becoming chairman in 1991, died today at Mumbai's Breach Candy Hospital. He was 86.

Ratan Tata, born on December 28, 1937, is the Chairman of Ratan Tata Trust, two of the largest private-sector-promoted philanthropic trusts in India.

Industrialist Ratan Tata, who passed away at the age of 86, is credited with transforming the Tata Group's portfolio during his tenure as chairman to include products from salt to software to sports cars.

Founded in 1868, Tatas have become one of largest and most diverse global conglomerates. It is a name heard in almost every home in India and tens of millions overseas.

1. Google Chrome on iPhones gets new features with Drive, Maps integration  Business Standard
2. Stop Using Chrome On Your iPhone, Warns Apple—Millions Of Users Must Now Decide  Forbes
3. 4 new Chrome improvements for iOS  The Keyword
4. Chrome on iOS now lets you search using images and text at the same time  TechCrunch
5. Google rolls out new features in Chrome for iPhone users  Moneycontrol

1. Donald Trump picks ex-US spy John Ratcliffe as CIA chief, Mike Huckabee as ambassador to Israel  Hindustan Times
2. Trump picks Ratcliffe as CIA director, Kash Patel misses out  India Today
3. Donald Trump picks ‘China hawk’ John Ratcliffe as CIA director, taps Fox News host Pete Hegseth as defence secretary  Mint
4. Trump picks John Ratcliffe to be CIA director  The Hindu
5. Meet former US spy John Ratcliffe, Trump's choice for CIA director  The Times of India

Children's Day, also known as 'Bal Diwas', is celebrated annually on November 14 in India. The day is celebrated to appreciate and acknowledge children as they are the future of the county.

The offer is valid across the US. Some of its international locations - the chain operates in 40 countries - also have World Kindness Day promotions planned.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[SAPS] SAPS members' continued efforts to prevent and detect crime yielded the following successes within the Joe Gqabi District as part of Operation Shanela during the week and start of the weekend .

[COSATU] The Congress of South African Trade Unions (COSATU) welcomes the slight drop in the expanded unemployment rate from 42.6% in the second quarter to 41.9% in the third quarter of this year.

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology(read more)

I have a standard cell library containing LEF, GDS, and spice models but no OA views. I'm unable to import these files into Virtuoso without a LayerMap file. How can I obtain or generate this required LayerMap file?

I am trying to install IC231 on RHEL 8 using installscape, however configuring keeps failing.

I tried to run the configuration file manually as suggested in one of the previous posts and it gives me following errors:

sh batch_configure.sh
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl64b23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl64b23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: oaRedist22.61-p003lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'oaRedist22.61-p003lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: amsEnv64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'amsEnv64b23.10-p043lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ihdl64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ihdl64b23.10-p043lnx86_101124125631.stat': No such file or directory

I am not very well versed with Linux at the moment but trying. Could any one suggest something or point to what is missing?

A recording of a training webinar on Microwave Office is available. Topics show the design environment, with special emphasis placed on electromagnetic (EM) simulation. Normal 0 false false false EN-US JA X-NONE ...(read more)

Dear all, 

I'm trying to perform an LVS check using Calibre between a layout that was generated by Innovus and the initial netlist generated by Genus. However, once I hit Run LVS on Calibre, it reports the following warnings and recommends to stop the process:

Source netlist references but does not define more than 10 subckts:
DFD1BWP7T
DFKCND1BWP7T
DFKCNQD1BWP7T
DFKSND1BWP7T
DFQD1BWP7T
IND2D0BWP7T
INR2D0BWP7T
INVD0BWP7T
INVD2P5BWP7T
IOA21D0BWP7T
... (and more)

If I proceed the LVS process it shows lots of errors as shown in the following image:

Why Genus doesn't include the definition of those sub circuits in the generated netlist? Is this related to Flat/Hierarchy netlisting? 

I have included my Genus scripts as well as the generated netlist in the attachments (and here - if attachment don't work).

Many thanks,

Anas

Hi everyone, 

Is there any method to generate "Sheet" column for a pin report like table below? The column "Name.Pin" & "Signal" can be generated easily, but I have no idea to generate the column of "Sheet Name".

The software using here are Allegro Design Entry HDL, OrCAD Capture and Allegro PCB Editor. Can these 3 software generate "Sheet Name" data?

Thank you. 

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more)

To stay ahead in competition in chip design real-time collaborations ensure traceability, speedy innovations at reduced the cost.(read more)

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and reduces project schedules with optimized continuous integration.(read more)

Live Doc is an advanced automated PCB documentation generation tool integrated with OrCAD X Presto designed to streamline the creation of PCB documentation. By automating the generation of PCB fabrication and assembly drawings, Live Doc significantly...(read more)

When working on a complex design, it is common to have very many net ratlines. Quantities like 1000 ratlines are possible. It can result in a cluttered view while routing. Therefore, it is useful to make all other ratlines invisible while routing interactively. You would like to make all ratlines visible again when each route action is completed.

You can easily do this by enabling the Auto-blank other rats option during routing. When enabled, all rats other than the primary ones are suppressed during the Add Connect command.

Verisium SimAI App harnesses the power of machine learning technology with the Cadence Xcelium Logic Simulator - the ultimate breakthrough in accelerating verification closure. It builds models from regressions run in the Xcelium simulator, enabling the generation of new regressions with specific targets. The Verisium SimAI app also features cousin bug hunting, a unique capability that uses information from difficult-to-hit failures to expose cousin bugs. With these advanced machine learning techniques, Verisium SimAI offers the potential for a significant boost in productivity, promising an exciting future for our users.

Figure 1: Regression compression and coverage maximization with Verisium SimAI 

What can I do with Verisium SimAI?

You can exercise different use cases with Verisium SimAI as per your requirements. For some users, the goal might be regression compression and improving coverage regain. Coverage maximization and hitting new bins could be another goal. Other users may be interested in exposing hard-to-hit failures, bug hunting for difficult to find issues. Verisium SimAI allows users to take on any of these challenges to achieve the desired results.

Let's go into some more details of these use cases and scenarios where using SimAI can have a big positive impact.

1. Using SimAI for Regression Compression and Coverage Regain

Unlock up to 10X compute savings with SimAI!

Verisium SimAI can be used to compress regressions and regain coverage. This flow involves setting up your regression environment for SimAI, running your random regressions with coverage and randomization data followed by training, and finally, synthesizing and running the SimAI-generated compressed regressions. The synthesized regression may prune tests that do not help meet the goal and add more runs for the most relevant tests, as well as add run-specific constraints. This flow can also be used to target specific areas like areas involving a high code churn or high complexity.

You can check out the details of this flow with illustrative examples in the following Rapid Adoption Kits (RAK) available on the Cadence Learning and Support Portal (Cadence customer credentials needed):

• Using SimAI with vManager (For Regression Compression and Coverage Regain) (RAK) 
• Using SimAI with a Generic Runner (For Regression Compression and Coverage Regain) (RAK)

2. Using SimAI for Coverage Maximization and Targeting coverage holes

Reduce your Functional Coverage Holes by up to 40% using SimAI!

Verisium SimAI can be used for iterative coverage maximization. This is most effective when regressions are largely saturated, and SimAI will explicitly try to hit uncovered bins, which may be hard-to-hit (but not impossible) coverage holes. This is achieved using iterative learning technology where with each iteration, SimAI does some exploration and determines how well it performed. This technique can also be used for bug hunting by using holes as targets of interest.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Coverage Maximization - vManager flow (RAK) 
• Using SimAI for Coverage Maximization - Generic Runner Flow (RAK)

3. Using SimAI for Bug Hunting

Discover and fix bugs faster using SimAI!

Verisium SimAI has a new bug hunting flow which can be used to target the goal of exposing hard-to-hit failure conditions. This is achieved using an iterative framework and by targeting failures or rare bins. The goal to target failures is best exercised when the overall failure rate is typically low (below 5%). Iterative learning can be used to improve the ability to target specific areas. Use the SimAI bug hunting use case to target rare events, low hit coverage bins, and low hit failure signatures.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Bug Hunting with vManager (RAK) 
• Using SimAI for Bug Hunting – Generic runner flow (RAK) 

Unlock compute savings, reduce your functional coverage holes, and discover and fix bugs faster with the power of machine learning technology now enabled by Verisium SimAI!

Please keep visiting  https://support.cadence.com/raks to download new RAKs as they become available.

Please note that you will need the Cadence customer credentials to log on to the Cadence Online  Support  https://support.cadence.com/, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies.

Happy Learning!

In SoC development, the verification cycle is a crucial phase that ensures products meet their specifications and function correctly. However, the complexity of modern SoC projects, with their constant data flow, multiple validation teams working in parallel, and tight schedules, presents significant challenges. This article explores these challenges and introduces Verisium Manager as a solution that embodies the 'One Tool Fits All' concept. This means that Verisium Manager is designed to handle all aspects of the verification process for SoC development, from planning to coverage analysis to regression testing, thereby addressing the complex needs of SoC verification.

The Hurdles in Traditional Validation Cycles

 A typical validation process involves planning, coverage analysis, and regression testing. This complexity is compounded by using separate tools for each activity, leading to multiple control environments, APIs, and databases, not to mention the array of tool owners. Such fragmentation results in constant data transfer and translation between systems, from the planning tool to the coverage analysis tool and then to the regression testing tool. This continuous movement of data causes delays, system instability, poor user experiences, and, ultimately, a dip in the quality of the validation process.

The use of multiple platforms leads to inefficiency and reduced productivity. What's needed is a unified system that can streamline the workflow, simplify the verification process, and enhance its effectiveness.

Envisioning the Ideal Solution: Verisium Manager

 The cornerstone of an efficient validation cycle is integration and simplicity. The ideal solution is a singular platform that consolidates planning, coverage analysis, and regression management into one smooth, unified process. Verisium Manager emerges as this much-needed solution, encompassing all the functionalities necessary to streamline the validation process. Its comprehensive nature instills confidence in its ability to handle all aspects of the verification cycle. It can be fully customized to address and enforce any validation methodology and can facilitate smooth integration into any customer environment.

Features that stand out in Verisium Manager include: 

• Unified Workflow: It acts as a single cockpit from which all activities are orchestrated, ensuring the validation teams' work is uninterrupted and seamlessly integrated.
• Customization and Integration: Verisium Manager supports customizing test-plan structures and mapping results per project, ensuring a perfect fit for various project requirements. Its ability to smoothly integrate into the project's environment and compute platforms is unparalleled.
• Support for Continuous Updates and Migration: The tool accommodates constant updates to project data and supports the migration of legacy data, ensuring that no historical data is lost in the transition to a new system.

Addressing Project-Specific Needs

 Verisium Manager recognizes diversity in different projects and offers project-specific solutions, including:

 Enforcing Project Test-Plan Structures and Attributes: It supports and enforces each project's unique test-plan structure and mapping guidelines.

• Unified Data Views and Measurements: Verisium Manager promotes a unified view of data across all teams and enforces unified measurements, ensuring consistency and clarity in the validation process.
• Enabling Project-Specific Actions and Integrations: The tool is designed to support project-specific actions directly from its graphical user interface and allows for smooth integration with in-house databases, dashboards, and the project execution stack.

Verisium Manager is the epitome of efficiency in software/hardware validation. Its differentiating features, such as support for customization, unified data view, and comprehensive coverage and regression requirements, make it an indispensable tool for any validation team looking to elevate their workflow.

Wild River Technology (WRT), the leading supplier of signal integrity measurement and optimization test fixtures for high-speed channels at data rates of up to 224G, has announced the availability of a new advanced channel modeling solution that helps achieve extreme signal integrity design to 70GHz. Read the press release. The CMP-70 program continues the industry-first simulation-to-measurement collaboration with Cadence that was initially established with the CMP-50. Significant resources were dedicated to the development of the CMP-70 by Cadence and WRT over almost three years. The CMP-70 will be on display at DesignCon 2025 , January 28-30, in Cadence booth 827 to benchmark the Cadence Clarity 3D Solver . “I am not a fan of hype-based programs that simply get attention,” remarked Alfred P. Neves, WRT’s co-founder and chief technical officer. “Both Cadence and Wild River brought substantial skills to the table in this project as we continued our industry-first simulation-to-measurement collaboration. The result is a proven, robust and accurate platform that brings extreme signal integrity to 70GHz designs. This application package has also been instrumental in demonstrating the robust 3D EM simulation capability of the Cadence Clarity solver.” “We’re delighted to continue the joint development and validation program with WRT that started with the CMP-50,” said Gary Lytle, product management director at Cadence. “The skilled and experienced signal integrity technologists that both companies bring to the program results in a superior signal integrity solution for our mutual customers.” CMP-70 Solution Features The solution is available both in a standard configuration and as a custom solution for customer-specific stackups and fabrication. The primary target application is to support a 3D EM solver analysis modeling versus the time- and frequency-domain measurement methodologies. The solution features include: The CMP-70 platform, assembled and 100% TDR NIST traceable tested, with custom stands Material Identification overview web-based meeting including anisotropic 3D material identification A cross-section PCB report and structures for using as-fabricated geometries Measured S-parameters, pre-tested for quality (passivity/causality and resampled for time domain simulations) A host of novel crosstalk structures suited for 112G HD level project analysis PCB layout design files (NDA required) An EDA starter library including loss models with industry-first accurate surface roughness models Comprehensive training available for 3D EM analysis – correspondence, material ID in X-Y and Z axis for a host of EDA tools Industry-First Hausdorff Technique The WRT application package also includes an industry-first modified Hausdorff (MHD) technique , included as MATLAB code. This algorithmic approach provides an accurate way to compare two sets of measurements in multi-dimensional space to determine how well they match. The technique is used to compare the results simulated by the Clarity solver with those measured on the CMP-70 platform. The methodology and initial results are shown in the figure below, where the figure of merit (FOM) is calculated from 10, 35, and finally to 50GHz. The MHD algorithm requires a MATLAB license, but WRT also accommodates customer data as another option, where WRT provides the comparison between measured and simulated data. Additional Resources If you are attending DesignCon 2025 , be sure to stop by Cadence booth 827 to see WRT’s CMP-70 advanced channel modeling solution in action with the Clarity 3D Solver. Check out our on-demand webinar, " Validating Clarity 3D Solver Accuracy Through Measurement Correlation ." Learn more about the CMP-70 solution and the Clarity 3D Solver . For more information about Cadence’s full suite of integrated multiphysics simulation solutions, download our Multiphysics System Analysis Solutions Portfolio .

This year, the Cadence Giving Foundation (CGF) launched Fem.AI to achieve a more inclusive tech sector, and the inaugural Fem.AI Summit that took place on October 1 was a luminary in a world where technology is evolving at an unprecedented pace. The summit not only excelled in its mission to enlighten, empower, and mobilize stakeholders across various industries on the issue of gender disparity in high tech and AI, but was a celebration of innovation, diversity, and empowerment. As we reflect on the moments that made the summit unforgettable, it's clear that the event was more than just a meeting of minds—it was a movement for change! Shaping Tomorrow Together Cadence’s president and CEO, Anirudh Devgan, stated, “Women’s talent and perspectives are crucial to shaping the future of AI.” Devgan’s words epitomized the driving force behind the first-ever Fem.AI Summit which brought together innovators, educators, business leadership, and investors across industries to create an ecosystem that ensures women can fully participate in the AI revolution and burgeoning AI economy. The energy of pioneers ready to collectively disrupt the status quo filled the air, and as the day-long summit began, it became clear that we were part of something truly groundbreaking. The event's lineup of speakers held discussions that went beyond the technical aspects of AI, emphasizing the vital importance of diversity in technology. Such insights were lent by leading voices from MIT, Stanford, and UC Berkeley, who set the stage for inspiring discussions with speakers like Dr. Joy Buolamwini, Founder of the Algorithmic Justice League, and Reshma Saujani, Founder and CEO of Moms First and Girls Who Code. Included in this lineup of leading figures was Dr. Chelsea Clinton, Vice Chair of the Clinton Foundation, who left us with her hopes for the future of women in AI: “I’m hoping because of company-wide commitments like what we’re experiencing here today thanks to Cadence, that the people who will be part of designing [future technologies] will have a different group of people around the proverbial table or the computer screens doing that… and that women will be more integral into the conceptualization and then the actualization of AI-driven enterprises.” The hopes and visions for women in AI cannot manifest in a vacuum, they must be achieved with the support of individuals and systems from education all the way to the upper echelons of leadership. It is with this understanding, that Fem.AI is committed to investing in women at every stage of their STEM journey. Breaking Barriers It is with this ideal that we were honored to hear from women breaking through barriers of gender, race, and class in achieving pinnacles of success in areas of science and technology. Dr. Sarah H. Chen, Postdoctoral Researcher at Stanford and Thriving Stars Scholar at MIT, Niki Karanikola, Machine Learning Engineer and Break Through Tech AI Scholar at MIT, and Katya Echazarreta, NASA’s first Mexican Astronaut, showcased the resilience and determination that drive progress within and beyond our industry. Through their stories of persevering despite all odds, we were reminded that supporting students in STEM can create generational change with impacts beyond the realms of AI and technology. The final speaker at the Cadence Fem.AI Summit, the trailblazing Brandi Chastain, Founder of Bay FC, World Cup Champion, and Olympic Gold Medalist, left us with a powerful reminder that when faced with this opportunity: “Our purpose needs to be intentional” especially in building the future of technology and AI where “diversity is not something to be afraid of, but something to be embraced.” Echoing this sentiment, summit attendees left the event reminded of the crucial role we collectively play in ensuring women are part of this tech revolution. Moving Forward While the summit may have concluded, its impact will continue through individuals, companies, and communities aspiring to achieve an equitable tech sector. This is just the start, and we must take collective action now. We hope that you will join Cadence to ensure that we clear the path and catalyze women's role in the AI revolution! Meet Our Partners Our partners are making Fem.AI’s vision a reality through their important work advancing women in technology, including fostering STEM excellence in higher education, launching STEM careers, and achieving gender diversity in leadership. Learn more about the important work of each of our partners by visiting their pages: Break Through Tech Last Mile Education Fund Fast Forward Generation VC Include Global Semiconductor Alliance Join the Fem.AI Alliance Joining the Fem.AI Alliance signals that your company or institution is committed to evolving the AI workforce. By increasing the representation of women in AI, we aim to broaden the talent pool and the perspective so that AI represents us all. Through the Fem.AI Alliance, companies and institutions can share best practices, guidance, and inspiration. Since its launch, companies like the Equinix Foundation, NetApp, NVIDIA, Unity Technologies, and Workday have joined the Alliance in their commitment to Fem.AI’s work and mission. Visit Fem.AI to get involved today or contact Fem.AI@cadence.com .