1. Has AIMIM’s Owaisi, the dark horse in Maharashtra elections, played a winning move?  Hindustan Times
2. Video | Maharashtra Election Will Throw Up Fractured Mandate: A Owaisi's Party Leader  NDTV
3. Owaisi backs Maratha reservation ahead of Maharashtra Assembly polls  India Today
4. Need to fight unitedly by Muslims, Maratha and Dalits: Barrister Owaisi.  Etemaad
5. No one can say Uddhav Thackrey won't go back to BJP: AIMIM  The Times of India

1. Chennai rain: IMD predicts heavy rainfall for Tamil Nadu. Are schools, colleges closed today?  Hindustan Times
2. Chennai rains today: Heavy downpour expected in many Tamil Nadu districts, IMD issues alert. Schools shut today?  Mint
3. Low pressure weakens, but heavy rain in Tamil Nadu may persist  The New Indian Express
4. Tamil Nadu weather: Schools shut in Chennai, IMD puts 17 districts in state on heavy rainfall alert  Business Today
5. Tamil Nadu rains: Schools, colleges closed in several districts amid heavy rain  The Hindu

1. Elon Musk, Vivek Ramaswamy to lead DOGE to clean up US bureaucracy: Trump  India Today
2. Trump’s 'Manhattan Project' of government reform: Musk and Ramaswamy to lead efficiency crusade  The Times of India
3. Democrat Senator's 'efficient' dig at Elon Musk-Vivek Ramaswamy heading DOGE  India Today
4. Donald Trump picks Elon Musk, Vivek Ramaswamy to lead newly formed Department of Government Efficiency (DOGE)  The Hindu
5. A dope for DOGE (and Dogecoin): Trump taps Musk in efficiency team, crypto fans rejoice  The Economic Times

The ASUS ROG Phone 9 has recently been spotted on Geekbench where it appears to be powered by the new Qualcomm chipset.

The post ASUS ROG Phone 9 spotted on Geekbench with Qualcomm’s latest chipset appeared first on Phandroid.

Atlas Biomed's website is no longer active and the phone number listed is dead as well.

In this clip, Steve Jobs pauses for 18 seconds to contemplate a question deeply before answering.

The $20 Merry Multiplier scratch-off ticket she chose turned out to be a $250,000 top prize winner.

A Bengaluru-based entrepreneur recently took to social media to jokingly explain how his daily commute on bike taxes in the city doubles as an unexpected fitness routine.

The prankster claims that as many as seven schools fell prey to his prank and made the hats.

US-based comedian Austin Nasso is going viral online for his hilarious impersonation of US-President-elect Donald Trump during a fictional visit to India.

Arduino’s MKR family of products got two new wireless connectivity boards added to its range of products. These include MKR WiFi 1010 and MKR NB 1500, both aimed at streamlining IoT product/service development.

Arduino’s blog notes that “the Arduino MKR WiFi 1010 is the new version of the MKR1000 with ESP32 module on board made by U-BLOX.”

MKR WiFi 1010: For prototyping of WI-FI based IoT applications

The core difference of MKR WiFi 1010 compared to MKR WiFi 1000 is that the former can be put to use in production-grade IoT apps and it has ESP32-based module manufactured by u-blox. The former enables to add 2.4GHz WiFi and Bluetooth capability to the application. Additionally, it comes with a programmable dual-processor system (an ARM processor and a dual-core Espressif IC).

MKR NB 1500: For on-field monitoring systems and remote-controlled LTE-enabled modules

The Arduino MKR NB 1500 is based on new low-power NB-IoT (narrowband IoT) standard. This makes it appropriate for IoT apps running over cellular/LTE networks.

Key use cases of this board are remote monitoring systems and remote-controlled LTE-enabled modules. It supports AT&T, T-Mobile USA, Telstra, Verizon over the Cat M1/NB1 deployed bands 2, 3, 4, 5, 8, 12, 13, 20 and 28.

Arduino also pitches this board to be used in IoT apps which used to rely on alternative IoT networks such as LoRa and Sigfox. It promises to save power compared to GSM or 3G cellular-based connections.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

[Parliament of South Africa] Parliament, Tuesday, 12 November 2024 - The National Assembly (NA) will hold a plenary session scheduled to start at 10:00. Among the items on the agenda from 10:00 to 13:00 is the statement by the Minister of Water and Sanitation on water security in the country and a debate on 16 Days of Activism for no violence against women and children. The debate will be held under the theme, "Marking 30 years of democratic rights for women and fostering national unity to end gender-based violence".

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

Hi there, 

we've encountered some strange behavior when trying to run the "check_litho" command from within INNOVUS 22.14. We set the required files and configuration files according to our PDK documentation. The command, without the absolute file paths, is:

check_litho -sign_off -cpu 96 -run_mode fg -create_guides -map_file <map file path> -config <config file path> -techfile <tech file path> -dir <output dir path> -write_stream_options "-mode ALL -merge <list of gds files>" -apply squishHints

We are currently using PEGASUSDFM 23.20 for this command but tested previous PEGASUSDFM and MVS versions as-well. After we issued the previous command, we see INNOVUS launching the PEGASUSDFM/MVS and trying to run the command. After some time, the command crashes with the error "mdb_load_with_extra: failed to pre-open extra input file './preproc/INTERMEDIATE.oas' for read". We have tested a similar setup with INNOVUS 19.10 where we did not have this issues. Did something change with the new INNOVUS version? Does anyone have an idea what we are missing? 

Thanks in advance.

Best regards,

PS

Hi everyone,

I'm designing a digital chip that will be fabricated. I have a HDL top module that includes several submodules inside it. I want to define the position of some of the submodules during the PnR so that later I can specify there positions in the Micrograph photo after the IC fabrication. When I perform the PnR using Innovus, I always got a layout shape where the submodules seems to be flatted. I wonder if there is a way to specify the placement of each submodule in my top module  (maybe in the tcl file) during the PnR so later I can define there positions in the micrograph photo. 

Thanks in Advance!

Hi everyone,

I'm new to using Innovus and I'm encountering an issue while trying to perform the "init_design" command. My goal is to perform the place and route. Here are the commands I'm using:

``
set init_verilog ./test.v
set init_top_cell TEST
set init_pwr_net {VDD VDD_2 VDD_3}
set init_gnd_net {VSS VSSA}
set init_lef_file { /home/laumecha/uw_openroad_free45/pdk/Drexel-ECEC575/Encounter/NangateOpenCellLibrary/Back_End/lef/NangateOpenCellLibrary.lef}
set init_mmmc_file {./viewDefinition.tcl}
init_design
```

However, I receive the following error:

```
#% Begin Load netlist data ... (date=06/04 12:07:50, mem=1478.7M)
*** Begin netlist parsing (mem=1439.0M) ***
Created 0 new cells from 0 timing libraries.
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
**ERROR: (IMPVL-209):   In Verilog file './test.v', check line 16 near the text # for the issue: 'syntax error'.  Update the text accordingly.
Type 'man IMPVL-209' for more detail.
Verilog file './test.v' has errors!  See above.

*** Memory Usage v#1 (Current mem = 1439.027M, initial mem = 634.098M) ***
#% End Load netlist data ... (date=06/04 12:07:50, total cpu=0:00:00.0, real=0:00:00.0, peak res=1478.7M, current mem=1478.7M)
**ERROR: (IMPVL-902):   Failed to read netlist ./test.v. See previous error messages for details.  Resolve the issues and reload the design.
```

However, the file works perfectly in Genus.

It seems there is a syntax error in my Verilog file at line 16, but I'm not sure how to resolve it. Any guidance or suggestions would be greatly appreciated.

Thanks in advance!

I am trying to remove the cdn_loop_breaker cells from the netlist. 
When I tried the below 2 things, genus synthesis tool removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1.  remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker  comand without the -instances switch
2. remove_cdn_loop_breaker  
     
both of the above things are not providing the proper connections after removing the loop_breaker_cells

can anyone suggest the best possible workaround for this please?

Hi all,

I have been following the tutorial "Innovus Block Implementation with Stylus Common UI", version 23.1.

While I was doing the clock tree synthesis, the tutorial calls for a command

clock_opt_design

But my tool tells me this is a beta feature which needs to be enabled.

Warning: clock_opt_design requires beta feature innovusClockOptFlow enabled.

Can I ask how do I enable this beta feature?

My version of Innovus is v21.35-s114_1, is it because of the version incompatibility?

Many thanks

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

Hi, I'm using genus (Version 21.14-s082_1) to synthesis a VHDL-design with multiple power-domains. After reading the power intent file and calling 'apply_power_intent',  I get the following warning:

Warning : Potential problem while applying power intent of 1801 file. [1801-99]
: Cannot find any instance for scope '/:CHIP_TOP'. Rest of commands in this scope will be skipped (set_scope:../../upf/CHIP_TOP.upf:2).
: Check the power intent. If the scenario is expected, this message can be ignored.

The fist two lines of CHIP_TOP.upf:

upf_version 3.1
set_scope :CHIP_TOP

I simulated the same  UPF and VHDL files with Xeclium and was able to verify all the IEEE1801/UPF aspects I need without any problems. I don't know, why genus is having a problem with the 'scope'.
In genus, after getting the warning, running 'set_db power_domain:CHIP_TOP/BLOCK_A/PD_CORE_D .library_domain PD0V5' returns the following error:

Error : <Start> word is not recognized. [TUI-182] [set_db]
: 'power_domain:CHIP_TOP/BLOCK/PD_CORE_D' is not a recognized object/attribute. Type 'help root:' to get a list of all supported objects and attributes.
: Check if the given <Start> word is a valid object_type, object or attribute.

Running 'commit_power_intent' gives me:

Started inserting low power cells...
====================================
Info : Command 'commit_power_intent' cannot proceed as there are no power domains present. [CPI-507]
: Design with no power domains is 'design:CHIP_TOP'.
Completed inserting low power cells (runtime 0.00).
====================================================

I'm suspecting that the problem lies in 'set_scope' and VHDL. I never had such problems with Verilog. I tried every way to reference the hierarchy in the code and now I'm at my wit's end and I need your help o/
How to set the scope with 'set_scope' in UPD 3.1 to the toplevel in VHDL, so that genus accepts it? Or is the problem caused by something else?

Best,

Iqbal

for debug I use suspend in my tcl script to debug，here is the code

after that the innovus command screen become 

how to quit the SUSPEND status？ thanks

Hi all, 

I have made a custom cell in Innovus that I will be instantiating into a bigger block, which I will also be using Innovus to do the Place & Route. 

I understand that I can generate a *.lef file and a *.lib file using Innovus. However, I need to also create a *.db file (these format of files are often used in DC Compiler synthesis tool). 

Is there a way to create the *.db file from Innovus? Or, is there a tool that I can use to create this *.db file? 

Thank you for your time. 

I am attempting to use dbGetNeighbor() function inside the dynamic display HUD so that the distance to the next metal on that layer could be viewed. Think of another line in this dynamic table here... 

My SKILL code is essentially the following:

procedure(getNearestNeighborOnMetal(cv)
let((direction tmpBoundingBox)
direction = internal_function()
tmpBoundingBox = dbCreateRect(geGetEditCellView() "tmp" list(hiGetCommandPoint() hiGetCommandPoint()))
car(dbGetNeighbor(geGetEditCellView() tmpBoundingBox direction))
)
)

this returns the distance to the closest metal based on some tests.

Next, I try to register this function to work in the Dynamic Display / Info Balloon world by executing odcRegisterCustomFunc() for each and every object type (I know, absurd, but trying to debug)

In the dynamic display menu, I toggle the "Custom SKILL Function" check in layoutXL, then hit apply, then OK.

After this I find I am unable to view the changes reflected in any info balloons or in the drawing HUD (above) for this wire. I have tried replacing my function with the sample "customFunc" from the odcRegisterCustomFunc() documentation and was still unable to produce any new output.

Any help diagnosing the use of this feature would be very much appreciated

Hello,

I would like to create a button for my form that prompts the user to click on a cellview and draw a rectangle bounding box, exactly like the one used in the Area and Density Calculator. Can someone please help me with this?

Thanks!

Beto

Hi guys,

I see that inside VNC I can’t resize window boxes by mouse. While pressing the arrow at the box edge and dragging it nothing happens:

is it a bug, or setup change require?

Noted, it only happens when trying to resize window box from left and right side..

Thx

Hi All,

I'm using a code (abConvertPolygonToPath.ils) that I found in other posts to convert a rect object to a path object inside a pcell code, but when I try to run a DRC, the layout export fails due to a warning message, here is the log message

*WARNING* (DB-270001): Pcell evaluation for 18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout has the following error(s):

*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" abConvertPolygonToPath))

ERROR (XOASIS-231): Pcell evaluation failed for '18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout' because the Pcell SKILL code contains either a syntax error or an unsupported XOasis function. Check the standard output or the Virtuoso log file for more information. Cadence recommends correcting the Pcell SKILL code to resolve the issue. However, to ignore these errors and continue the translation, you may use the 'ignorePcellEvalFail' option.

INFO (XOASIS-282): Translation Failed. '1' error(s) and '3' warning(s) found.

And when compile the code I get the following message:

*WARNING* defgeneric function already defined - abConvertPolygonToPath

I will aprreciate any help in how to waive this error, or fix it.

Thank you

Hello All:

I am looking for help on the following, as I am new to Cadence tools [I have to use Cadence Innovus for Physical Design after Logic Synthesis using Synopsys Design Compiler, using Nangate 45 nm Open Cell Library]: while using Cadence Innovus, I would need to select a few specific nets to be routed through a specific metal layer. How can I do this on Innovus [are there any command(s)]? Also, would writing and sourcing a .tcl script [containing the command(s)] on the Innovus terminal after the Placement Stage of Physical Design be fine for this?

Secondly, is there a way in Innovus to manipulate layout components, such as changing some pin placements, wire directions (say for example, wire direction changed to facing east from west, etc.) or moving specific closely placed cells around (without violating timing constraints of course) using any command(s)/.tcl script? If so, would pin placement changes and constraining some closely placed cells to be moved apart be done after Floorplanning/Powerplanning (that is, prior to Placement) and the wire direction changes be done after Routing? 

While making the necessary changes, could I use the usual Innovus commands to perform Physical Design of the remaining nets/wires/pins/cells, etc., or would anything need modification for the remaining components as well?

I would finally need to dump the entire design containing all of this in a .def file.

I tried looking up but could only find matter on Virtuoso and SKILL scripting, but I'd be using Innovus GUI/terminal with Nangate 45 nm Open Cell Library. I know this is a lot, but I would greatly appreciate your help. Thanks in advance.

Riya

Dear all, 

I'm trying to perform an LVS check using Calibre between a layout that was generated by Innovus and the initial netlist generated by Genus. However, once I hit Run LVS on Calibre, it reports the following warnings and recommends to stop the process:

Source netlist references but does not define more than 10 subckts:
DFD1BWP7T
DFKCND1BWP7T
DFKCNQD1BWP7T
DFKSND1BWP7T
DFQD1BWP7T
IND2D0BWP7T
INR2D0BWP7T
INVD0BWP7T
INVD2P5BWP7T
IOA21D0BWP7T
... (and more)

If I proceed the LVS process it shows lots of errors as shown in the following image:

Why Genus doesn't include the definition of those sub circuits in the generated netlist? Is this related to Flat/Hierarchy netlisting? 

I have included my Genus scripts as well as the generated netlist in the attachments (and here - if attachment don't work).

Many thanks,

Anas

Hello,

I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help 

 -submit waveform loadsignals -using "Waveform 2" FB1.svwf but it gives me the below error

-submit waveform new -reuse -name Waveforms

I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes the transmission gate alongside standard cells?

Could you provide guidance or a methodology for integrating custom cells, like the transmission gate, into the synthesis flow for accurate analysis?

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more)

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3-compatible rates of 10.3125 Gbps (for Gen 2) and 20.625 Gbps (for Gen 3). It becomes very important to verify the Thunderbolt  backward compatibility with the designs. Though the support of USB4 Interoperability with Thunderbolt  3 (TBT3) is optional in USB4 host or USB4 peripheral device and required USB4 Hub and USB4 Based Dock but it is very essential to work in the existing ecosystem. 

Few Main features of USB4 Interoperability with Thunderbolt  3 (TBT3) Systems

• Support for Bi-Directional Pins & Retimers: TBT3 Active Cables can contain two bidirectional Re-timers which have the capability to send AT Responses on its RX channel. Router connected directly to such Retimer needs to support A Router that is connected directly to a bidirectional Re-timer shall support reception of Transactions on both TX and RX channels. 

• Bounce Mechanism: This feature is used by Router to access the Register Space of a Cable Re-timer that can only be accessed by its Link Partner.
• Asymmetric Negotiation: The Router which connects with Cable Retimers needs to follow Asymmetric TxFFE in Phase 5 of Lane Initialization. 
• USB4 Link Transitions: In TBT3 mode, the configuration of two independent Single Lane Links can be used non-transient state or Single Lane Link just using the Lane1 Adapter.

Cadence has a mature USB4 Verification IP solution that can help in the verification of USB4 designs with TBT3. Cadence has taken an active part in the Cairo group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members. If you plan to have a USB4-compatible design, you can reduce the risk of adopting new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team, for more details.

Achieving optimal power transfer in RF PCBs hinges on meticulously routed traces that meet specific impedance requirements. Impedance matching is essential to ensure that traces have the same impedance to prevent signal reflection and inefficient pow...(read more)

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.

Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available.

Follow these steps to Align Components using Offset Mode:

1. Set Application Mode to Placement Edit.
2. Drag the components that need to be aligned and right-click and choose Align Components.
3. Now, in the Options tab, you will notice Spacing Section with Equal Offset. You can equally and individually offset the components by using the +/- buttons for increment or decrement.

Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD).

The splash screen for Allegro X APD will appear as shown below, instead of showing APD+ 2023:

For the Windows Start menu in 23.1, it will display as Allegro X APD 2023 instead of APD+ 2023, as shown below

23.1 Start menu 

In the Product Choices window for 23.1, you will see Allegro X Advanced Package Designer in the place of Allegro Package Designer +, as shown below: 

23.1 product title

Have you ever encountered ERROR(SPMHNI-67) while importing logic? If yes, you might already know that you had to export libraries of the design and make sure that paths (devpath, padpath, and psmpath) include the location of exported files.  

Starting in SPB23.1, if you go to File > Import > Logic/Netlist and click on the Other tab, you will see an option, Reuse device files for existing components. 

After selecting this option, ERROR(SPMHNI-67) will no longer be there in the log file, because the tool will automatically extract device files and seamlessly use them for newly imported data. In other words, SPB_23.1 lets you reuse the device / component definitions already in the design without first having to dump libraries manually. An excellent improvement, don’t you think?  

Starting from SPB23.1, a new option, Allow DRCs to surrounding metal, has been added in the Etch-Back form to allow DRCs to the surrounding objects. form to allow DRCs to the surrounding objects.

The Allow DRCs to surrounding metal option lets you see and adjust objects instead of the current behavior, which sacrifices the width of the mask for the trace.

• When this option is turned off, it maintains the EB mask to another object clearance.
• When this option is enabled, it keeps the EB mask to the EM trace edge clearance and shows a DRC if the EB mask to another object spacing is out of rule.

At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net, and it is required to push the new net to all its connected objects. At times, you might update the die or copy routing to other components, when a portion of routing gets the wrong net.

To propagate the net of the pin to all its physically connected objects, Allegro X APD uses the standalone command, Push Connectivity.

You can call the command through Logic > Push Connectivity.

Alternately, you can use the push connectivity command at the command line. Once the command is active, it lets you select pins or symbols that will be used to push net connectivity to all connected objects.

Presently, dynamic shapes and filled rectangles are not considered as part of connectivity. Static shapes are supported.