USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

The responsibility of programming routing tables lies with the Connection Manager. Connection Manager, having the complete view of the hierarchy of the routers, programs the routing tables at all relevant adapter ports. Accordingly, the USB3, PCIe and DisplayPort protocol tunneled packets are routed, and reach their respective intended destinations.

The diagrammatic representation below is an example of tunneling of USB3 protocol traffic from USB4 Host Router to USB4 Peripheral Device Router through a USB4 Hub Router. The path from USB3 Host to USB3 Device is depicted by routing tables indicated at A -> B -> C -> D, and the one from USB3 Device to USB3 Host by routing tables indicated at E -> F -> G -> H . Note that the Input HopID from and Output HopID to all three protocol adapters for USB3, PCIe and DisplayPort Aux traffic, are fixed as 8, and for DisplayPort Main Link traffic are fixed as 9.

Once the native protocol traffic come into the transport layer of a USB4 router, the transport layer of it does not know to which native protocol a tunneled packet belongs to. The only way a transport layer tunneled packet is routed through the hierarchy of the routers is using the HopID values and the information programmed in the routing tables.

The figure below shows an example of tunneling of all the three USB3, PCIe and DisplayPort protocol traffic together. The transport layer tunneled packets of each of these native protocols are transported simultaneously through the routers hierarchy.

 Cadence has a mature Verification IP solution for the verification of USB3, PCIe and DisplayPort tunneling. This solution also employs the industry proven VIPs of each of these native protocols for native USB3, PCIe and DisplayPort traffic.

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.

The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed for a transition. Until conditions for both are satisfied an adapter cannot transition to the next training sub-state.

As deduced from the lane adapter state machine section of USB4 specification, the reception condition for the next training sub-state transition is less strict than that of the transmission condition. For ex., for LOCK1 to LOCK2 transition, the reception condition requires only two SLOS symbols in a row being detected, while the transmission condition requires at least four complete SLOS1 ordered sets to be sent.

From the above conditions in the specification, it is a possibility that a lane adapter A may detect the two SLOS or TS ordered sets, being sent by the lane adapter B on the other end, in the very beginning as soon as it starts transmitting its own SLOS or TS ordered sets. On the other hand, it is also a possibility that these SLOS or TS ordered sets are not yet detected by lane adapter A even when it has met the condition of sending minimum number of SLOS or TS ordered sets.

In such a case, lane adapter A, even though it has satisfied the transmission condition cannot transition to the next sub-state because the reception condition is not yet met. Hence lane adapter A must first wait for the required number of ordered sets to be detected by it before it can go to the next sub-state. But this wait cannot be endless as there are timeouts defined in the specification, after which the training process may be re-attempted.

This interlocked way of operation also ensures that state machine of a lane adapter does not go out of sync with that of the other lane adapter. Such type of scenarios can occur whenever lane adapter state machine transitions to the training state from other states.

Cadence has a mature Verification IP solution for the verification of various aspects of the logical layer of a USB4 router design, with verification capabilities provided to do a comprehensive verification of it.