1 Netherlands Antillean Guilder = 0.7808 Canadian Dollar

1 Estonian Kroon = 0.0983 Canadian Dollar

1 Danish Krone = 0.2037 Canadian Dollar

1 Fiji Dollar = 0.6222 Canadian Dollar

1 New Zealand Dollar = 0.8604 Canadian Dollar

1 Croatian Kuna = 0.202 Canadian Dollar

1 Peruvian Nuevo Sol = 0.4124 Canadian Dollar

1 Dominican Peso = 0.0255 Canadian Dollar

1 Papua New Guinean Kina = 0.4086 Canadian Dollar

1 Brunei Dollar = 0.9919 Canadian Dollar

Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution, a next-generation RTL synthesis tool that takes physical awareness in some new directions.

Here are four important things to know about Genus technology:

• A massively parallel architecture improves turnaround time by up to 5X while maintaining quality of results
• The Genus solution synthesizes up to 10M+ instances flat without impacting power, performance and area (PPA)
• The Genus solution provides tight correlation with the Innovus Implementation System, using the same placement and routing algorithms
• Globally focused PPA optimization saves up to 20% datapath area and power

Compared to previous-generation products such as the Cadence Encounter RTL Compiler Advanced Physical Option, the Genus solution approaches physical synthesis in a different way. The Encounter solution applied physical optimization “at the tail end of synthesis,” said David Stratman, senior principal product manager at Cadence. “We were doing a final incremental push, but we could only do so much, since we had locked in a lot of the earlier steps from a logical-only synthesis perspective.”

Genus Synthesis Solution supports the physical synthesis features in the previous Encounter solution, but it also brings the full physical scope upstream to RTL logic designers. “It’s going to enable the unit-level RTL designer to gain the benefits of physical synthesis without having to understand it,” Stratman said. As an example, users can apply generic (unmapped) placement at the earliest stages of synthesis, using a lightweight version of the Innovus placement engine. The bottom line: “Genus is a full solution where every step of synthesis can be done physically.”

Getting Massively Parallel

If you bring physical data into synthesis, you need a way to improve capacity and runtimes, especially with today’s gigantic advance-node SoCs. That’s why a massively parallel architecture is the cornerstone of the Genus solution. In this way, the Genus solution is following in the footsteps of the Innovus Implementation System, which also provides a massively parallel architecture.

Both the Innovus and Genus solutions can handle blocks of 10M instances flat. Given that SoCs today may have up to 100M instances, and often up to 50-100 top-level blocks, this is an important capability. Many tools today will only handle blocks of 1M instances. As a result, design teams often have to constrain block sizes.

Genus technology offers timing-driven, multi-level design partitioning across multiple threads and machines. It enables a near-linear runtime scaling without impacting PPA. According to Stratman, the Genus solution will scale well beyond 64 CPUs for a large design, with a “sweet spot” around 8-20 CPUs for today’s typical block sizes. Runs that used to take days, he noted, can now be done in hours.

As shown below, Genus technology leverages parallelism at three levels. The Genus solution can distribute design partitions to multiple threads or CPUs, and also supports local algorithm-level multithreading on each machine with shared memory. An adaptive scheduler ensures the best use of the available CPUs.

Fig. 1 – Genus Synthesis Solution provides three levels of parallelism

With its massive parallelism, Stratman said, Genus technology can obtain production-level quality of results (QoR) in runtimes typically seen in “prototype-level” synthesis runs. The “secret sauce,” he said, is in the partitioning. Cadence has found a way to generate partitions in a way that “slices the design more intelligently, and takes advantage of the Genus database to merge partitions without losing timing, power, or area,” Stratman said.

Playing in the Sandbox

In the Genus Synthesis Solution, a process called “sandboxing” allows any subset or partition of a design to be extracted along with full timing and a physical context. Optimization algorithms will treat a sandbox as a complete design.

The “Clipper” flow clips out or extracts the context of the larger SoC blocks. “It’s kind of a skeleton floorplan but it has all the timing information,” Stratman said. These extracted contexts include all the critical physical information to make the right RTL synthesis choices at the unit level. This information is used to streamline the handoffs between unit-level RTL designers, integration engineers, and implementation engineers. It’s a way for logic designers to gain some physical knowledge without having to be a physical synthesis expert, or without having to run a full top-level synthesis.

Fig. 2 – Clipper flow provides context for unit-level blocks

Correlation with Innovus Implementation System

Although Genus technology can work with third-party IC implementation systems, it shares algorithms and engines with Innovus Implementation System, as well as a common user interface. As shown below, both the Genus and Innovus solutions use a table-based Quantus QRC parasitic extraction, effective current source model (ECSM) and composite current source (CCS) delay calculations, and a unified global routing engine. Timing and wire length claim a 5% correlation.

Fig. 3 – Genus Synthesis Solution offers tight correlation with Innovus Implementation System

Genus technology doesn’t model everything to the same level of accuracy as the Innovus solution, however. “We chose to be lighter weight and more nimble to get expected runtimes,” Stratman said. A tight correlation is possible because the Genus and Innovus solutions use a similar code base. This correlation will be tighter than that between Encounter RTL Compiler Advanced Physical Option and the Encounter Digital Implementation System today.

Genus Synthesis Solution uses a new Hybrid Global Router that provides the ability to resolve congestion and construct layer-aware, timing-driven wire topologies. This accelerates analysis and debug, and reduces iterations. Users can avoid blockages and see a full Manhattan route as opposed to “flight lines.” Layer awareness is particularly important, given the large RC variations within the metal stack at advanced process nodes.

A version of the Innovus GigaPlace engine is available within the Genus solution. Here, users can do an RTL-level generic gate placement early in the synthesis flow (“generic gate” means there is no mapping into standard cell libraries, but there’s still an area estimate). This helps designers understand PPA tradeoffs earlier.

While users can go all the way to a design-rule “legal” placement with Genus Synthesis Solution, this isn’t generally recommended. “You can do a placement and use the same algorithms as GigaPlace and get a nice correlation without all the runtimes and additional steps of doing a fully legal placement,” Stratman said.

So where does Genus technology end and Innovus technology begin? That’s up to the user. You could use the Genus solution for logical synthesis and run all physical implementation in the Innovus system. If you run physical synthesis within the Genus solution, there’s more work earlier in the flow, but you get better insights into downstream problems and reduce iterations.

“Physical synthesis should be no more than 2X [runtime] of logic synthesis,” Stratman said. “All of the runtime that moves up should be shaved off of the place-and-route stages, because now you can do lightweight incremental optimization and incremental placement. The overall flow should be runtime neutral or better.”

Be Globally Aware

Finally, Genus Synthesis Solution offers a globally focused early PPA optimization across the whole datapath, delivering up to a 20% area reduction in the datapath. Stratman noted that this capability is a follow-on to an RCP feature called “globally focused mapping” that can determine the best cells to use in a library. What’s new with the Genus solution is that this concept has been applied at the arithmetic level.

For example, there are many ways to configure a multiplier – you may want to prioritize speed, power, or size. In the past, Stratman noted, synthesis tools have not been very good at globally optimizing the architecture selection for PPA optimization. “We can [now] find the most efficient global datapath implementation for a given region,” he said.

For further information about the Cadence Genus Synthesis Solution, including a datasheet and technical product brief, see this landing page.

Richard Goering

Related Blog Posts

Designer View – RTL Synthesis Success Strategies at 28nm and Below

Front-End Design Summit: The Future of RTL Synthesis and Design for Test

Physically-Aware Synthesis Helps Design a New Computer Architecture

One reason for attending the upcoming Design Automation Conference (DAC 2015) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is the Cadence Theater, located at the Cadence booth (#3515). The Theater will host continuous half-hour customer and partner presentations from 10:00 am Monday, June 8, to 5:30 pm Wednesday June 4.

As of this writing, 43 presentations are scheduled. This includes 17 customer presentations, 23 partner presentations, and 3 Cadence presentations, The presentations are open to all DAC attendees and no reservations are required.

Cadence customers who will be speaking include engineers from AMD, ams, Allegro Micro, Broadcom, IBM, Netspeed, NVidia, Renesas, Socionet, and STMicroelectronics. Partner presentations will be provided by ARM, Cliosoft, Dini Group, GLOBALFOUNDRIES, Methodics, Methods2Business, National Instruments, Samsung, TowerJazz, TSMC, and X-Fab.

These informal presentations are given in an interactive setting with an opportunity for questions and answers. Audio recordings with slides will be available at the Cadence web site after DAC. To access recordings of the 2014 DAC Theater presentations, click here.

This Cadence DAC Theater presentation drew a large audience at DAC 2015

Here’s a listing of the currently scheduled Cadence DAC Theater presentations. The latest schedule is available at the Cadence DAC 2015 site.

Monday, June 8

Tuesday, June 9

Wednesday, June 10

In a Wednesday session (June 10, 10:00 am) at the theater, the Cadence Academic Network will sponsor three talks on academic/industry collaboration models. Speakers are Dr. Zhou Li, architect, Cadence; Prof. Xin Li, Carnegie-Mellon University; and Prof. Laleh Behjat, University of Calgary.

As shown above, there will be a giveaways for a set of Bose noise-cancelling headphones, an iPad Mini, and a GoPro Hero3 video camera.

See the Cadence Theater schedule for further details. And be sure to view our Multimedia Site for live blogging and photos and videos from DAC. For a complete overview of Cadence activities at DAC, see our DAC microsite.

Richard Goering

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DAC 2015: Tackling Tough Design Problems Head On

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design or verification engineer can use.

JasperGold was the initial (in fact only) product of Jasper Design Automation, acquired by Cadence in 2014. Jasper pioneered the formal Apps concept several years ago. While the company had previously sold JasperGold as a one-size-fits-all solution, Jasper began selling semi-automated JasperGold Apps that solved specific problems using formal analysis technology.

The new release is the next generation of JasperGold and will be available later this month. It includes three major improvements over previous Cadence and Jasper formal analysis offerings:

• A unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain over previous solutions.
• JasperGold is integrated into the Cadence System Development Suite, where it provides formal-assisted simulation, emulation, and coverage. As a result, System Development Suite users can find bugs three months earlier than existing verification methods.
• JasperGold’s formal analysis engines are integrated with the recently announced Indago debug platform, automating root cause analysis and on-the-fly, what-if exploration.

Best of Both Formal Verification Worlds

Taking advantage of technologies from both Cadence and Jasper, the new JasperGold represents a “best of both worlds” solution, according to Pete Hardee, product management director at Cadence. This solution combines technologies from the Cadence Incisive Enterprise Verifier and Incisive Formal Verifier with JasperGold formal analysis engines.

For example, to ease migration from Incisive formal tools, Cadence has integrated an Incisive common front end into the JasperGold apps platform. Jasper formal engines can run within the Incisive run-time environment. Cadence has also brought some selected Incisive formal engines into JasperGold.

As shown to the right, the JasperGold platform supports both the existing JasperGold front-end parser and the Incisive front-end parser. Hardee observed that this dual parser arrangement simplifies migration from Incisive formal tools to JasperGold, and provides a common compilation environment for people who want to use JasperGold with Incisive simulation. Further, the common run-time environment enables formal-assisted simulation.

The combination of JasperGold engines and Incisive engines supports two use models for formal analysis: formal proofs and bug hunting. In the first case, formal engines try all combinations of inputs without a testbench. The test is driven by formal properties written in languages such as SVA (SystemVerilog assertions) or PSL (Property Specification Language). Completion of a property is exhaustive proof that something can or cannot happen. This provides a “much stronger result” than simulation, Hardee said.

He also noted that formal analysis doesn’t necessarily require that all properties are completed. “You can get a lot of value even if proofs don’t complete,” he said. “Proofs that run deep enough to find bugs are just fine.”

Bug hunting involves random searches, and JasperGold bug hunting engines are very fast. However, these engines don’t necessarily use the most optimal path to get to a bug. So, Cadence engineers brought a constraint solver from Incisive and integrated it into JasperGold. “It looks at the constraints in the environment and gives you a better starting point,” Hardee said. “It takes more up-front time, but once you’ve done that the bug hunting engines can actually take a shorter path and find a bug a lot quicker.”

Another new JasperGold capability from the Incisive Formal Verifier is called “search pointing.” This uses simulation to penetrate deeply into the state space, and then kicks off a random formal search from a given point that you’ve reached in simulation. This technique makes it possible to find bugs that are very deep in the design.

It is probably clear by now that a number of different formal “engines” may be required to solve a given verification problem. Traditionally, a formal tool (or user) will farm a problem out to many engines and see which one works best. To put more intelligence into that process, Cadence launched the Trident “multi-cooperating engine” a couple of years ago. That has now been brought into JasperGold, where it helps “orchestrate” the engines according to what will work best for the design. This is a big part of the reason for the 15X speedup noted earlier in this post.

Integration with System Development Suite

The Cadence System Development Suite is an integrated set of hardware/software development and verification engines, including virtual prototyping, Incisive simulation, emulation, and FPGA-based prototyping. As shown below, JasperGold technology is integrated into the System Development Suite in several places, including formal-assisted debug, formal-assisted verification closure, formal-assisted simulation, formal-assisted emulation, and the Incisive vManager verification planning tool.

Formal-assisted emulation sounds like it should be easy, especially since Cadence has both accelerated verification IP (VIP) and assertion-based VIP. However, there’s a complication. Accelerated VIP represents less verification content than simulation VIP, because you have to remove many checkers to get VIP to compile on a Palladium emulator. That’s because the Palladium requires synthesizable code.

What you can do, however, is use assertion-based VIP in “snoop mode” as shown below. Assertion-based VIP coded in synthesizable SystemVerilog can replace the missing checkers in accelerated VIP. In this diagram, everything in the green box is running in the emulator and is thus completely accelerated.

Another example of formal-assisted emulation has to do with deep traces. As Hardee noted, emulation will produce very long traces, and it can be very difficult to find a point of interest in the trace and determine what caused an error. With formal-assisted emulation, users can find interesting events within the traces and create properties that mark them, so a debugger can find these events and trace back to the root cause.

Formal-assisted verification closure is available with the new JasperGold release. This is possible because you can use the vManager product to determine which tasks were completed by formal engines. It’s important information for verification managers who are not used to formal tools, Hardee noted.

Another aspect of formal-assisted verification closure is the JasperGold Unreachability Analysis (UNR) App, which can save simulation users weeks of time and effort. This App takes in the simulation coverage database and RTL, and automatically generates properties to explore coverage holes and determine if holes are reachable or unreachable. The App then generates an unreachable coverage point database. If the unreachable code does something useful, there’s a bug in the design or the testbench; if not, you don’t have to worry about it. The diagram below shows how it works.

Formal-Assisted Debugging

The third major component of the JasperGold announcement is the integration of formal analysis into the Indago debugging platform. As shown below, this platform has several apps, including the Indago Debug Analyzer. Two formal debug capabilities from the Jasper Visualize environment have been added to the the Indago Debug Analyzer:

• Highlight Relevant Logic: This highlights the “cone of influence,” or the logic that is involved in reaching a given point
• Why: This button highlights the immediate causes for a given event, and allows users to trace backwards in time

More formal capabilities will come with the Indago Advanced Debug Analyzer app, scheduled for release towards the end of 2015. This includes Quiet Trace, a Jasper capability that reduces trace activity to transactions relevant to an event. Also, a what-if analysis allows on-the-fly trace editing and recalculation to explore effects and sensitivities, without having to re-compile and re-execute the simulation.

Finally, Cadence has a Superlint flow that is now fully integrated with the JasperGold Visualize debugger. This two-tiered flow includes a basic lint capability as well as automated formal analysis based on the JasperGold Structural Property Synthesis app. “This could be a very good entry point for designers to start using formal,” Hardee said.

“Formal is taking off,” Hardee concluded. “People are no longer talking about return on investment for formal—they have established that. Now they’re supporting a proliferation of formal in their companies such that a wider set of people experience the benefit from that proven return on investment.”

Further information is available at the JasperGold Formal Verification Platform (Apps) page.

Richard Goering

Related Blog Posts

- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow

- Why Cadence Bought Jasper—A New Era in Formal Analysis

- Q&A: An R&D Perspective on Formal Verification—Past, Present and Future

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

- DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design

- Q&A with Nimish Modi: Going Beyond Traditional EDA

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference (DAC 2015) described collaboration models that are working today.

The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left to right in the photo below:

• Prof. Xin Li, Electrical and Computer Engineering, Carnegie-Mellon University (CMU)
• Chuck Alpert, Senior Software Architect, Cadence
• Prof. Laleh Behjat, Department of Electrical and Computer Engineering, University of Calgary

Alpert, who was filling in for Zhuo Li, Software Architect at Cadence, was the vice chair of DAC 2015 and will be the general chair of DAC 2016 in Austin, Texas. “My team at Cadence really likes to collaborate with universities,” he said. “We’re a big proponent of education because we really need the best and brightest students in our industry.”

Contests Boost EDA Research

One way that Cadence collaborates with academia is participation in contests. “It’s a great way to formulate problems to academia,” Alpert said. “We can have the universities work on these problems and get some strategic direction.”

For example, Cadence has been involved with the annual CAD contest at the International Conference on Computer-Aided Design (ICCAD) since the contest was launched in 2012. This is the largest worldwide EDA R&D contest, and it is sponsored by the IEEE Council on EDA (CEDA) and the Taiwan Ministry of Education. Its goals are to boost EDA research in advanced real-world problems and to foster industry-academia collaboration.

Contestants can participate in one of more problems in the three areas of system design, logic synthesis and verification, and physical design. The 2015 contest has attracted 112 teams from 12 regions. Cadence contributes one problem per year in the logic synthesis area. Zhuo Li was the 2012 co-chair and the 2013 chair. The awards will be given at ICCAD in November 2015.

Another step that Cadence has taken, Alpert said, is to “hire lots of interns.” His own team has four interns at the moment. One advantage to interning at Cadence, he said, is that students get to see real-world designs and understand how the tools work. “It helps you drive your research in a more practical and useful direction,” he said.

The Cadence Academic Network co-sponsors the ACM SIGDA PhD Forum at DAC, and Xin Li and Zhuo Li are on the organizing committee. This event is a poster session for PhD students to present and discuss their dissertation research with people in the EDA community. This year’s forum was “packed,” Alpert said, and it’s clear that the event needs a bigger room.

Finally, Alpert noted, Cadence researchers write and publish technical papers at DAC and other conferences, and Cadence people serve on the DAC technical program committee. “We try to be involved with the academic community on a regular basis,” Alpert said. “We want the best and the brightest people to go into EDA because there is still so much innovation that’s needed. It’s a really cool place to be.”

Research Collaboration Exposes Failure Rates

Xin Li presented an example of a successful research collaboration between CMU and Cadence. The challenge was to find a better way to estimate potential failure rates in memory. As noted in a previous blog post, PhD student Shupeng Sun met this challenge with a new statistical methodology that won a Best Poster award at the ACM SIGDA PhD Forum at DAC 2014.

The new methodology is called Scaled-Sigma Sampling (SSS). It calculates the failure rate and accounts for variability in the manufacturing process while only requiring a few hundred, or a few thousand, sample circuit blocks. Previously, millions of samples were required for an accurate validation of a new design, and each sample could take minutes or hours to simulate. It could take a few weeks or months to run one validation.

The SSS methodology requires greatly reduced simulation times. It makes it possible, Li noted, to run simulations overnight and see the results in the morning.

Li shared his secret for success in collaborations. “I want to emphasize that before the collaboration, you have to understand the goal. If you don’t have a clear goal, don’t collaborate. Once you define the goal, stick to it and make it happen.”

Contest Provides Learning Experience

Last year Laleh Behjat handed two of her new PhD students a challenge. “I told them there is an ISPD [International Symposium for Physical Design] contest on placement, and I expect you to participate and I expect you to win. Not knowing anything about placement, I don’t think they realized what I was asking them.”

The 2015 contest was called the Blockage-Aware Detailed Routing-Driven Placement Contest. Results were announced at the end of March at ISPD. And the University of Calgary team, despite its lack of placement experience, took second place.

Such contests provide a good learning tool, according to Behjat. Graduate students in EDA, she said, “have to be good programmers. They have to work in teams and be collaborative, be able to innovate, and solve the hardest problems I have seen in engineering and science. And they have to think outside the box.” A contest can bring out all these attributes, she said.

Further, Behjat noted, contest participants had access to benchmarks and to a placement tool. They didn’t have to write tools to find out if their results were good. Industry sponsors, meanwhile, got access to good students and new approaches for solving problems.

“You can see Cadence putting a big amount of time, effort and money to get students here and get them excited about doing contests,” she said. She advised students in the theater audience to “talk to people in the Cadence booth and see if you can have more ideas for collaboration.”

Richard Goering

Related Blog Posts

EDA Plus Academia: A Perfect Game, Set and Match

Cadence Aims to Strengthen Academic Partnerships

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

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I'm trying to generate IBIS models for the parts that I'm designing.  I'm designing using CADENCE Virtuoso.  

I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso.   Please pardon me if my question is broad.      

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• 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
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Hello, i saw that MAESTRO is a plotting addon is it a part of ADE EXPLORER?

i cant see the relation between the two.i started to read manual and regarding MAESTRO i only see code.

is there some simple examples?
Thanks.

Hello, i have a realy mistick thing going with copying libraries in cadence virtuoso,

When i copy straight forwart the whole library it gives me a warning that accsess was denied,but when i go into the library and copy it as a single file, then it goes fine.

another problem is it doesnt show in the massage console  ALL the files which could not be copied.(which is the much bigger problem,becuase i would have to pass threw all the subdirectories to verify if all files are there)

Is there a way to see which files wasnt able to be copied?

Thanks. 

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hello, I have a problem with a certain type of transistor,my hyrarchy has a lot components an sub components and visually inspecting them is very hard.

is there a way like in other cadence layout viewer tools , to enter the name of the component or a NET somewhere and it will focus on it visualy or give the hyrarchy path to it?

Thanks.

Hello

The document I referenced is https://filebox.ece.vt.edu/~symort/rfworkshop/Mixer_workshop_instruction.pdf. (This is cadence workshop document)

While following the pxf simulation in the above article, the results are different and I have a question.

My result picture is shown below.

<my result error>

<document result>

<my direct plot>

<document direct plot>

The difference with the documentation is that in the direct plot screen after the pxf simulation,

1.output harmonics-> input sideband

2.Frequency axis: out-> frequency axis: absin

3.The results for port0 (RF port) are also different (see photo below).

4.The frequency values in the box are different.

My screen shows 5G, 10G, 1K ~ 10M, but the document is the same as 1K ~ 10M.

Ask for a solution. Thank you.

Hi, all

Recently, I meet the simulation error as the picture shows when I simulate my circuit with transient.  how can I solve this problem?

thank you~

Hello, i am trying to produce a gain circles on a simple transistor as shown bellow.

i have defined the range from 1 til 30 dB and i dont get any circle just dots in infinity?

Where did i go wrong?
Thanks.

Hello, i have built a matching network of 13dB gain and  NF as shown bellow step by step.(including all the plots and matlab )

its just not working at all,i am doing it exacly by the thoery

taking a point inside the circle-> converting its gamma to Z_source->converting gamma_s into gamma_L with the formulla bellow as shown in the matlab->converting the gamma_L into Z_L-> building the matching network for conjugate of Z_L and Z_c.Its just not working.

where did i got  wrong?

Thanks.

gamma_s=75.8966*exp(deg2rad(280.88)*i);
z_s=gamma2z(gamma_s,50);
s11=0.99875-0.03202*i
s12=721.33*10^(-6)+8.622*10^(-3)*i
s21=-188.37*10^(-3)+30.611*10^(-3)*i
s22=875.51*10^(-3)-100.72*10^(-3)*i
gamma_L=conj((s22+(s12*s21*gamma_s)/(1-s11*gamma_s)))
z_L=gamma2z(gamma_L,50)

Hello, There is a manual in matlab of matching LNA  shown in the link bellow.

In it as shown in the plot bellow they mention input and output circle plots.

Is there such option of input and output circle in cadence virtuoso?

https://www.mathworks.com/help/rf/examples/designing-matching-networks-part-1-networks-with-an-lna-and-lumped-elements.html

Hello folks,

Greetings.

One of my customer claims that he is using Cadence IES version 18.09.011 with Vivado 2019.2. The version of IES that we officially support with Vivado 2019.2 is 15.20.073. Though the tool is forward compatible, I am not sure what are the versions of IES that are released after 15.20.073. Could you please give me a list of the versions of Cadence IES released after 15.20.073 and which is the latest version as of now ?

Best regards,

Chinmay

I'm trying to re-install ORCAD 17.2  in a PC from a DVD which I have upgraded from Win 7 to Win 10 and  now has a new 500GB SSD. While installing I got a Windows Application Error  0xc000007b. When I try to run ORCAD I get the same Error.

Looking for ways to fix this problem.

Hello All,

I'm currently using OrCAD PCB Designer Professional w/ PSpice (version 16.6-2015).  In the 'Design Object Find Filter' side bar, all options are grayed out and unselectable.  I did attempt to 'Reset UI to Cadence Default' without any luck.  A colleague has no issues with the identical file on his computer.  Any guidance would be much appreciated.  Thanks!

George

Hi There,

The variant bom I set gone dissapear. Is there any way to recover this back from the old design file? 

This is the second time it happen to me. Not really sure what could cause this. 

Thanks,

Pornchai

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

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