“What’s our plan if we get hit by a big flood?” While this question may be plenty familiar to emergency management professionals, city administrators, legislators, and other leaders in coastal regions that are known for their exposure to potentially disastrous weather events, these days it’s being asked in some unexpected [...]

The post Four technology tips for government leaders preparing for flood disasters appeared first on Government Data Connection.

The city of Heidelberg, Germany is known for its romantic cityscape, which attracts tourists from all over the world. It also has the youngest population in Germany, thanks largely to the many students at one of Europe's oldest and largest universities. Perhaps less well known is that Heidelberg is twinned [...]

The post Smart City Heidelberg: SAS Hackathon complements city's digital transformation journey appeared first on Government Data Connection.

Government employees charged with monitoring environmental compliance face a downpour of information, wading through countless reports and stacks of paperwork to accomplish their mission. To help these dedicated public servants increase productivity, agencies should consider a broader set of tools to control pollution, enforce regulations and improve compliance. Although foundational [...]

The post Time for government agencies to embed data and AI into environmental compliance appeared first on Government Data Connection.

Read the in depth Review of Marshall Woburn III Audio Video. Know detailed info about Marshall Woburn III configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Microsoft Ads on File Explorer were subject to widespread criticism and the company claimed it was “experimental” and “turned off”. But, there are other Windows 10 or Windows 11 ads you may want to get rid of.

Some businesses overlook alternative data. That's probably a mistake.

The post Alternative data may feel risky: Here's why it's not appeared first on The Data Roundtable.

The Congress will begin a month-long 'Delhi Nyay Yatra' from Rajghat on Friday to corner the Aam Aadmi Party government on various issues affecting the city.

Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

Bangladesh is pinning its hopes on one of the nation's most acclaimed intellectuals to bring stability to a country scarred by coups and political upheaval.

Jimmy Carter celebrated his 100th birthday on Tuesday - the first ever US president to reach the century mark and another extraordinary milestone for the one-time peanut farmer who found his way to the White House.

Ratan Naval Tata, the business titan and global icon who led the Tata behemoth from thirty countries to over a hundred since becoming chairman in 1991, died today at Mumbai's Breach Candy Hospital. He was 86.

US President-elect Donald Trump has named Mike Waltz, a Congressman from Florida and co-chair of the India Caucus, as the new National Security Adviser.

1. Pakistan Government's Firm Stance On Champions Trophy, Report Says PCB Told To...  NDTV Sports
2. ICC in a catch-22 situation amid PCB's steadfast stance on hosting Champions Trophy  Cricbuzz
3. Champions Trophy: PCB wants an explanation in writing from India for refusal to travel  ESPNcricinfo
4. 'Duniya bewakoof hai': Basit Ali gives unique solution to India-Pakistan Champions Trophy stand-off  The Times of India
5. Champions Trophy : Rizwan's welcome message for KL Rahul and Suryakumar  India Today

1. Delhi: India's capital chokes as air pollution turns 'severe'  BBC.com
2. Several flights diverted due to low visibility conditions at Delhi airport  The Times of India
3. Delhi's toxic air: Why you should not take your cough lightly  India Today
4. Delhi air pollution: Visibility near-zero amid thick smog; CPCB says AQI 'very poor', IQAir shows 'hazardous' | Details  Hindustan Times
5. Delhi's IGI airport sees flight diversions as season's first dense fog hits national capital  Moneycontrol

In a unique online romance scam, a man in Tianjin, China, fell victim to a bizarre "marriage bed burning" ritual, costing him Rs 11 lakh.

The video features models dressed in the latest fashion, strutting like mannequins on a moving runway outside the designer store ITIB.

The couple, together for nine years, had announced the wedding date in January and were eagerly looking forward to their long-awaited special day.

[GroundUp] Former Lavender Hill gangster died on 29 October

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[SAnews.gov.za] Twenty-three people in Gauteng have died as a result of food borne-related poisoning after consuming food from spaza shops.

[Premium Times] In September, Tyla made headlines at the MTV Video Music Awards (VMAs) for winning the "Best Afrobeats," but she stirred debate by clarifying that she identified with the Amapiano genre rather than Afrobeats

[Afropop] Thandiswa Mazwai has lived the modern history of African music. In the early '90s, when she was still a teenager, she pioneered the emerging kwaito sound in South Africa, first with a trio called Jack-Knife, and then as the lead vocalist and composer for Bongo Maffin. Thandiswa's 2004 debut album as a solo artist, Zabalaza, went double platinum and established her as a major star. Since then, she has delved into jazz, rock, classic African pop styles, and more. Her latest release, Sankofa, is an expansive

[COSATU] The Congress of South African Trade Unions (COSATU) is deeply concerned by the Minister for Communications and Digital Technologies, Mr. S. Malatsi's sudden withdrawal of the South African Broadcasting Corporation (SABC) SOC Ltd Bill from Parliament where it was being engaged upon by the National Assembly's Portfolio Committee: Communications and Digital Technologies.

Hi,

I have a string "[@global_vddi:%:vddi!]" which I need to process to remove "@[]" chars. The desired result is "global_vddi:%:vddi!". I tried the following in CIW

netExpr = "[@global_vddi:%:vddi!]"
rexCompile("\([a-zA-Z0-9_:!%]+\)")
t
rexExecute(netExpr)
t
rexSubstitute( "\0" )
"global_vddi:%:vddi!"

and I achieved the desired value. I added the same code to my script but it didn't work. In my script rexExecute returns 't' but rexSubstitute returns 'nil' 

Here is the snippet from my script

netExpr = dbGetTermNetExpr(term)
if(netExpr then
rexCompile("\([a-zA-Z0-9_:!%]+\)")
rexExecute(netExpr)
netExpr1 = rexSubstitute( "\0" )

...

. ..)  and trace log showing the variable values as the code executes

stopped before evaluating dbGetTermNetExpr(term)
after evaluating dbGetTermNetExpr(term)==> "[@global_vddi:%:vddi!]"
after evaluating (netExpr = dbGetTermNetExpr(term))==> "[@global_vddi:%:vddi!]"
stopped before evaluating if(netExpr then rexCompile("\([a-zA-Z0-9_:!%]+\)") rexExecute(netExpr) (netExpr1 = rexSubstitute("\0")) ... )
stopped before evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")
after evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")==> t
stopped before evaluating rexExecute(netExpr)
after evaluating rexExecute(netExpr)==> t
stopped before evaluating (netExpr1 = rexSubstitute("\0"))
stopped before evaluating rexSubstitute("\0")
after evaluating rexSubstitute("\0")==> nil
|[2]netExpr1 set to nil, was nil

Any help or suggestions as to why the code executes differently in CIW and when called from a SKILL script file will be much appreciated.

I also tried a different approach using rexReplace instead of rexSubstitute but couldn't get the regex pattern correct. The code I tried in CIW using rexReplace is as follows

a = "[@global_vddi:%:vddi!]"
"[@global_vddi:%:vddi!]"
rexCompile("\([@\[\]]*\)")
t
rexReplace(a "" 0)
"global_vddi:%:vddi!]"

Only '@[' get replaced and ']' is still present. The regex pattern contains '\]' to match the closing square bracket yet it is not replaced. Please let me know what I'm missing in these 2 scenarios.

Any help is much appreciated!!

Regards,

Confused SKILL user 

Hi All,

I'm using a code (abConvertPolygonToPath.ils) that I found in other posts to convert a rect object to a path object inside a pcell code, but when I try to run a DRC, the layout export fails due to a warning message, here is the log message

*WARNING* (DB-270001): Pcell evaluation for 18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout has the following error(s):

*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" abConvertPolygonToPath))

ERROR (XOASIS-231): Pcell evaluation failed for '18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout' because the Pcell SKILL code contains either a syntax error or an unsupported XOasis function. Check the standard output or the Virtuoso log file for more information. Cadence recommends correcting the Pcell SKILL code to resolve the issue. However, to ignore these errors and continue the translation, you may use the 'ignorePcellEvalFail' option.

INFO (XOASIS-282): Translation Failed. '1' error(s) and '3' warning(s) found.

And when compile the code I get the following message:

*WARNING* defgeneric function already defined - abConvertPolygonToPath

I will aprreciate any help in how to waive this error, or fix it.

Thank you

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

The automotive industry revolutionized the definition of a vehicle in terms of safety, comfort, enhanced autonomy, and internet connectivity. With this trend, the automotive industry rapidly adopted automotive Ethernet such as 10Base-T1, 100Base-T1, and in some cases, 1000Base-T1. 

Faster Speed (than CAN-FD), Scalability, embedded security protocols (like MacSec), cost and energy efficiency, and simple yet redundant network made Ethernet an obvious choice over CAN(FD) and FlexRay.  

Ethernet 10Base-T1 

10BASE-T1S is defined under IEEE with 802.3cg. The S in 10BASE-T1S stands for a short distance. 10BASE-T1S uses a multidrop topology, where each node connects to a single cable. Multidrop topology eliminates the need for switches and, as a result, fewer cables/less cost. The primary goal of 10BASE-T1S is a deterministic transmission on a collision-free multidrop network. 10BASE-T1S cables use a pair of twisted wires. As per IEEE, at least eight nodes can connect to each, but more connections are feasible.    

The Physical Layer Collision Avoidance [PLCA] protocol ensures that it uses the entire 10 Mbps bandwidth. In 10BaseTs, Reconciliation Sublayer provides optional Physical Layer Collision Avoidance (PLCA) capabilities among participating stations. Using PLCA-enabled Physical Layers in CSMA/CD half-duplex shared-medium networks can provide enhanced bandwidth and improved access latency under heavily loaded traffic conditions. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). 10BASE-T1S also supports an arbitration scheme that guarantees consistent node access to the media within a predefined time.  

The 10BASE-T1S PHY is intended to cover the low-speed/low-cost applications in the industrial and automotive environment. A large number of pins (16) required by the MII interface is one of the significant cost factors that must be addressed to fulfill this objective. The 10BASE-T1S "Transceiver" solution is suited for embedded systems where the digital portion of the PHY is fully integrated, e.g., into an MCU or an Ethernet switch core, leaving only the analog portion (the transceiver) into a separate IC. 

Ethernet 100Base-T1/1000Base-T1 

100Base-T1 and 1000Base-T1 can be used for audio/video information. With Higher bandwidth capacity, 100Base-T1/ 1000Base-T1 paired with AVB (Audio video bridging) can be used for car infotainment systems. 100Base-T1/1000Base-T1 paired with time-sensitive networking [TSN] protocol can be used to fulfill the automotive industry's mission-critical, time-sensitive, and deterministic latency needs. 

 PTP Over MacSec  

With today's automotive network, all the Electronic Control Units connected require timing accuracy and network synchronization, Precision Time Protocol (PTP), defined in IEEE 1588, provides synchronized clocks throughout a network.  While maintaining the timing accuracy for mission-critical applications, protecting the vehicle network from vulnerable threats is mandatory, and PTP over MacSec provides the consolidated solution.  

With the availability of the Cadence Verification IP for 10/100/1000BaseT1 and TSN, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. The 10/100/1000GBaseT1 and TSN provide a full-stack solution, including support to the PHY, MAC, and TSN layers with a comprehensive coverage model and protocol checkers. Ethernet BaseT1 and TSN VIP covers all features required for complete coverage verification closure. More details are available in the Ethernet Verification IP portfolio. 

Krunal 

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.

This year, the Cadence Giving Foundation (CGF) launched Fem.AI to achieve a more inclusive tech sector, and the inaugural Fem.AI Summit that took place on October 1 was a luminary in a world where technology is evolving at an unprecedented pace. The summit not only excelled in its mission to enlighten, empower, and mobilize stakeholders across various industries on the issue of gender disparity in high tech and AI, but was a celebration of innovation, diversity, and empowerment. As we reflect on the moments that made the summit unforgettable, it's clear that the event was more than just a meeting of minds—it was a movement for change! Shaping Tomorrow Together Cadence’s president and CEO, Anirudh Devgan, stated, “Women’s talent and perspectives are crucial to shaping the future of AI.” Devgan’s words epitomized the driving force behind the first-ever Fem.AI Summit which brought together innovators, educators, business leadership, and investors across industries to create an ecosystem that ensures women can fully participate in the AI revolution and burgeoning AI economy. The energy of pioneers ready to collectively disrupt the status quo filled the air, and as the day-long summit began, it became clear that we were part of something truly groundbreaking. The event's lineup of speakers held discussions that went beyond the technical aspects of AI, emphasizing the vital importance of diversity in technology. Such insights were lent by leading voices from MIT, Stanford, and UC Berkeley, who set the stage for inspiring discussions with speakers like Dr. Joy Buolamwini, Founder of the Algorithmic Justice League, and Reshma Saujani, Founder and CEO of Moms First and Girls Who Code. Included in this lineup of leading figures was Dr. Chelsea Clinton, Vice Chair of the Clinton Foundation, who left us with her hopes for the future of women in AI: “I’m hoping because of company-wide commitments like what we’re experiencing here today thanks to Cadence, that the people who will be part of designing [future technologies] will have a different group of people around the proverbial table or the computer screens doing that… and that women will be more integral into the conceptualization and then the actualization of AI-driven enterprises.” The hopes and visions for women in AI cannot manifest in a vacuum, they must be achieved with the support of individuals and systems from education all the way to the upper echelons of leadership. It is with this understanding, that Fem.AI is committed to investing in women at every stage of their STEM journey. Breaking Barriers It is with this ideal that we were honored to hear from women breaking through barriers of gender, race, and class in achieving pinnacles of success in areas of science and technology. Dr. Sarah H. Chen, Postdoctoral Researcher at Stanford and Thriving Stars Scholar at MIT, Niki Karanikola, Machine Learning Engineer and Break Through Tech AI Scholar at MIT, and Katya Echazarreta, NASA’s first Mexican Astronaut, showcased the resilience and determination that drive progress within and beyond our industry. Through their stories of persevering despite all odds, we were reminded that supporting students in STEM can create generational change with impacts beyond the realms of AI and technology. The final speaker at the Cadence Fem.AI Summit, the trailblazing Brandi Chastain, Founder of Bay FC, World Cup Champion, and Olympic Gold Medalist, left us with a powerful reminder that when faced with this opportunity: “Our purpose needs to be intentional” especially in building the future of technology and AI where “diversity is not something to be afraid of, but something to be embraced.” Echoing this sentiment, summit attendees left the event reminded of the crucial role we collectively play in ensuring women are part of this tech revolution. Moving Forward While the summit may have concluded, its impact will continue through individuals, companies, and communities aspiring to achieve an equitable tech sector. This is just the start, and we must take collective action now. We hope that you will join Cadence to ensure that we clear the path and catalyze women's role in the AI revolution! Meet Our Partners Our partners are making Fem.AI’s vision a reality through their important work advancing women in technology, including fostering STEM excellence in higher education, launching STEM careers, and achieving gender diversity in leadership. Learn more about the important work of each of our partners by visiting their pages: Break Through Tech Last Mile Education Fund Fast Forward Generation VC Include Global Semiconductor Alliance Join the Fem.AI Alliance Joining the Fem.AI Alliance signals that your company or institution is committed to evolving the AI workforce. By increasing the representation of women in AI, we aim to broaden the talent pool and the perspective so that AI represents us all. Through the Fem.AI Alliance, companies and institutions can share best practices, guidance, and inspiration. Since its launch, companies like the Equinix Foundation, NetApp, NVIDIA, Unity Technologies, and Workday have joined the Alliance in their commitment to Fem.AI’s work and mission. Visit Fem.AI to get involved today or contact Fem.AI@cadence.com .

On November 5, 2024, the Cadence Bangalore Toastmasters Club celebrated a significant milestone by hosting its 50th meeting. Established in December 2020, the club was created to provide a supportive environment for individuals looking to improve their communication and leadership skills. Over the years, the club has evolved into a vibrant community filled with success stories of personal development and newfound confidence. A testament to the club's dedication is its achievement of the "Select Distinguished Club" status during the 2023-2024 program year. By fulfilling 7 out of 10 distinguished goals, the club highlighted its commitment to excellence—a success driven by its vibrant members' relentless focus and perseverance. The strategic insight gained from regular Toastmasters committee meetings and the influential "Moments of Truth" sessions held in 2023 and 2024 are key to this success. Our club members have consistently demonstrated strong performance in various speech contests, with notable achievements across multiple levels. In 2023, members excelled in Evaluation and Table Topics contests, reaching the district level while advancing to the Division Level in the International Speech Contest. Continuing their success into 2024, members again qualified for area-level contests, securing third-place positions in the Evaluation and Table Topics categories, highlighting the club's dedication and competitive spirit. The 50th meeting was based on the theme of serendipity. It was not only a milestone celebration but also a vibrant festival of achievements and growth. The day buzzed with energy as activities like a spirited Treasure Hunt injected enthusiasm and camaraderie among attendees. Distinguished guests, including Kripa Venkitachalam and Madhavi Rao, enriched the occasion with inspiring speeches. Madhavi reignited the club's spirit, while Kripa's discourse on the Growth Mindset and the "Power of Yet" encouraged members to pursue continuous self-improvement. The Cadence Bangalore Toastmasters Club is enthusiastic about its promising future and is committed to creating an environment that promotes personal and professional growth. Many members are close to completing their Toastmasters levels and pathways, and this term, a new group of approximately 30 individuals has joined, bringing the total membership to 52. This vibrant community is just beginning its journey and is eager to reach new milestones together through mutual support and a shared commitment to excellence. The transformations experienced by many club members are truly compelling. They often share how the club has significantly improved their communication skills and boosted their confidence. One member recalls, "Before joining, I found public speaking intimidating. Now, I embrace every opportunity to share my ideas." Another member highlights how the club's supportive environment helped him overcome his fear of public speaking, propelling his career to new heights. This culture of constructive feedback and continuous improvement has inspired countless members to pursue their dreams with renewed determination and optimism. The Cadence Bangalore Toastmasters Club's journey is a living testament to the power of community and the potential within each of us to grow and achieve greatness. As the club continues to evolve and inspire, it serves as a beacon for those aspiring to transform their skills and seize their moment in the spotlight. Learn more about life at Cadence.

Hi, all.

When I use vavlog to compile verilog rtl, it will recognize IO width mismatch problem as a fatal error.

How to turn the error into warning?

VCS can use -error=noIOPCWM to ingore the error.

Is vavlog has similar arguments?

For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.

My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

Hi

I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell?  I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain.  I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again.  I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it.  Is there a way to "break" the features of XL like this?  I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.

Thanks

Chris

Hello all,

I have run a simulation with a lot of instnaces extraction and the psf.trn is >= 200 Gb, I tried to load it with simvision and it just breaks.

I would like to ask if there is a way to open this file, e.g. if I could read only some time window e.g. from 10us -> 15us.

getVersion(t)
"sub-version  ICADVM20.1-64b.500.34 "

XCELIUMMAIN23.03.001

thank you in advance

I just completed the setup of xcelium and I am trying to test a very simple vhdl file - I got " CSI: *F,INTERR: INTERNAL EXCEPTION" without any further explanation. Could someone point me to how to investigate this error further?

csi-xmelab - CSI: Command line: 
xmelab
-f /home/cadadmin/test/xcelium.d/run.lnx86.23.03.d/xmelab.args
-ACCESS +r
-no_analogsolver
-MESSAGES
andgate
-XLMODE ./xcelium.d/run.lnx86.23.03.d
-RUNMODE
-CDSLIB ./xcelium.d/run.lnx86.23.03.d/cds.lib
-HDLVAR ./xcelium.d/run.lnx86.23.03.d/hdl.var
-WORK worklib
-IRUNHASTOP
-CHECK_VERSION TOOL: xrun 23.03-s001
-LOG_FD 4

csi-xmelab - CSI: *F,INTERR: INTERNAL EXCEPTION
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmelab 23.03-s001
OPERATING SYSTEM: Linux 4.18.0-513.9.1.el8_9.x86_64 #1 
Elaboration of package STD.STANDARD
-----------------------------------------------------------------

csi-xmelab - CSI: Cadence Support Investigation, recording details
csi-xmelab - CSI: investigation complete took 0.000 secs, send this file to Cadence Support

Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more)

By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more)

Designing 3D-ICs with integrity involves a commitment to ethical practices, reliability, and sustainability throughout the design and manufacturing process. This includes using environmentally friendly materials, ensuring robust and efficient performance, and incorporating thorough testing and verification. By prioritizing transparency, responsibility, and long-term sustainability, designers can create advanced integrated circuits that meet high standards of quality and social responsibility.

Start Learning Now!

Start with our Designing with Integrity 3D-IC online course, which introduces Integrity 3D-IC, the industry's first comprehensive, high-capacity 3D-IC platform that integrates 3D design planning, implementation, and system analysis in a single, unified environment. You will be guided through the following activities involved in designing a silicon interposer with a digital ASIC and HBM2 interface in a 2.5D configuration.

• You will design the interposer from scratch in the new Integrity System Planner and the Integrity 3D-IC implementation environment.
• You will examine the ASIC and interposer designs using some of the new 3D-IC multi-die design features.
• You will route the interposer using some of the new advanced routing capabilities with NanoRoute

—and this in only two days!

WATCH VIDEO

Interested? Get an overview in less than two minutes.

Are you primarily interested in selected snippets instead? Then, take our Training Bytes, which—like the online training course—are available to Cadence customers for free 24/7 in the Cadence Learning and Support portal.

Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise.

To find out more, see the blog post. It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Related Resources

• 3D-IC Introduction (Video)
• 3D-IC Development Process With Challenges. (Video)
• Demo: How to Create the Interposer Contact Pads and Die Connectivity Using the Integrity 3D-IC? (Video)
• Demo: How To Pull The Interposer Design From System Planner Into Integrity 3D-IC Layout? (Video)
• Demo: Routing The Interposer Design Using The Integrity 3D-IC Layout_Part 1 (Video)
• Demo: Routing The Interposer Design Using The Integrity 3D-IC Layout_Part 2 (Video)
• Demo: How To Create C4 Bumps For NC Connections And Generating C4 Dummy Cover Bumps In Integrity 3D-IC? (Video)

Related Blogs

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The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore.

Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner.

As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power.

Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts.

Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer.

We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals.

We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them.

In addition, we’ll talk about basic debug rules and methods to analyze failures.

Sounds Interesting?

Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024!

For more details and registration, please contact Training Germany.

If you would like to have an instructor-led training session in another region please contact your local training department.

Become Cadence Certified

Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn.

Related Training

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Cerebrus Primitives (Video) 

How to Reuse Cerebrus (Video) 

Cerebrus - Verifying Distribution Script (Video)

How to distribute Cerebrus Scenarios (Video) 

Cerebrus Web Interface Monitor and Control (Video) 

How to Setup Cerebrus for a Successful Run (Video) 

Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) 

Cerebrus Cost Functions (Video) 

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