sig Data, analytics and humans: The insight equation By feedproxy.google.com Published On :: Tue, 31 Mar 2020 15:30:59 +0000 Jim Harris shows how data, analytics and humans work together to form the "insight equation." The post Data, analytics and humans: The insight equation appeared first on The Data Roundtable. Full Article Uncategorized big data data management for analytics data quality
sig DCB Bank sees significant jump in foreign remittance services on coronavirus pandemic By www.financialexpress.com Published On :: 2020-04-16T15:50:00+05:30 "Since March 15, our volumes on outward remittance services have increased many fold. There is a significant difference in before-and-after demand since mid of March," said Praveen Kutty, Head of Retail and SME Banking, DCB Bank without quantifying the increase in demand. Full Article Banking & Finance Industry
sig Coronavirus outbreak: MIT team working on an open-source, low-cost design of ventilators By www.financialexpress.com Published On :: 2020-03-29T20:10:00+05:30 COVID-19: The team, which consists of only volunteers, has been working without any funding and is working anonymously so that people do not call them with inquiries about the project. Full Article Lifestyle Science
sig Klose signs up as Bayern assistant coach By www.dailystar.com.lb Published On :: 2020-05-07T18:22:00.0000000 World Cup record scorer Miroslav Klose has signed a one-year contract to become Bayern Munich assistant coach under head coach Hansi Flick from next season, the Bundesliga champions said Thursday. Full Article Football
sig CANTILEVER AND OVERHEAD SIGN STRUCTURES, I-95 By www.deldot.gov Published On :: Wed, 20 Nov 2019 05:00:00 GMT CANTILEVER AND OVERHEAD SIGN STRUCTURES, I-95 Full Article
sig SR 1, TYBOUTS CORNER LEFT EXIT SIGNING By www.deldot.gov Published On :: Tue, 03 Dec 2019 05:00:00 GMT SR 1, TYBOUTS CORNER LEFT EXIT SIGNING Full Article
sig All You Need To Know About Imran Hussain, Delhi's Minister Designate By www.ndtv.com Published On :: Sat, 15 Feb 2020 23:21:35 +0530 Imran Hussain, the Ballimaran MLA, has been retained as a Cabinet minister in the Arvind Kejriwal government. He will take oath of office on Sunday along with his five Cabinet colleagues and Arvind... Full Article People
sig RBI to issue Rs 1,000 banknotes with new design By www.banknetindia.com Published On :: RBI to issue banknotes of Rs 1,000 Denomination with new design Full Article
sig Film Funding Network launched by Six Sigma Films By www.filmfundingnetwork.com Published On :: India's Biggest Film Funding Platform, Film Funding Network directly connects a global network of investors, HNIs with filmmakers for funding movies, short films, TV shows. Full Article
sig TV Star Anushka Sen First Short Film On Six Sigma Films Channel By youtu.be Published On :: TV Star Anushka Sen Short Film 'Sammaditthi' Is Trending On YouTube Full Article
sig Best Indian Short Films - Six Sigma Films By www.youtube.com Published On :: Best Indian Short Films - Six Sigma Films Full Article
sig Customer Insight Inspires Innovation and Growth By stagecorp.ztsaccess.com Published On :: Thu, 30 Jul 2015 00:00:00 +0000 Dr. Catherine Knupp, executive vice president and president of Research and Development at Zoetis, shares her insights on the value of innovation to both animal and human health. Full Article
sig Trump Says He’s ‘Torn’ on China Deal as Advisers Signal Harmony on Trade By www.nytimes.com Published On :: Fri, 08 May 2020 10:50:07 GMT The president’s comments, coming just hours after advisers said the agreement was on track, indicate an increasingly unstable relationship. Full Article
sig Ducks re-sign Djoos, Hakanpää to 1-year deals By www.espn.com Published On :: Wed, 6 May 2020 19:19:39 EST The Anaheim Ducks have re-signed defensemen Christian Djoos and Jani Hakanpaa to one-year contracts, the team announced Wednesday. Full Article
sig Panthers DT Brown first 1st-rounder to sign deal By www.espn.com Published On :: Fri, 8 May 2020 18:06:54 EST Former Auburn defensive tackle Derrick Brown became the first player chosen in the NFL draft's first round to agree on a deal. The Panthers will sign him to a four-year, fully guaranteed contract worth $23.62 million. Full Article
sig How to Verify Performance of Complex Interconnect-Based Designs? By feedproxy.google.com Published On :: Sun, 14 Jul 2019 15:43:00 GMT With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions: While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases? To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels: Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth. Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager Metric-Driven Signoff Platform. To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system. With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure. For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage. Thierry Full Article Verification IP Interconnect Workbench Interconnect Validator SoC Performance modeling AMBA ATP ARM System Verification
sig Dimensions to Verifying a USB4 Design By feedproxy.google.com Published On :: Sun, 08 Sep 2019 19:53:00 GMT Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled through a USB4 fabric, and converted back into the respective original native protocol traffic. It may sound simple but is perhaps not. There are several aspects in a router that come into picture to carry out this task of conversion of native protocol traffic, route it to the intended destination, and then convert it back to the original form. Some of those are the USB3, DP and PCIe protocol adapters, transport mechanism using routing, flow control, paths, path set-up and teardown, control and configuration, configuration spaces. That is not all. There are core USB4 specific logical layer intricacies as well, which carry out the tasks of ensuring that all the USB4 ports and links are working as desired to provide up to 40Gbps speed and that the USB4 traffic flows through out the fabric in the intended way. These bring on the table features like High Speed link, ordered sets, lane initialization, lane adapter state machine, low power, lane bonding, RS-FEC, side band channel, sleep and wake, error checking. All of these put together give rise to a very large verification space against which a USB4 router design should be verified. If we were to break down this space it can be broadly put in the following major dimensions, Protocol Adapter Layer USB3 tunneling DP tunneling PCIe tunneling Host Interface Adapter Layer Transport Layer Flow control Routing Paths Configuration layer and control packet protocol Configuration spaces Logical Layer The independent verification of these dimensions is not all that would qualify the design as verified. They have to be verified in various combinations of each other too. Overall, all the parts of a USB4 router system need to be working together coherently. For example, the following diagram depicts the various layers that a USB4 router may comprise of, A USB4 router or a domain of routers does not work on its own. There is a Connection Manager per domain, which is a software-based entity managing a domain. A router provides the various capabilities for a Connection Manager to carry out its responsibilities of managing a domain. It would not be an exaggeration to say that the spectrum of verification of a USB4 router ranges from the very minute details of logical layer to the system-level like multiple dependencies as the whole USB4 system is brought up layer by layer, step-by-step. Cadence has a mature Verification IP solution that can help in the verification of USB4 designs. Cadence has taken an active part in the working group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members in the last two years. If you plan to have a USB4 compatible design, you can reduce the risk of adopting a new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team for more details and to get connected. Full Article Verification IP Router DisplayPort USB usb4 PCIe USB3 tunneling
sig PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offering By feedproxy.google.com Published On :: Tue, 29 Oct 2019 09:26:00 GMT PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May. A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 (only in Taipei), several member companies shared their view on Testing, PCB analysis and Signal integrity. The exhibit is also another spotlight of this event where the member companies showcased their latest PCIe solutions. Presentation Track (Taipei), Exhibit (Tokyo), Exhibit (Taipei) Cadence, as the market leading PCIe IP vendor, participated APAC tour this year with bringing in its latest PCIe IP solution offering (Gen 5/4) to the region as well as showcasing two live demo setups in the exhibit floor. One setup is the PCIe software development kit (SDK) while the other is the Interop/compliance/debug platform. Both come with the Cadence PCIe Gen 4 hardware setup and its corresponding software kit. The SDK can be used for Device Driver Development, Firmware Development, and for pre-silicon emulation as well. It supports Xtensa and ARM processor with Linux OS and it also equip with Ethernet interface which can be used for remote debugging. It also supports PCIe stress tests for Speed change, link enable/disable, entry/exist for lower power states, …etc. Cadence PCIe 4.0 Software Development Kit The “System Interop/Compliance/Debug platform” was set up to test with multiple endpoint and System platforms. This system come with integrated Cadence software for basic system debug without the need for analyzer to perform the analysis, such as LTSSM History, TS1/TS2 transmitted/received with time stamp, Link training phases, Capturing Packet errors details, Capturing PHY TX/RX internal state machine details, ...etc. Cadence PCIe System Interop/Compliance/Debug Platform The year 2019 is certainly a "fruitful year" for the PCIe as more Gen 4 products are now available in the market, Gen 5 v1.0 specification got officially ratified, and PCI-SIG's revealing of Gen 6 specification development. We were glad to be part of this APAC tour with the chance to further introduce Cadence’s complete and comprehensive PCIe IP solution. See you all next year in APAC again! More Information For more information on Cadence's PCIe IP offerings, see our PCI Express page. For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website. Related Posts Blog: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product Blog: PCIe Gen4: It’s Official, We’re Compliant Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016 Full Article PCI Developers Conference Design IP PCIe Gen4 PCIe Gen3 PCIe PHY PCIe Gen5 PCI Express PCI-SIG
sig Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple By feedproxy.google.com Published On :: Mon, 10 Feb 2020 15:19:00 GMT Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality. The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed for a transition. Until conditions for both are satisfied an adapter cannot transition to the next training sub-state. As deduced from the lane adapter state machine section of USB4 specification, the reception condition for the next training sub-state transition is less strict than that of the transmission condition. For ex., for LOCK1 to LOCK2 transition, the reception condition requires only two SLOS symbols in a row being detected, while the transmission condition requires at least four complete SLOS1 ordered sets to be sent. From the above conditions in the specification, it is a possibility that a lane adapter A may detect the two SLOS or TS ordered sets, being sent by the lane adapter B on the other end, in the very beginning as soon as it starts transmitting its own SLOS or TS ordered sets. On the other hand, it is also a possibility that these SLOS or TS ordered sets are not yet detected by lane adapter A even when it has met the condition of sending minimum number of SLOS or TS ordered sets. In such a case, lane adapter A, even though it has satisfied the transmission condition cannot transition to the next sub-state because the reception condition is not yet met. Hence lane adapter A must first wait for the required number of ordered sets to be detected by it before it can go to the next sub-state. But this wait cannot be endless as there are timeouts defined in the specification, after which the training process may be re-attempted. This interlocked way of operation also ensures that state machine of a lane adapter does not go out of sync with that of the other lane adapter. Such type of scenarios can occur whenever lane adapter state machine transitions to the training state from other states. Cadence has a mature Verification IP solution for the verification of various aspects of the logical layer of a USB4 router design, with verification capabilities provided to do a comprehensive verification of it. Full Article Verification IP DP VIP DisplayPort PCIExpress USB Lane Adapter usb4 PCIe usb4 router tunneling
sig DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design By feedproxy.google.com Published On :: Wed, 10 Jun 2015 15:36:20 GMT There has been so much hype about the “Internet of Things” (IoT) that it is refreshing to hear about a cutting-edge development project that can bring concrete benefits to millions of people. That project is the ongoing development of the Google Smart Contact Lens, and it was detailed in a keynote speech June 8 at the Design Automation Conference (DAC 2015). The keynote speech was given by Brian Otis (right), a director at Google and a research associate professor at the University of Washington. The “smart lens” that the project envisions is essentially a disposable contact lens that fits on an eye and continuously monitors blood glucose levels. This is valuable information for anyone who has, or may someday have, diabetes. Since he was speaking to an engineering audience, Otis focused on the challenges behind building such a device, and described some of the strategies taken by Google and its partner, Novartis. The project required new approaches to miniaturization, low-power design, and connectivity, as well as a comfortable and reliable silicon-to-human interface. Otis discussed the “why” as well and showed how the device could potentially save or improve millions of lives. Millions of Users First, a bit of background. Google announced the smart lens project in a blog post in January 2014. Since then it has been featured in news outlets including Forbes, Time, and the Wall Street Journal. In March 2015, Time reported that Google has been granted a patent for a smart contact lens. The smart lens monitors the level of blood glucose by looking at its concentration in tears. The lens includes a wireless system on chip (SoC) and a miniaturized glucose sensor. A tiny pinhole in the lens allows tear fluid to seep into the sensor, and a wireless antenna handles communications to the wireless devices. “We figure that if we can solve a huge problem, it is probably worth doing,” Otis said. “Diabetes is one example.” He noted 382 million people worldwide have diabetes today, and that 35% of the U.S. population may be pre-diabetic. Today, diabetics must *** their fingers to test blood glucose levels, a procedure that is invasive, painful, and subject to infrequent monitoring. According to Otis, the smart contact lens represents a “new category of wearable devices that are comfortable, inexpensive, and empowering.” The lens does sensor data logging and uses a portable instrument to measure glucose levels. It is thin, cheap, and disposable, he said. Moreover, the lens is not just for people already diagnosed with diabetes—it’s for anyone who is pre-diabetic, or may be at risk due to genetic predisposition. “If we are pro-active rather than re-active,” Otis said, “Instead of waiting until a person has full-fledged diabetes, we could make a huge difference in peoples’ lives and lower the costs of treating them.” Technical Challenges No one has built anything quite like the smart lens, so researchers at Google and Novartis are treading new ground. Otis identified three key challenges: Miniaturization: Everything must be really small—the SoC, the passive components, the power supply. Components must be flexible and cheap, and support thin-film integration. Platform: Google has developed a reusable platform that includes tiny, always-on wireless sensors, ultra low-power components, and standards-based interfaces. Data: Researchers are looking for the best ways to get the resulting data into a mobile device and onto the cloud. Comfort is another concern. “This is not intended to be for the most severe cases,” Otis said. “This is intended to be for all of us as a pro-active way of improving our lifestyles.” The platform provides a bidirectional encrypted wireless link, integrated power management, on-chip memory, standards-based RFID link, flexible sensor interface, high-resolution potentiostat sensor, and decoupling capacitors. Most of these capabilities are provided by the standard CMOS SoC, which is a couple hundred microns on a side and only “tens of microns” thick. Otis noted that unpackaged ICs are typically 250 microns thick when they come back from the foundry. Thus, post-processing is needed so the IC will fit into a contact lens. Furthermore, the design requires precision analog circuitry and additional environmental sensors. “Some of this stuff sounds mundane but it is really hard, especially when you find out you can’t throw large decoupling capacitors and bypass capacitors onto a board, and all that has to be re-integrated into the chip,” Otis said. Sensor Challenges Getting information from the human body is challenging. The smart lens sensor does a direct chemical measurement on the surface of the eye. The sensor is designed to work with very low glucose concentrations. This is because the concentration of glucose in tears is an order of magnitude lower than it is in blood. In brief, the sensor has two parallel plates that are coated with an enzyme that converts glucose into hydrogen peroxide, which flows around the electrodes of the sensor. This is actually a fairly standard way of doing glucose monitoring. However, the smart lens sensor has two electrodes compared to the typical three. In manufacturing, it is essential to keep costs low. Otis outlined a three-step manufacturing process: Start with the bottom layer, and mold a contact lens in the way you typically would. Add the electronics package on top of that layer. Build a second layer that encapsulates the electronics and provides the curvature needed for comfort and vision correction. Beyond the technical challenges are the “clinical” challenges of working with human beings. The human body “is messy and very variable,” Otis said. This variability affects sensor performance and calibration, RF/electro-magnetic performance, system reliability, and comfort. The final step is making use of the data. “We need to get the data from the device into a phone, and then display it so users can visualize the data,” Otis said. This provides “actionable feedback” to the person who needs it. Eventually, the data will need to be stored in the cloud. As he concluded his talk, Otis noted that the platform his group developed may have many applications beyond glucose monitoring. “There is a lot you can do with a bunch of logic and sensing capability,” he said, “and there are hundreds of biomarkers beyond glucose.” Clearly this will be an interesting technology to watch. Richard Goering Related Blog Post - Gary Smith at DAC 2015: How EDA Can Expand Into New Directions Full Article Smart Contact Lens DAC Industry Insights IoT google Otis glucose monitoring DAC 2015 diabetes Google Smart Lens
sig About modus design constraints By feedproxy.google.com Published On :: Fri, 13 Mar 2020 12:09:02 GMT Hi! In my design, there is an one hold violation on scan path, test data is corrupted during scan cycles (when i run verilog simulation of test vectors). I created constraint 'falsepath' to 'TI' input of violated flop and load it into Modus, but this does not have effect. Can enyone explain to me, does 'falsepath' constraint affects scan path (from Q to TI/SI input, i.e. during SCAN procedure) or this constraint is only for functional mode (ie affects TEST cycle only - to 'D' input)? I hope resolve this problem this by using some modus design constraints or any other method. Full Article
sig stretching LOW pulse signal for extra 100ns By feedproxy.google.com Published On :: Tue, 18 Jun 2019 12:02:54 GMT Hello, i have a logic output from a D-flipflop which generates a reset signal with variable pulse width. I want to stretch this LOW pulse width with an extra 100ns added to the original pulse width digitally, is there any way to do that? Full Article
sig How to customize default_hdl_checks/rules in CCD conformal constraint designer By feedproxy.google.com Published On :: Tue, 03 Sep 2019 08:12:48 GMT Dear all, I am using Conformal Constraint Designer (Version 17.1) to analyse a SystemVerilog based design. While performing default HDL checks it finds some violations (issues) in RTL and complains (warnings, etc) about RTL checks and others. My questions: Is there any directive which I can add to RTL (system Verilog) so that particular line of code or signal is ignored or not checked for HDL or RTL checks. I can set ignore rules in rule manager (gui) but it does not seems effective if code line number changes or new signals are introduced. What is the best way to customize default_hdl_rules ? I will be grateful for your guidance. Thanks for your time. Full Article
sig SystemVerilog package used inside VHDL-2008 design? By feedproxy.google.com Published On :: Thu, 17 Oct 2019 15:46:22 GMT Hi, Is it possible to use a SystemVerilog package which is compiled into a library and then use it in a VHDL-2008 design file? Is such mixed-language flow supported? I'm considering the latest versions of Incisive / Xcelium available today (Oct 2019). Thank you, Michal Full Article
sig How to Set Up and Plot Large-Signal S Parameters? By feedproxy.google.com Published On :: Mon, 04 Dec 2017 09:23:00 GMT Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and are defined as the ratio of reflected (or transmitted) waves to incident waves. (read more) Full Article RF Simulation Spectre RF Virtuoso ADE Virtuoso
sig DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More By feedproxy.google.com Published On :: Wed, 29 May 2019 23:45:00 GMT Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more) Full Article security 5G DAC DAC2019 prototyping palladium z1 Safety tortuga logic Protium Emulation ARM AI
sig SIP to Allegro pcb designer 17.2 ver By feedproxy.google.com Published On :: Tue, 28 Jan 2020 13:25:18 GMT Iam new to Package design SIP tool. I had created the DIE package using SIP. Kindly give the direction how to map the created DIE package in Allegro pcb editor 17.2 ver. In Allegro design capture CIS tool we had created the schematics file. The DIE which we are using is having 100pins, We had created the DIE in SIP tool. Out of 100 Die pins, only 90 pins is getting connected others are NC pins. We had mapped the Bond fingers only for 90 Die pins in the SIP package. But in the Schematics we had created the DIE logic symbol for 100 pins. Please advice whether we can able to import the DIE package in the allegro tool. In this scenario while importing the 100 pin DIE package in allegro pcb editor will the net connectivity will be shown from the DIE pad to Bond fingers and from Bond fingers to respective components? Please suggest whether we are going in the right path or please advice what we have to proceed with. Thanks in Advance, Rajesh Full Article
sig BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly By community.cadence.com Published On :: Tue, 28 Apr 2020 13:12:00 GMT Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig My Journey - From a Layout Designer to an Application Engineer By community.cadence.com Published On :: Wed, 29 Apr 2020 14:41:00 GMT Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis By community.cadence.com Published On :: Wed, 29 Apr 2020 15:00:00 GMT In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution.... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig 2019 HF1 Release for Clarity, Celsius, and Sigrity Tools Now Available By community.cadence.com Published On :: Fri, 01 May 2020 21:20:00 GMT The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig Signoff in the Cloud By community.cadence.com Published On :: Mon, 04 May 2020 12:00:00 GMT Here's a nightmare. You sign off your design with the usual margins. It is a 7nm chip that is meant to run at 3GHz. But it only runs at 2.7GHz. You get Cadence to help you work out what is going... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig IC Packagers: Advanced In-Design Symbol Editing By community.cadence.com Published On :: Wed, 06 May 2020 14:09:00 GMT We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro® Package Designer Plus layout tools allowing you to work... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig BoardSurfers: Training Insights: Placing Parts Manually Using Design for Assembly (DFA) Rules By community.cadence.com Published On :: Fri, 08 May 2020 14:41:00 GMT If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
sig Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Think By feedproxy.google.com Published On :: Wed, 24 Jul 2019 21:13:00 GMT Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019. What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”. Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it. SaaS companies like Workday and Salesforce deliver their value in this manner. The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest. Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides. All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud. Wait—actually, they are. Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space. The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one. Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one. Cloud computing is the future of EDA. See the future here. Full Article DAC 2019 Semiconductor cadence cloud
sig BoardSurfers: Training Insights: Creating Custom Reports using ‘Extract’ By feedproxy.google.com Published On :: Wed, 11 Mar 2020 16:45:00 GMT You must deal with many reports in your daily life – for your health, financial accounts, credit, your child’s academic records, and the count goes on. Ever noticed that these reports contain many details, most of which you don’t wa...(read more) Full Article Allegro PCB Editor
sig BoardSurfers: Allegro In-Design IR Drop Analysis: Essential for Optimal Power Delivery Design By feedproxy.google.com Published On :: Wed, 01 Apr 2020 15:12:00 GMT All PCB designers know the importance of proper power delivery for successful board design. Integrated circuits need the power to turn on, and ICs with marginal power delivery will not operate reliably. Since power planes can...(read more) Full Article PCB PI PCB design power
sig BoardSurfers: Training Insights: Loading SKILL Programs Automatically By feedproxy.google.com Published On :: Tue, 07 Apr 2020 14:51:00 GMT Imagine you are on a vacation with your family, and suddenly, your phone starts buzzing. You pick it up and what are you looking at is a bunch of pending, unanswered e-mails. You start recollecting the checklist you had made before taking off only to realize that you haven’t put on the automatic replies! (read more) Full Article Cadence SKILL Allegro PCB Editor Allegro Skill
sig BoardSurfers: Training Insights - Fundamentals of PDN for Design and PCB Layout By feedproxy.google.com Published On :: Wed, 22 Apr 2020 02:31:00 GMT What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more) Full Article power integrity Sigrity Allegro PCB Editor PowerDC
sig BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly By feedproxy.google.com Published On :: Tue, 28 Apr 2020 13:12:00 GMT Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more) Full Article PCB design Sigrity Allegro
sig BoardSurfers: Training Insights: Placing Parts Manually Using Design for Assembly (DFA) Rules By feedproxy.google.com Published On :: Fri, 08 May 2020 14:41:00 GMT So, what if you can figure out all that can go wrong when your product is being assembled early on? Not guess but know and correct at an early stage – not wait for the fabricator or manufacturer to send you a long report of what needs to change. That’s why Design for Assembly (DFA) rules(read more) Full Article Allegro PCB Editor
sig New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification By feedproxy.google.com Published On :: Mon, 10 Dec 2012 13:32:00 GMT All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check. The power structure integrity of a mixed-signal, low-power block is verified via Conformal Low Power integrated into the Virtuoso Schematic Editor Power Intent Export Assistant (VSE-PIEA). Here is the flow. Applying the flow iteratively from lower to higher levels can verify the power structure. Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: Mixed-Signal Low Power Structural Verification. To read the overview presentation, click on following link: PIEA Overview To download this PIEA RAK click on following link: PIEA RAK Download The RAK includes Rapid Adoption Kit with demo design (instructions are provided on how to setup the user environment). It Introduces the Power Intent Export Assistant (PIEA) feature that has been implemented in the Virtuoso IC615 release. The power intent extracted is then verified by calling Conformal Low Power (CLP) inside the Virtuoso environment. Last Update: 11/15/2012. Validated with IC 6.1.5 and CLP 11.1 The RAK uses a sample test case to go through PIEA + CLP flow as follows: Setup for PIEA Perform power intent extraction CPF Import: It is recommended to Import macro CPF, as oppose to designing CPF for sub-blocks. If you choose to import design CPF files please make sure the design CPF file has power domain information for all the top level boundary ports Generate macro CPF and design CPF Perform low power verification by running CLP It is also recommended to go through older RAKs as prerequisites. Conformal Low Power, RTL Compiler and Incisive: Low Power Verification for Beginners Conformal Low Power: CPF Macro Models Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users To access all these RAKs, visit our RAK Home Page to access Synthesis, Test and Verification flow Note: To access above docs, use your Cadence credentials to logon to the Cadence Online Support (COS) web site. Cadence Online Support website https://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you can receive new solutions, Application Notes (Technical Papers), Videos, Manuals, and more. You can send us your feedback by adding a comment below or using the feedback box on Cadence Online Support. Sumeet Aggarwal Full Article COS conformal VSE Virtuoso Schematic Editor Low Power clp Conformal Low Power Cadence Online Support Mixed Signal Verification mixed-signal low-power Mixed-Signal Virtuoso Power Intent Export Assistant PIEA mixed signal design CPF CPF Macro Modelling Digital Front-End Design
sig Mixed-signal and Low-power Demo -- Cadence Booth at DAC By feedproxy.google.com Published On :: Fri, 31 May 2013 18:11:00 GMT DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921. For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for: The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week! A sneak preview of the eBook version of the Mixed-signal Methodology Guide Customer presentations at the Cadence DAC Theater 9am, Tuesday, June 4 ARM Low-Power Verification of A15 Hard Macro Using CLP 10:30am, Tuesday, June 4 Silicon Labs Power Mode Verification in Mixed-Signal Chip 12:00pm, Tuesday, June 4 IBM An Interoperable Flow with Unified OA and QRC Technology Files 9am, Wednesday, June 5 Marvell Low-Power Verification Using CLP 4pm, Wednesday, June 5 Texas Instruments An Inter-Operable Flow with Unified OA and QRC Technology Files Partner presentations at the Cadence DAC Theater 10am, Monday, June 3 X-Fab Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit 3:30pm, Monday, June 3 TSMC TSMC Custom Reference Flow for 20nm - Cadence Track 9:30am,Tuesday, June 4 TowerJazz Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow 12:30pm, Wednesday, June 5 GLOBALFOUNDRIES 20nm/14nm Analog/Mixed-signal Flow 2:30pm, Wednesday, June 5 ARM Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications Technology sessions at suites 10am, Monday, June 3 Low-power Verification of Mixed-signal Designs 2pm, Monday, June 3 Advanced Implementation Techniques for Mixed-signal Designs 2pm, Monday, June 3 LP Simulation: Are You Really Done? 4pm, Monday, June 3 Power Format Update: Latest on CPF and IEEE 1801 11am, Wednesday, June 5 Mixed-signal Verification 11am, Wednesday, June 5 LP Simulation: Are You Really Done? 4pm, Wednesday, June 5 Successful RTL-to-GDSII Low-Power Design (FULL) 5pm, Wednesday, June 5 Custom/AMS Design at Advanced Nodes We will also have three presentations at the Si2 booth (#1427): 10:30am, Monday, June 3 An Interoperable Implementation Solution for Mixed-signal Design 11:30am, Tuesday, June 4 Low-power Verification for Mixed-signal Designs Using CPF 10:30am, Wednesday, June 5 System-level Low-power Verification Using Palladium We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC! Full Article DAC Low Power microcontrollers IBM Palladium Mixed Signal Verification Incisive mixed-signal low-power encounter Low Power Mixed Signal Verification Virtuoso Internet of Things low-power design mixed signal GlobalFoundries ARM Design Automation Conference microcontroller
sig Transimpedance amplifier design Cadence By feedproxy.google.com Published On :: Thu, 27 Feb 2020 00:13:46 GMT Hi, I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response. First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated. Thanks, -Rakesh. Full Article
sig Design library not defined while reading module with ncsim By feedproxy.google.com Published On :: Fri, 25 Oct 2019 08:27:37 GMT Hi supporters, I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20): ---- ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.ncsim: *E,DLOALB: Design library 'tcbnxxx' not defined while reading module tcbnxxx.MAOxxx:bv (VST).ncsim: *F,NOSIMU: Errors initializing simulation 'alu_tb' ---- xxx: standard library name. My netlist design uses a cell "MAOxxx". I already included the library behavior model to compile using ncverilog, there is no error while compiling. But when I run with ncsim to execute the test, I got above error. I tried to run with other vendors such as VCS or MTI, they worked. Please help to understand the error. Thanks. Full Article
sig Design of DC motor model By feedproxy.google.com Published On :: Tue, 21 Jan 2020 07:32:56 GMT Hi I want develope basic circuit of DC motor which consist of resistor, inductor and back emf in capture and check its simulation in pspice, for reference I have attached image and link. https://www.precisionmicrodrives.com/content/ab-025-using-spice-to-model-dc-motors/ . Full Article
sig IC Packagers: Five Steps to IC-Driven Package Design By feedproxy.google.com Published On :: Thu, 05 Mar 2020 17:23:00 GMT They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now. The net result of this run? Well, you can't design ICs in isolation from the...(read more) Full Article Allegro Package Designer
sig IC Packagers: Design Element Label Management By feedproxy.google.com Published On :: Wed, 18 Mar 2020 13:46:00 GMT A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...(read more) Full Article Allegro Package Designer Allegro PCB Editor
sig IC Packagers: Advanced In-Design Symbol Editing By feedproxy.google.com Published On :: Wed, 06 May 2020 14:09:00 GMT We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...(read more) Full Article Allegro Package Designer
sig Multiple parts for single reference designator By feedproxy.google.com Published On :: Tue, 28 Apr 2020 15:34:37 GMT Variants seem to be defined as present or not present. Is there a variant that can assign different parts to the same reference designator? i.e. R17 can be either 0 ohm 0805 jumper or 12k ohms 0805 resistor. The simplest way I can think of is to use two parts with the same footprint and overlay them. Is there a more functional way of doing this? So that the variant would put the correct part in the BOM and the parts would of course have the same identical footprint. Full Article