The American Cancer Society National Lung Cancer Roundtable (ACS NLCRT), American College of Radiology® (ACR®), Radiology Health Equity Coalition (RHEC), and GO2 for Lung Cancer (GO2) have partnered once again for the second annual National Lung Cancer Screening Day (“National LCS Day”) on Saturday, November 9, 2024, which has been officially proclaimed by Governor John […]

Read the in depth Review of Sony Ericsson Vivaz Pro: Loses 8MP camera, gets a keyboard - at Rs. 24,585 Mobile Phones. Know detailed info about Sony Ericsson Vivaz Pro: Loses 8MP camera, gets a keyboard - at Rs. 24,585 configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

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Read the in depth Review of Samsung 50-inch The Frame QLED 4K Smart TV (2021) TV. Know detailed info about Samsung 50-inch The Frame QLED 4K Smart TV (2021) configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of FUJIFILM FinePix Real 3D W1 - world's first 3D camera - price Rs. 39,999 Digital Cameras. Know detailed info about FUJIFILM FinePix Real 3D W1 - world's first 3D camera - price Rs. 39,999 configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

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1. Best smartphones under ₹30,000 with good battery life and cameras | Mint  Mint
2. Best smartphones under 20,000 with good cameras: Redmi Note 13 Pro, Vivo T3 5G and others  Hindustan Times
3. 5 Affordable Camera Phones To Make Instagram Reels  Times Now
4. Best Smartphones Under Rs 20,000 With Excellent Cameras, Redmi Note 13 Pro, Vivo T3 5G & More  NewsX

1. 26 die as bus plunges into Indus in Diamer  DAWN.com
2. 14 Dead As Bus With Wedding Guests Falls Into River In Pak, Bride Survives  NDTV
3. A bus carrying wedding guests falls into a river in northern Pakistan, killing 18  The Times of India
4. Tragic Gilgit-Baltistan Bus Accident Claims 26 Lives During Wedding Journey  Oneindia
5. 14 Drown, 12 Missing In Pakistan After Bus Plunges Into River In PoK's Gilgit-Baltistan  News18

Shared by Gator Boys star Paul Bedard, the viral video shows the alligator emerging from his den to the tune of the iconic song.

[COSATU] The Congress of South African Trade Unions (COSATU) is deeply concerned by the Minister for Communications and Digital Technologies, Mr. S. Malatsi's sudden withdrawal of the South African Broadcasting Corporation (SABC) SOC Ltd Bill from Parliament where it was being engaged upon by the National Assembly's Portfolio Committee: Communications and Digital Technologies.

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

I'm trying to write a generic piece of code that will return the layermap file location, with file name, for a variety of projects (which could potential have different layermap file naming conventions. The below code is what I've used to date, but this assumes the file name is xxxx.layermap. I can obviously do some string matching to find it, assuming the various files all contain some common characters. I thought I'd ask if there is a simpler way to find it, I know that this information is automatically loaded into the Xstream out gui, so maybe I can use the same approach to find it.

techLibName=techGetTechFile(cv)~>libName

techLibLayerMap=strcat(ddGetObj(techLibName)~>readPath "/" techLibName ".layermap")

Hi everyone. 

I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence skills.

I have some digital decision logic. Some are combinational logic, some are sequential logic that I would like to import or generate random input combination to the inputs of my decision logic to get the maximum, minimum, and average delay power dissipation and area when feeding the different input combination.

My logic has 8-bit, 16-bit, and 32-bit input. The imported data tends to be decimal numbers.

I would like to ask you:

- which tool(s) are the most appropriate to import and feed the different combination to my decision logic?

- which tool is the most appropriate to synthesis with different number of input? - I have used Genus Synthesis Solution so far. However with my skill right now I can only let Genus synthesize my Verilog code one setup at a time. I'm not sure if I there is anyway I can feed a lot of input at a time and get those results (min, max, average of delay, power dissipation and area)

- which language or scripts I should pick up to use and achieve these results?

-where can I find information to solve my problem? which information shall I look for?

Thank you so much for your time!!

Best Regards

Hi Cadence, 

I use simvision 20.09-s007 but my computer screen resolution is very high. As a result, the texts are too small. 

In ~/.simvision/Xdefaults I changed that number to 16, from 12. But the signal names in the waveform traces don't reflect the change. 

Simvision*Font: -adobe-helvetica-medium-r-normal--16-*-*-*-*-*-*-*

Other .font changes seem to reflect on the simvision correctly, except the signal names. 

How do I fix that? I dont mind a single variable to change all the texts fonts to 16. 

Thank you!

PS: I found the answer with another post. I change Preference/Waveform/Display/Signal Height. 

Hi everyone, 

Is there any method to generate "Sheet" column for a pin report like table below? The column "Name.Pin" & "Signal" can be generated easily, but I have no idea to generate the column of "Sheet Name".

The software using here are Allegro Design Entry HDL, OrCAD Capture and Allegro PCB Editor. Can these 3 software generate "Sheet Name" data?

Thank you. 

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more)

The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those who want to use formal analysis for design or verification. 

To optimally benefit from this course, you must already have sufficient knowledge of the System Verilog assertions to be capable of writing properties for formal verification. Hence, this training provides a module on formal analysis to help cover this essential background. 

In this course, you will learn how to code efficient SVA Properties for formal analysis, understand formal complexity and how to overcome it, and learn the basics of formal coverage.

After completing this course, you will be able to:

• Define reusable, functionally correct SVA properties that are efficient for formal tools. These shall use abstract auxiliary code to simplify descriptions, make code maintenance easier, reduce debug time, and reduce tool-proof runtime.
• Set up, run, and analyze results from formal analysis.
• Identify designs upon which formal is likely to be successful while understanding formal complexity issues and how to identify and overcome them.
• Use a systematic property development process to approach a completely new verification problem.
• Understand the basics of formal coverage.

 The most recently updated release includes new modules on:

• "Basic complexity handling" which discusses the complexity in formal and how to identify and handle them.
• "Complexity reduction methods” which discusses the complexity reduction methods and which is suitable for which type of complexity problem.
• “Coverage in formal” which discusses the basics of coverage in formal verification and how coverage can be used in formal.   

Take this course to learn the basics of formal verification. 

What's Next? 

You can check out the complete training: Jasper Formal Fundamentals. There is a free online version of the training available 24/7 for all customers with a Cadence Learning and Support Portal account. If you are interested in an instructor-led version of the training, please contact Cadence Training. And don't forget to obtain your digital badge after completing the training!

You can also check Jasper University page for more materials on formal analysis and Jasper apps. 

Related Trainings 

Jasper Formal Expert Training Course | Cadence

Verilog Language and Application Training Course | Cadence

SystemVerilog for Design and Verification Training Course | Cadence

SystemVerilog Assertions Training Course | Cadence

Related Training Bytes 

Jasper Formal Property Verification (FPV) App: Basic Usage Demo (Video)

Jasper Formal Methodology playlist

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This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Read on to know about the Operating Point Parameters Summary window that gives you a one-stop view of the categorized and tabulated details on all operating point parameters in your design. This window improves your review cycle with its many benefits.(read more)

This blog describes an efficient way to name the histories saved by the simulation runs in Virtuoso ADE Assembler.(read more)

Dear all,

I defined two design variables in ADE Assembler, say V1 and V2, that define the voltage 1 and voltage 2 of a "vpulse" voltage source in my schematic.

Then, I define V1 = 1.0, and V2 = 2.0, run a transient simulation, and everything is as expexcted. The source provides pulses between 1.0 V and 2.0 V.

Next, I set V1 = 1.0:0.5:1.5, thereby creating a parametric sweep with 1.0 V and 1.5 V for V1. I keep V2 at 2.0 V. Then the simulation fails, and all I get is "netl err" in my Output Expressions and an error message that the results directory does not exist and nothing can be plotted: This is reasonable, as the results directory is deleted on starting a new simulation, and as there is no simulation result, none of my output expressions can be plotted.

WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
        Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
WARNING (ADE-1065): No simulation results are available.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.

Normally, this kind of para,metric sweep is not a problem, I have done this many times before. There must be something special in THIS PARTICULAR test bench or simulator setup. The trouble is, I don't get any useful error messages.

Does anyone know what might be the problem here OR where to find useful information to investigate further (log files stored somewhere)? Thank you!

Regards,

Volker

P.S. Using Corners instead does not help either. Running it through all values by hand works, though.

How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?

Dear community

We would like to have more minimalistic and customized sheet borders for our schematics. I used this guide to create a starting point. Essentially, I made a copy of the US_8ths library and modified the Title symbol to look something like that:

Problem 1

The variable ilInst~>libName points to the library of the sheet border symbols, not to the library of the schematic. How do I need to modify this field in order to see the library name of the schematic where the border is instantiated?

Problem 2

The function CCSgetCreator() was taken from here. This solution does not seem to work with our management toll (we use VersIC); the function always returns nil as value. What is the simplest way to display the name of the user that created the schematic? A custom field that could be filled manually would also do the job for us; it doesn't need to be something that automatically fetches data from a database system.

Thanks for any input.

Hi,
I want to parameterized width and length of a NMOS, but it ignore it and I face this error:
*WARNING* Value input must be a number - setting back to previous value.

Does anybody know how I can fix this issue?
Thanks

Dear all,

Hi!

I'm trying to do a Harmonic Balance (HB) Large-Signal S-Parameter (LSSP) simulation to figure out the input impedance of a nonlinear circuit.

Through this simulation, what I want to know is the large-signal S11 only (not S12, S21 and S22).

So, I have simulated with only single port (PORT0) at input, but LSSP simulation is terminated and output log shows following text.

" Analysis `hb' was terminated prematurely due to an error "

The LSSP simulation does not proceed without second port.

Should I use floating second port (which is not necessary for my circuit) to succeed the LSSP simulation?

Does the LSSP simulation really need two ports?

Below figure is my HB LSSP simulation setup.

Additionally, Periodic S-Parameter (PSP) simulation using HB is succeeded with only single port.

What is the difference between PSP and LSSP simulations?

Hi,

In our design team, we're looking for a strategy to make all cell views self-contained. We are struggling to do so when nport devices are involved.

The nport file requires a full path, whereas what we need is a relative path to the current path of the cell in which we're using the nport.

I have browsed through the forums & cadence support pages, but could not find a solution.

1) There is a proposal from Andrew to add the file directory in ADE option "Simulation Files." :https://community.cadence.com/cadence_technology_forums/f/rf-design/27167/s-parameter-datafile-path-in-nport . This, however, is not suitable, because the cell is not self contained.

2) The new cadence version off DataSource "cellView" in nport options:

This however is not suitable for us due to two reasons:

i- Somehow we don't get this option in the nport cell (perhaps some custom modification from our PDK team)

ii- Even if we had this option, it requires to select the library, which again makes it unsuitable: We often copy design libraries for derivative products using "Hierarchical Copy" feature. And when the library is copied, the nport will still be pointing to the old library. Thus, it is still not self-contained.

In principle, it should not be difficult (technically) to point to a text file relative to the cell directory (f.ex we can make a folder under the same cell with name "sparFiles" & place all spar files under this folder), however it does not seem to be possible.

Could you perhaps recommend us a work-around to achieve our goal: making the cells which contain nport devices self-contained so that when we copy a cell, we do not have to update all the nport file destinations ?

Thanks in advance.

My Cadence Version: IC23.1-64b.ISR4.51

My Spectre version: 23.1.0.362.isr5

Che(read more)

New York continues to reign as leader of fDi’s American Cities of the Future 2019/20 ranking. San Francisco retains second place with Toronto rising to third. Naomi Davies reports.

A more detailed look at fDi's judges’ top five American Cities of the Future 2019/20 for FDI strategy. Naomi Davies reports.

Uruguay-based Zonamerica has successfully expanded into Colombia and China, and is now looking to export its model to other parts of Asia and Africa.

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 

While governments grow more protectionist over trade and physical borders, companies such as Microsoft are bridging the gap by funding international collaborative enterprises.

Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf.

Up to 18 countries across Latin America have joined China’s new Belt and Road Initiative, hoping to boost their infrastructure development and investment.  

The coronavirus pandemic could change human behaviour more permanently in future.

The fallout from the pandemic looks set to stall trade and investment to Latin America.

Good news for games developers: the Australian Government is introducing a 30% tax offset for local and international businesses that develop digital games in Australia.

Recent South American free trade agreements will have implications for Australian agricultural exports.

Xbox Game Pass Ultimate gives gamers access to hundreds of games, exclusive deals, and more. Three-month stackable memberships are on sale for £28.35.

One prominent Apple prognosticator says the company is working on a smart home camera for launch in 2026.

First Nations business Aldridge Railway Signals was named Exporter of the Year at Supply Nation’s Supplier Diversity Awards.

The Federal Energy Regulatory Commission has received two applications for preliminary permits for a pumped storage project at Lake Elsinore in California.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the third quarter of 2023 closed with 359.3 million domain name registrations across all top-level domains (TLDs), an increase of 2.7 million domain name registrations, or 0.8%, compared to the second quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 359.3 Million Domain Name Registrations in the Third Quarter of 2023 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the fourth quarter of 2023 closed with 359.8 million domain name registrations across all top-level domains (TLDs), an increase of 0.6 million domain name registrations, or 0.2%, compared to the third quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 359.8 Million Domain Name Registrations in the Fourth Quarter of 2023 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the first quarter of 2024 closed with 362.4 million domain name registrations across all top-level domains (TLDs), an increase of 2.5 million domain name registrations, or 0.7%, compared to the fourth quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.4 Million Domain Name Registrations in the First Quarter of 2024 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the second quarter of 2024 closed with 362.4 million domain name registrations across all top-level domains (TLDs), unchanged compared to the first quarter of 2024. Domain name registrations increased by 5.8 million, or 1.6%, year over year. Check […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.4 Million Domain Name Registrations in the Second Quarter of 2024 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the third quarter of 2024 closed with 362.3 million domain name registrations across all top-level domains (TLDs), a decrease of 0.1 million domain name registrations, or less than 0.05%, compared to the second quarter of 2024. Domain name […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.3 Million Domain Name Registrations in the Third Quarter of 2024 appeared first on Verisign Blog.

NVIDIA today announced that it has named to its board of directors Ellen Ochoa, who was the former director of NASA’s Johnson Space Center in Houston, and the first Latina astronaut in space.