Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Sample clues

18 across: Makoto Hagiwara and David Jung both claim to have invented it (7,6)

1 down: French impressionist who rejected that term (5)

3 down: Artificial surface used for playing hockey (9)

7 down: The sequel to Iliad (7)

12 down: Adipose tissue (4,3)

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Sample clues

6 across: Franchise revived by Frank Miller (6)

13 across: What Keanu Reeves and Zayed Khan have in common (5)

18 across: What Frank Sinatra and George Clooney have in common (6,6)

19 across: Dosa mix, for example (6)

2 down: Green, in a non-environmental way (7)

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Sample clues

5 down: Torso covering (6)

7 down: Government by rogues (12)

15 across: eBay speciality (7)

18 across: Demonic (8)

20 across: Common language (6,6)

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Sample clues

17 across: Beckham speciality (4,4)

4 down: Havana speciality (5)

19 across: Infamous 1988 commercial against Michael Dukakis (9,4)

11 down: Precisely (2,3,3)

13 down: City infamously ransacked by the Japanese in 1937 (7)

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Sample clues

11 across: Chandigarh’s is 0172 (3,4)

21 across: He’s a loser, baby (4)

1 down: Garment meant to shape the torso (6)

12 down: It’s slogan: “Life, Liberty and the Pursuit” (8)

18 down: Noise made by badminton players? (6)

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Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

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Sample clues

14 across: FDR’s baby (3,4)

1 down: A glitch in the Matrix? (4,2)

4 down: Slanted character (6)

5 down: New Year’s venue in New York (5,6)

16 down: Atmosphere of melancholy (5)

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Sample clues

6 across: Alejandro González Iñárritu’s breakthrough film (6,6)

19 across: Soft leather shoe (8)

7 down: Randroids, for example (12)

12 down: First American World Chess Champion (7)

17 down: Circle of influence (5)

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Sample clues

5 across: Robbie Robertson song about Richard Manuel (6,5)

2 down: F5 on a keyboard (7)

10 across: Lionel Richie hit (5)

3 down: ALTAIR, for example (5)

16 down: The problem with Florida 2000 (5)

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Sample clues

9 across: Van Morrison classic from Moondance (7)

6 down: Order beginning with ‘A’ (12)

6 across: Fatal weakness (8,4)

19 across: Rolling Stones classic (12)

4 down: Massacre tool (8)

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Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.(read more)

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more)

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.(read more)

Which Analysis is Being Performed by Allegro in this Image?

A. Impedance

B. Coupling

C. Crosstalk

D. Return Path

E. Reflection

Simply answer by letter or include any reason to support your answer...

Hi

the signal SPI_SCLK belongs to TWO Spacing CLASSES: CLS_SP_SPI and CLS_SP_SPI_CLOCK

I then assign TWO different SPACING RULES to each class : CLS_SP_SPI  > 2H and CLS_SP_SPI_CLOCK > 3.5H

Which SPACING RULE will inherit the signal SPI_SCLK ??

Is it possible to manually define the PRIORITY on Design Rules ??

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

hello

is there a way to scale a footprint of a symbol?

scaling a footprint means moving all the pad locations of the symbol by +x% or -x%. 

regards

masa

Hello everyone!

Have you ever used the axlDllOpen function for Allegro 16.6?

It doesn't work for me. Please give me your solution.
Thank you.

HoangKhoi

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Hai Community,

I have a PCB board which has multiple high speed nets and I want to perform the EMI and EMC checking.

Which Cadence tool should I use for checking the EMI and EMC coupling?

Regards,

Rohit Rohan

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Hai Community,

What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24.

Can I get the grid matrix difference between these two tools?

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

Has anyone experienced the same situation?

The world of electronics design thrives on efficient tools that bridge the gap between concept and silicon. Virtuoso Digital Implementation is a powerful ally for mixed-signal designs, which integrate both analog and digital components. This blog post will examine Virtuoso Digital Implementation's capabilities and explore how it can streamline your mixed-signal design workflow.

Virtuoso Digital Implementation in a Nutshell

Virtuoso Digital Implementation is a license package within the Cadence Virtuoso Design Platform. It offers a streamlined RTL-to-GDSII flow to implement smaller digital blocks within a mixed-signal design environment. Here's what makes Virtuoso Digital Implementation stand out:

• Focus on Small Digital Blocks: Optimized for digital blocks with an instance count of up to 50,000 (expandable to 150,000 with specific configurations), Virtuoso Digital Implementation is ideal for integrating digital logic into your analog-centric design.
• Leveraging Industry Leaders: Virtuoso Digital Implementation utilizes cut-down versions of the renowned Cadence Genus Synthesis Solution and Innovus Implementation System under the hood. This ensures you get access to proven technologies for logic optimization and place-and-route.
• Seamless Integration with the Virtuoso Environment: Virtuoso Digital Implementation's key advantage is its tight integration with the Virtuoso Layout Suite. You can launch the synthesis and place-and-route tools directly from the Virtuoso environment, eliminating the need to switch between platforms.

Benefits of Using Virtuoso Digital Implementation

 By incorporating Virtuoso Digital Implementation into your mixed-signal design flow, you can get several benefits:

• Simplified Workflow: Virtuoso Digital Implementation offers a centralized environment for both digital block implementation and layout editing within the Virtuoso environment. This reduces context switching and streamlines the design process.
• Faster Time-to-Market: Virtuoso Digital Implementation's streamlined workflow can significantly reduce design turnaround times, allowing you to get your product to market quicker.
• Improved Design Quality: Leveraging industry-leading synthesis and place-and-route engines from Cadence ensures high-quality digital block implementation within your mixed-signal design.

Who Should Consider Virtuoso Digital Implementation?

 Virtuoso Digital Implementation is a valuable tool for anyone working on mixed-signal designs with smaller digital blocks. It's particularly well-suited for:

• Analog IC designers who need to integrate digital logic into their designs.
• Circuit design teams working on mixed-signal applications like data converters, power management ICs, and RF transceivers.

Virtuoso Digital Implementation provides a compelling solution for designers working on mixed-signal projects. Its streamlined workflow, tight integration with the Virtuoso design platform, and access to proven digital design tools can significantly improve design efficiency and time-to-market. Virtuoso Digital Implementation is worth considering if you're looking to optimize your mixed-signal design flow.

I am here to help and guide you on how to learn more about Virtuoso Digital Implementation flow.

Welcome to Virtuoso Digital Implementation, an online course recently released. This course teaches implementing digital blocks using Cadence tools based on the Virtuoso Digital Implementation flow. Also, you can download a lab database after the lecture and get hands-on experience in each stage.

Want to Enroll in this Course?

We organize this Virtuoso Digital Implementation training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

• Log on to cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for Virtuoso Digital Implementation using the search bar.
• Select the course and click Enroll.

And don't forget to obtain your Digital Badge after completing the training!

Related Resources

Online Courses

• Cadence RTL-to-GDSII Flow v6.0
• Virtuoso Digital Implementation Training

Training Byte Videos

• How Do You Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus?

Happy Learning!

A more appropriate title for this blog could be “All Vehicles with ADAS Need the Midas Functional Safety Platform”.

EVs tend to have advanced driving assistance systems (ADAS) because they’re newer, but not all vehicles with ADAS are EVs!

Certifying Advanced Driver Assistance Systems (ADAS) is a multifaceted process involving rigorous testing, validation, and regulatory compliance to ensure safety and reliability.
As ADAS technologies become increasingly sophisticated, the certification process is evolving to meet these challenges.

The ISO26262 standard provides the requirements to be met to attain safety certification for digital designs.

One of the key aspects of ADAS certification is functional safety. This includes:

• Ensuring the system operates as intended under all conditions, including failures.
• Adherence to standards like ISO26262.
• Rigorous testing to identify potential hazards and mitigate risks.

The Midas Safety Platform provides early-phase exploration of functional safety architectures and leverages native chip design data to perform accurate safety analysis efficiently.

The platform is a unified solution available across Cadence products, and with its modular architecture, it supports both embedded and standalone usage with the Cadence flow.

After extracting the design information, an output Midas database file contains the isolated DUT and provides the design components and their fault tolerances to various tools in the flow.

Conformal can easily verify design transformations that include necessary components like TMR for safety.

In these videos, we explore how to create reports for both Transient and Permanent faults.

Creating Detailed FMEDA in Midas (Video)

Creating Architectural FMEDA in Midas (Video) 

Also, read this blog post for additional motivation: What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

What Next?

Join the Midas Safety Platform Introduction and the Functional Safety Implementation and Verification with Midas trainings and learn more about:

• Setting up and defining the USF file
• Using the Midas Safety Platform to create functional safety reports, and
• Midas integration with the Genus  Synthesis Solution, Innovus  Implementation System, and Conformal Equivalence Checker tools to implement functional safety

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

If you want to make sure you are always the first to know about anything new in training, then you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.

When Is the Webinar?

Date and Time

Wednesday, September 18, 2024
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing 

REGISTER

To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System.

Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.

If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

To view our complete training offerings, visit the Cadence Training website.

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Want to Learn More?

This link gives you more information about the related training course and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Also, take this opportunity to register for the free Online Trainings related to this webinar topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Xcelium Integrated Coverage

Related Training Bytes

How to Run the Synthesis Without DFT?

How to Run the Synthesis Flow with DFT? (Video)

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions.

Conformal ECO compares two designs and generates a functional patch that implements the changes between the two designs.

One major criterion for determining patch quality is whether the patch can meet timing closure. To determine this, you typically need to run the time-consuming process of incremental synthesis and place-and-route. Instead, Conformal can analyze path logic depth changes before and after ECO patch generation. This provides a faster way to evaluate timing impact in patch generation stages.

After the patch is created and applied, it is passed to Genus to optimize the patch.

During patch optimization, you can choose to do many things like:

• Keeping constants in the patch
• Allowing tie cell inversion
• Specifying tie cell types
• Preserve DFF cells and cell types in the patch
• Preserve all cells and nets in the patch
• Preserve clock buffer cell in the patch
• Turn on/off sequential constant and sequential merge in patch optimization
• Allowing phase mapping for DFFs
• Map to spare cells
• Force fix DRC before timing

What's Next?

Join the Conformal ECO course to:

• Explore the many options and capabilities of Conformal ECO
• Use Conformal Engineering Change Order (ECO) for flat and hierarchical designs
• Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology
• Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
• Run a postmask ECO using Conformal ECO GXL

Make sure you have experience with Conformal Equivalence Checker or completed the Conformal Equivalence Checking course before taking this course.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both "Blended" and "Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
• If you would like to stay up-to-date with the latest news and information about Cadence trainings and webinars, subscribe to the Cadence Training emails.

Related Blogs

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Binge on Chip Design Concepts this Weekend!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs:

Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community

Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community

Let's Replay the Process of Power Estimation with the Power of 'x'! - Digital Design - Cadence Blogs - Cadence Community

Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

The UAE's DMCC takes home the top prize in fDi’s Global Free Zones of the Year for a fifth consecutive year. 

Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders.

Combining a strategic location with an investor-friendly environment, Egypt is ensuring its Suez Canal Economic Zone is primed for foreign investment. 

North Rhine-Westphalia is fDi's top large region for FDI Strategy, with the Basque Country topping the table for mid-sized regions and Ireland South East first among small regions. 

From historically underperforming when compared with its peers, the German federal state of Rhineland-Palatinate is now attracting major investment projects on the back of its auto and electrification expertise.

Frankfurt (Oder) is building on the strengths of its university to foster the development of successful start-ups through new co-working spaces and the promotion of sustainable practices and products. 

Stevens Mokgalapa talks about foreign investment opportunities and challenges in South Africa’s administrative capital, and the balancing act of development and environmental needs in the developing world.

Despite its thriving automotive sector, Gothenburg is vulnerable to global economic pressures. However, local authorities are confident that their strategies will see the city ride out the uncertainties related to Brexit and the US-China trade wars.

US web infrastructure and cyber security company Cloudflare wants to improve people’s internet experiences through affordable, reliable and accessible interconnection points, especially in less privileged parts of the world. 

Passion Capital's Eileen Burbidge talks to fDi about what fintech companies should consider when expanding internationally, and why London will always be a key market in the sector.

Financial incentives from two different cities persuaded US grocery chain The Fresh Market to stay headquartered in its home state of North Carolina.

Global FDI flows recorded a marginal 1% fall in 2019, but the value of announced greenfield investment projects plummets by 22%.

ING Media names Tokyo, New York, London and Paris as global super brands for digital visibility.

India’s 2020 budget continues the process of opening up to overseas investment.

The US has the world’s strongest soft power, while China and Russia are rising in influence, according to a recent ranking from Brand Finance.

Kazakhstan’s sovereign wealth fund, Samruk-Kazyna, has approved a new 2018 to 2028 strategy that will eventually expand its investment activity beyond the domestic market.

The eastern Chinese city of Zibo is recognised as the official birthplace of football. However, its local government is hoping it will soon be known for its excellence in the chemical, medical and manufacturing industries.