This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.(read more)

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this blog.(read more)

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

This blog helps in demonstrating the use of Pin to trunk routing style which helps in enhancing the layout experience.(read more)

Is there a way to set a thru via hole to thru via hole spacing constraint?

I need the hole to hole spacing, nit pad to pad spacing.

I can calculate the spacing using the via pad diameter, but this won't work for multiple via pad sizes.

Hello,

I have a sensitive trace on layer 2 and I would like to prevent any routing along or across it on adjacent layers (L1 and L3).

My idea was to use a route keepout shape on L1 and L3, however that also removed the ground pour on those layers and I would like to keep the ground pour.

Can I get around this somehow or should I use something else than route keepout?

Regards,

Filip

hello.

i have asked this question a few years back but no good answer so i ask again.

i would like to spread clines with equal spacing.

i do know how to spread clines between vias.

but i would like to simply spread clines between two clines (not between two vias).

for instance, there are 4 parallel clines but the inner 3 spaces are not equal so i would like to move the inner 2 clines to make the 3 spaces equal.

regards

masa

hello

is there a way to update one dynamic shape instead of updating all dynamic shapes?

i have over 6000 dynamic shapes on my design and it takes over 10 mins to update them all.

i just would like to update only one dynamic shape sometimes to find out if placing vias and lines in a shape has enough space or not.

regards

masa

Hi

the signal SPI_SCLK belongs to TWO Spacing CLASSES: CLS_SP_SPI and CLS_SP_SPI_CLOCK

I then assign TWO different SPACING RULES to each class : CLS_SP_SPI  > 2H and CLS_SP_SPI_CLOCK > 3.5H

Which SPACING RULE will inherit the signal SPI_SCLK ??

Is it possible to manually define the PRIORITY on Design Rules ??

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

hello

is there a way to scale a footprint of a symbol?

scaling a footprint means moving all the pad locations of the symbol by +x% or -x%. 

regards

masa

hello:

i place a symbol into my design.

on my design, i change the symbol property by unlocking the symbol and unfixing pins so that i can move pins on the symbol.

i move some pins on my design.

but when i export the symbol from my design, the symbol is not current but has the original pin location.

is there a way to retain the pin locations after moving pins on a symbol when exporting the symbol?

regards

masa

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Hello,

Trying to figure out why this situation does not generate a DRC error.

A resistor was accidently placed so the pad was on top of another pad. See picture:

I have checked the CM and both Spacing Constraint Set and Same Net Spacing Constraint Set have Smd pin to Smd pin set to 0.1 mm.

I'm using Allegro PCB designer 22.1.

If someone has an idea why this does not give a DRC i would appreciate it. Thanks.

Regards,

Filip

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

Has anyone experienced the same situation?

The blog discusses Voltus InsightAI RAK that is designed to give you an accelerated start on the execution of Voltus InsightAI flow.(read more)

The world of electronics design thrives on efficient tools that bridge the gap between concept and silicon. Virtuoso Digital Implementation is a powerful ally for mixed-signal designs, which integrate both analog and digital components. This blog post will examine Virtuoso Digital Implementation's capabilities and explore how it can streamline your mixed-signal design workflow.

Virtuoso Digital Implementation in a Nutshell

Virtuoso Digital Implementation is a license package within the Cadence Virtuoso Design Platform. It offers a streamlined RTL-to-GDSII flow to implement smaller digital blocks within a mixed-signal design environment. Here's what makes Virtuoso Digital Implementation stand out:

• Focus on Small Digital Blocks: Optimized for digital blocks with an instance count of up to 50,000 (expandable to 150,000 with specific configurations), Virtuoso Digital Implementation is ideal for integrating digital logic into your analog-centric design.
• Leveraging Industry Leaders: Virtuoso Digital Implementation utilizes cut-down versions of the renowned Cadence Genus Synthesis Solution and Innovus Implementation System under the hood. This ensures you get access to proven technologies for logic optimization and place-and-route.
• Seamless Integration with the Virtuoso Environment: Virtuoso Digital Implementation's key advantage is its tight integration with the Virtuoso Layout Suite. You can launch the synthesis and place-and-route tools directly from the Virtuoso environment, eliminating the need to switch between platforms.

Benefits of Using Virtuoso Digital Implementation

 By incorporating Virtuoso Digital Implementation into your mixed-signal design flow, you can get several benefits:

• Simplified Workflow: Virtuoso Digital Implementation offers a centralized environment for both digital block implementation and layout editing within the Virtuoso environment. This reduces context switching and streamlines the design process.
• Faster Time-to-Market: Virtuoso Digital Implementation's streamlined workflow can significantly reduce design turnaround times, allowing you to get your product to market quicker.
• Improved Design Quality: Leveraging industry-leading synthesis and place-and-route engines from Cadence ensures high-quality digital block implementation within your mixed-signal design.

Who Should Consider Virtuoso Digital Implementation?

 Virtuoso Digital Implementation is a valuable tool for anyone working on mixed-signal designs with smaller digital blocks. It's particularly well-suited for:

• Analog IC designers who need to integrate digital logic into their designs.
• Circuit design teams working on mixed-signal applications like data converters, power management ICs, and RF transceivers.

Virtuoso Digital Implementation provides a compelling solution for designers working on mixed-signal projects. Its streamlined workflow, tight integration with the Virtuoso design platform, and access to proven digital design tools can significantly improve design efficiency and time-to-market. Virtuoso Digital Implementation is worth considering if you're looking to optimize your mixed-signal design flow.

I am here to help and guide you on how to learn more about Virtuoso Digital Implementation flow.

Welcome to Virtuoso Digital Implementation, an online course recently released. This course teaches implementing digital blocks using Cadence tools based on the Virtuoso Digital Implementation flow. Also, you can download a lab database after the lecture and get hands-on experience in each stage.

Want to Enroll in this Course?

We organize this Virtuoso Digital Implementation training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

• Log on to cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for Virtuoso Digital Implementation using the search bar.
• Select the course and click Enroll.

And don't forget to obtain your Digital Badge after completing the training!

Related Resources

Online Courses

• Cadence RTL-to-GDSII Flow v6.0
• Virtuoso Digital Implementation Training

Training Byte Videos

• How Do You Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus?

Happy Learning!

Training Bytes are not just short technical videos; they are particularly designed to provide comprehensive support in understanding and learning various concepts and methodologies.

These comprehensive yet small Training Bytes can be created to show various concepts and processes in a shorter pane of five to ten minutes, for example, running DFT synthesis, scanning insertion, inserting advanced testability features, test point insertion, debugging DFT violations, etc.

In this blog, we will show you the DFT Synthesis Flow with Cadence's Genus Synthesis Solution using small Training Bytes available on the Cadence Learning and Support Portal. To explore these training bytes more, log on to support.cadence.com and select the learning section to choose the training videos, as shown below.

DFT Synthesis Flow with Genus Synthesis Solution

First, we will understand the Synthesis Flow with DFT in the Genus Synthesis Solution:

Understanding a Script File that Used to Run the Synthesis Flow With DFT

Here, we will show you "How to run the Test Synthesis Flow to Insert Scan Chains and Improve the Testability of a Design" in the Genus Synthesis Solution:

Running Test Synthesis Flow to Insert Scan Chains And Improve the Testability of a Design in the Genus Synthesis Solution

Let's check the flops marked with the dft_mapped attribute for scan mapping in Genus Synthesis Solution:

How to Check Flops Marked With dft_mapped Attribute For Scan Mapping in Genus Synthesis Solution?

How to Find Non-Scan Flops of a Design in Genus? (Video)

Once the flops are mapped to scan flip flops and the scan chain inserted, we will see how to handle the flops marked with the dft_dont_scan attribute for scan mapping in Genus Synthesis Solution.

How to Handle the Flops Marked With the dft_dont_scan Attribute For Scan Mapping in Genus Synthesis Solution?

Here, we will see how to fix DFT Violations using the command fix_dft_violations:

Fixing DFT Violations (Video)

Once the design has been synthesized, let's explore the DFT design hierarchy in Genus Stylus CUI:

Exploring DFT Design Hierarchy in Genus Stylus CUI (Video)

Understand why sequential elements are not mapped to a scan flop:

Why Are Sequential Elements Not Mapped to a Scan Flop?

Explore hierarchical scan synthesis in Genus Stylus Common UI:

Understanding Hierarchical Scan Synthesis in Genus Stylus Common UI. (Video)

To understand how to resolve different warnings and errors (for example, DFT-415, DFT-512, DFT-304, etc.) in Genus Synthesis Solution, here are some videos you can refer to:

How to Resolve Warning: DFT-415 (Video)

How to Resolve Error: DFT-407 (Video)

How to Resolve Error: DFT-404 (Video)

DFT-510 Warning During Mapping (Video)

How to Resolve Warning: DFT-512 (Video)

How to Resolve Warning: DFT-511 (Video)

How to Resolve Warning: DFT-304 (Video)

How to Resolve Warning: DFT-302 (Video)

How to Resolve Error: DFT-515 (Video)

How to Resolve Error: DFT-500 (Video)

Here, we will see how we can generate SDC constraints for DFT constructs for many scan insertion techniques, such as FULLSCAN, OPCG, Boundary Scan, PMBIST, XOR Compression, SmartScan Compression, LBIST, and IEEE 1500:

How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution? (Video)

Explore advanced testability features that can be inserted in Genus Synthesis Solution, such as Boundary Scan, Programmable Memory built-in Self-Test Logic (PMBIST), Compression Logic, Masking, and On-Product Clock Generation Logic (OPCG):

Advanced Testability Features (Video)

To understand What the IEEE 1500 Wrapper and its Insertion Flow in Genus Synthesis Solution, follow the bytes:

What Is IEEE 1500 Wrapper? (Video)

IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution (Video)

Understand the On-product Clock Generation (OPCG) insertion flow in Genus Synthesis Solution Stylus CUI with this byte:

Understanding On Product Clock Generator (OPCG) Insertion in Genus Stylus CUI (Video)

To debug DFT violations, you can use DFT Analyzer from Genus GUI and explore its features here:

Debugging Using GUI: DFT Analyzer (Video)

Exploring DFT Analyzer View of Genus Synthesis Solution GUI (Video)

To understand What is Shadow Logic, How to Insert Test Points, How to do Testability Analysis Using LBIST, and How to Deterministic Fault Analysis in Genus, follow this article:

What is Shadow Logic

To insert the Boundary Scan Logic in and control Boundary Optimization in Genus Synthesis Solution, refer to these small bytes:

How to Insert Boundary Scan Logic in Genus? Video)

Controlling Boundary Optimization in Genus Synthesis Solution Stylus CUI (Video)

Compression techniques are used during scan insertion to reduce the test data volume and test application time (TAT) while retaining the test coverage. To understand what compression and the compression techniques are, watch this article:

What is Compression Technique During Scan Insertion? (Video)

Interested to know what "Unified Compression" is? To get the concept, you can watch this small demo:

What Is Unified Compression? (Video)

To Explore More, Register for Online Training

• Log on to Cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for "Test Synthesis with Genus Stylus Common UI" using the search bar.
• Select the course and click "Enroll."

Designing 3D-ICs with integrity involves a commitment to ethical practices, reliability, and sustainability throughout the design and manufacturing process. This includes using environmentally friendly materials, ensuring robust and efficient performance, and incorporating thorough testing and verification. By prioritizing transparency, responsibility, and long-term sustainability, designers can create advanced integrated circuits that meet high standards of quality and social responsibility.

Start Learning Now!

Start with our Designing with Integrity 3D-IC online course, which introduces Integrity 3D-IC, the industry's first comprehensive, high-capacity 3D-IC platform that integrates 3D design planning, implementation, and system analysis in a single, unified environment. You will be guided through the following activities involved in designing a silicon interposer with a digital ASIC and HBM2 interface in a 2.5D configuration.

• You will design the interposer from scratch in the new Integrity System Planner and the Integrity 3D-IC implementation environment.
• You will examine the ASIC and interposer designs using some of the new 3D-IC multi-die design features.
• You will route the interposer using some of the new advanced routing capabilities with NanoRoute

—and this in only two days!

WATCH VIDEO

Interested? Get an overview in less than two minutes.

Are you primarily interested in selected snippets instead? Then, take our Training Bytes, which—like the online training course—are available to Cadence customers for free 24/7 in the Cadence Learning and Support portal.

Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise.

To find out more, see the blog post. It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Related Resources

• 3D-IC Introduction (Video)
• 3D-IC Development Process With Challenges. (Video)
• Demo: How to Create the Interposer Contact Pads and Die Connectivity Using the Integrity 3D-IC? (Video)
• Demo: How To Pull The Interposer Design From System Planner Into Integrity 3D-IC Layout? (Video)
• Demo: Routing The Interposer Design Using The Integrity 3D-IC Layout_Part 1 (Video)
• Demo: Routing The Interposer Design Using The Integrity 3D-IC Layout_Part 2 (Video)
• Demo: How To Create C4 Bumps For NC Connections And Generating C4 Dummy Cover Bumps In Integrity 3D-IC? (Video)

Related Blogs

• How Cadence Is Expanding Innovation for 3D-IC Design
• Training Bytes: They May Be Shorter, But the Impact Is Stronger!
• Training Insights — 3D-IC: What Is Silicon Interposer?
• System Analysis Knowledge Bytes: What’s New in the Clarity 3D Solver Course
• System Analysis Knowledge Bytes - Early System-Level Thermal Analysis
• 3D-IC: The Future of Integrated Electronics Is the Future of Electronics Itself

Related Trainings

• OrbitIO System Planner
• Allegro Package Designer Plus

The traditional methods of power analysis lag by various shortcomings and challenges:

• Getting an accurate measure of RTL power consumption during design exploration
• Getting consistent power through the design progress from RTL to P&R.
• System-level verification tools are disconnected from the implementation tools that translate RTL to gates and wires.

The Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes, capacity, and high-quality estimates of gates and wires based on production implementation technology. The Cadence Joules RTL Power Solution is an RTL power analysis tool that provides a unified engine to compute gate netlist power and estimate RTL power. The Joules solution delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power.

Moreover, it integrates seamlessly with numerous Cadence platforms, eliminating compatibility and correlation issues! In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities.

Want to take a tour of this power estimation world? Gear up to attend the training class created just for you to dive deep into the entire flow and explore this exciting power estimation method/flow with hands-on labs in two days!

Training

In the Joules Power Calculator Training course, you will identify solutions and features for RTL power using Cadence Joules RTL Power Solution. You will set up and run the RTL power flow with Joules RTL Power Solution and identify Joules's Graphical User Interface (GUI) capabilities. The training also explores how you can estimate power using vectorless power, stimulus flow, RTL Stim to Gate flow, and replay flow, and also interfaces Joules with Cadence's Palladium Emulation Platform. You will estimate power at the chip level and understand how to navigate the design and data mining using Joules.

The training also covers power exploration features and how to analyze ideal power and ODC-driven sequential clock gating. You will identify low-activity registers at the clock gate. You will also identify techniques to analyze power, generate various reports, and analyze results through Joules GUI. The training covers multiple strategies to debug low stimulus annotation and how you can better correlate RTL power with signoff. You also identify Genus-Joules Integration. In addition, we ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

To start you on your exciting journey as an RTL power analysis expert, we have created a series of short channel lab videos on our Customer Support site: Lab Demo: Setting Up and Running Basic RTL Power Flow in Joules RTL Power Solution (Video). You can refer to each lab module's instructions in demo format. This will help accelerate your tool ramp-up and help you perform the lab steps more quickly if you are stuck. You might be a beginner in the RTL power analysis world, but we can help you sail through it smoothly.

What's Next?

Grab your badge after finishing the training and flaunt your expertise!

Related Training

• Genus Low-Power Synthesis Flow with IEEE 1801
• Low-Power Synthesis Flow with Genus Stylus Common UI

Related Blogs

• Do You Want to Flaunt Your Expertise? Grab the Digital Badge Today!
• Become Cadence Certified
• Let's Replay the Process of Power Estimation with the Power of 'x'
• Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit
• What's Inside Joules Graphical User Interface
• Joules – Power Exploration Capabilities

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both "Blended" and "Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
• If you would like to stay up-to-date with the latest news and information about Cadence trainings and webinars, subscribe to the Cadence Training emails.

Related Blogs

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Binge on Chip Design Concepts this Weekend!

This blog informs about the new badge certification available for Cadence Certus Closure Solution, that grants credit to your proficiency.(read more)

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

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The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Related Training Bytes

What is RTL Coding In VLSI Design?

What is Digital Verification?

What Is Synthesis in VLSI Design?

What Is Logic Equivalence Checking in VLSI Design?

What Is DFT in VLSI Design?

What is Digital Implementation?

What is Power Planning?

What are DRC and LVS in Physical Verification?

What are On-Chip Variations?

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Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

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London event hears how the UK export credit agency is increasing its focus on trade with African countries. Jason Mitchell reports.

Warsaw already offers a skilled workforce and has improved its infrastructure – now it must focus on climate change and reducing congestion, mayor Rafał Trzaskowski tells fDi.

Having opened new production facilities in Rwanda and South Africa, Mara Phones is looking to alter Africa's mindset from being a 'consumer' to being a 'manufacturer'. 

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The social turmoil in Hong Kong has triggered an economic crisis, raising questions over the special administrative region’s future as a major financial hub on mainland China’s doorstep. 

China's coronavirus outbreak is having a seismic effect in Asia and beyond, writes Lawrence Yeo.

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 

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