The silkscreen layer plays a crucial role in the assembly, repair, and testing of a PCB. You can add a variety of information to this layer, such as the location of the components, polarity, component orientation, on-off switches, LEDs, and testpoint...(read more)

Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently announced products of Optimality and OnCloud.(read more)

Do you know if it is possible to define localized back etching (LBE) in EMX? It should be associated to a layer which defines the holes done in the substrate. I've not found any reference for this in the .proc syntax. 

--> Answer found. This is not possible because EMX considers the same dielectric in all x-y plane

Hi,

My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2

I have an expression where the EvalType is "sweeps". Here is the expression (I also attached the snapshot):

(peakToPeak(leafValue(swapSweep(delay(?wf1 clip((VT("/clk0") - VT("/clk180")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value1 0 ?edge1 "rising" ?nth1 1 ?td1 0 ?tol1 nil ?wf2 clip((VT("/tx_padp") - VT("/tx_padn")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value2 0 ?edge2 "rising" ?nth2 1 ?tol2 nil ?td2 nil ?stop nil ?multiple nil) "VDD_FIXED_NOISE") "VREGLN_cmode" 0.85 "VREGDRV_novn" 0.4 "datarate" 1.658e+10) ?overall t) / 10.0)

What this expression does is that it compares the delay between the output data with respect to a reference clock. I then get this information for two conditions (VDD_FIXED_NOISE = 0 or 10mV) to get the effect of the supply-induced jitter. In the expression, I need to give the value of each parameter in different modes to distinguish them from each other. Now I want to sweep the base supply values and see the supply variation effects. For example, I want to change VREGLN_cmode from 0.85 to 0.81 and see how my supply-induced jitter changes. For that, the hard way is to copy the expression and change that value accordingly (e.g. "VREGLN_cmode" 0.81). I'm looking for an easier way to use a variable in the expression. Something like VAR("VREGLN_Sweep"). But I see it doesn't work in my expression and it gives an eVal error. I tested this before in other expressions (not sweep type) and it always worked. I have only one test and these variables are all Design Variables and not Global variables.
I want to know what mistake am I doing here and is there a way to make this work. Sorry that if I could not explain better my inquiry. Thank you.

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

Che(read more)

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.(read more)

Concurrent Layout Editing enables more than one designer to work in a hierarchy at the same time. Check out this blog to know more. (read more)

This blog helps in demonstrating the use of Pin to trunk routing style which helps in enhancing the layout experience.(read more)

I am trying to figure out the most efficient workflow for adding test points. My use case involves adding ~100 or so SMT pads at the bottom for bed-of-nails ICT test that are required to be on a test point grid. A lot of the nets are on the top or from inner layers and so have to be brought to the bottom using stubs. I'm used to Xpediiton workflow of being able to set a test point padstack, set a test point grid, and then select a net, add the test point to the bottom layer on the grid with that net attached and then route the stub with gridless routing.

In Orcad, it seems I need to route the stub, switch layer pairs to be both bottom once I bring the stub to the bottom and then change the grid to be the test point grid and then add the test point on the grid. It requires a lot of clicks, very mistake prone requiring lots of oops and very slow for 100+ test points to be brought out at the bottom. 

I'm sure there is a better way that is used by folks with a lot of Orcad experience. Any suggestions?

Which Analysis is Being Performed by Allegro in this Image?

A. Impedance

B. Coupling

C. Crosstalk

D. Return Path

E. Reflection

Simply answer by letter or include any reason to support your answer...

I want to make an opening in the solder mask right above a trace that is acting like a guard ring. Do I really need to go and buy the Allegro Productivity Toolbox add-on for using the Cross-Copy tool for a basic operation like that??

/F

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution, and Quantus Extraction Solution—Socionext achieved remarkable improvements.

Notably, the Tempus DSTA tool dramatically cut timing closure time by 73%, outperforming conventional single-machine STA methods. This achievement, combined with the synergistic use of Cadence's Certus Closure and Tempus Timing solutions, allowed Socionext to meet their ambitious three-day iteration target and double productivity. Additionally, integrating these solutions significantly decreased both human and machine resource needs, slashing memory and disk costs by up to 90% and halving engineering resources during the optimization and signoff phases.

For more on this collaboration, check out the "Designed with Cadence" success story video on Cadence's website and YouTube channel.

Also, don't miss the on-demand webinar "Fast, Accurate STA for Large-Scale Design Challenges," which provides a deeper dive into Socionext's breakthroughs and the innovative solutions that powered their success.

The blog discusses Voltus InsightAI RAK that is designed to give you an accelerated start on the execution of Voltus InsightAI flow.(read more)

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both "Blended" and "Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
• If you would like to stay up-to-date with the latest news and information about Cadence trainings and webinars, subscribe to the Cadence Training emails.

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Binge on Chip Design Concepts this Weekend!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

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Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

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Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

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London has been named fDi’s inaugural Fintech Location of the Future for 2019/20, followed by Singapore and Belfast. 

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London LEP and Thames Valley Berkshire LEP hold on to their respective first and second places in the Local Enterprise Partnership rankings, while Oxfordshire LEP jumps up eight places to third. 

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