While millions face the disease, almost all are facing economic hurdles. No sector is untouched, and no impact is small. Looking beyond oil and aviation, we bring you stories of sectors facing their own unique challenges.

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This new film is the latest remake of Devdas, but what is equally interesting is the fact that it is in conversation with films made in the West. Unlike Bhansali’s more spectacular version of the older story, Anurag Kashyap’s Dev.D is a genuine rewriting of Sarat Chandra’s novel. Kashyap doesn’t flinch from depicting the individual’s downward spiral, but he also gives women their own strength. He has set out to right a wrong—or, at least, tell a more realistic, even redemptive, story. If these characters have lost some of the affective depth of the original creations, they have also gained the hard edges of modern lives.

We don’t always feel the pain of Kashyap’s characters, but we are able to more readily recognize them. Take Chandramukhi, or Chanda, who is a school-girl humiliated by the MMS sex-scandal. Her father, protective and patriarchal, says that he has seen the tape and thinks she knew what she was doing. “How could you watch it?” the girl asks angrily. And then, “Did you get off on it?” When was the last time a father was asked such a question on the Hindi screen? With its frankness toward sex and masturbation, Dev.D takes a huge step toward honesty. In fact, more than the obvious tributes to Danny Boyle’s Trainspotting, or the over-extended psychedelic adventure on screen, in fact, as much as the moody style of film-making, the candour of such questions make Dev.D a film that is truly a part of world cinema.

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For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test equipment. Among the semiconductor designs they create for these products is a test processor chip with over 100 million logic transistors, but also with lots of analog functions.They set out to find a way to speed up their full-chip simulations to a point where they could run the system software. To do that, they needed about a 50X speed-up. Well, they did it!

Figure 1: Advantest SoC Test Products

To skip the commentary, read Advantest's paper here. 

Problem Statement

Software is becoming a bigger part of just about every hardware product in every market today, and that includes the semiconductor test market. To achieve high product quality in the shortest amount of time, the hardware and software components need to be verified together as early in the design cycle as possible. However, the throughput of a typical software RTL simulation is not sufficient to run significant amounts of software on a design with hundreds of millions of transistors.  

Executing software on RTL models of the hardware means long runs  (“deep cycles”) that are a great fit for an emulator, but the mixed-signal content posed a new type of challenge for the Advantest team.  Emulators are designed to run digital logic. Analog is really outside of the expected use model. The Advantest team examined the pros and cons of various co-simulation and acceleration flows intended for mixed signal and did not feel that they could possibly get the performance they needed to have practical runtimes with software testbenches. They became determined to find a way to apply their Palladium XP platform to the problem.

Armed with the knowledge of the essential relationship between the analog operations and the logic and software operations, the team was able to craft models of the analog blocks using reduction techniques that accurately depicted the essence of the analog function required for hardware-software verification without the expense of a continuous time simulation engine.

The requirements boiled down to the following:

• Generation of digital signals with highly accurate and flexible timing

• Complete chip needs to run on Palladium XP platform

• Create high-resolution timing (100fs) with reasonable emulation performance, i.e. at least 50X faster than simulation on the fastest workstations

Solution Idea

The solution approach chosen was to simplify the functional model of the analog elements of the design down to generation of digital signal edges with high timing accuracy. The solution employed a fixed-frequency central clock that was used as a reference.Timing-critical analog signals used to produce accurately placed digital outputs were encoded into multi-bit representations that modeled the transition and timing behavior. A cell library was created that took the encoded signals and converted them to desired “regular signals”. 

Automation was added to the process by changing the netlisting to widen the analog signals according to user-specified schematic annotations. All of this was done in a fashion that is compatible with debugging in Cadence’s Simvision tool.  Details on all of these facets to follow.

The Timing Description Unit (TDU) Format

The innovative thinking that enabled the use of Palladium XP was the idea of combining a reference clock and quantized signal encoding to create offsets from the reference. The implementation of these ideas was done in a general manner so that different bit widths could easily be used to control the quantization accuracy.

Figure 2: Quantization method using signal encoding

Timed Cell Modeling

You might be thinking – timing and emulation, together..!?  Yes, and here’s a method to do it….

The engineering work in realizing the TDU idea involved the creation of a library of cells that could be used to compose the functions that convert the encoded signal into the “real signals” (timing-accurate digital output signals). Beyond some basic logic cells (e.g., INV, AND, OR, MUX, DFF, TFF, LATCH), some special cells such as window-latch, phase-detect, vernier-delay-line, and clock-generator were created. The converter functions were all composed from these basic cells. This approach ensured an easy path from design into emulation.

The solution was made parameterizable to handle varying needs for accuracy.  Single bit inputs need to be translated into transitions at offset zero or a high or low coding depending on the previous state.  Single bit outputs deliver the final state of the high-resolution output either at time zero, the next falling, or the next rising edge of the grid clock, selectable by parameter. Output transitions can optionally be filtered to conform to a configurable minimum pulse width.

Timed Cell Structure

There are four critical elements to the design of the conversion function blocks (time cells):

                Input conditioning – convert to zero-offset, optional glitch preservation, and multi-cycle path

                Transition sorting – sort transitions according to timing offset and specified precedence

                Function – for each input transition, create appropriate output transition

                Output filtering – Capability to optionally remove multiple transitions, zero-width, pulses, etc.

Timed Cell Caveat

All of the cells are combinational and deliver a result in the same cycle of an input transition. This holds for storage elements as well. For example a DFF will have a feedback to hold its state. Because feedback creates combinational loops, the loops need a designation to be broken (using a brk input conditioning function in this case – more on this later). This creates an additional requirement for flip-flop clock signals to be restricted to two edges per reference clock cycle.

Note that without minimum width filtering, the number of output transitions of logic gates is the sum of all input transitions (potentially lots of switching activity). Also note that the delay cell has the effect of doubling the number of output transitions per input transition.

Figure 3: Edge doubling will increase switching during execution

SimVision Debug Support

The debug process was set up to revolve around VCD file processing and directed and viewed within the SimVision debug tool. In order to understand what is going on from a functional standpoint, the raw simulation output processes the encoded signals so that they appear as high-precision timing signals in the waveform viewer. The flow is shown in the figure below.

Figure 4: Waveform post-processing flow

The result is the flow is a functional debug view that includes association across representations of the design and testbench, including those high-precision timing signals.

Figure 5: Simvision debug window setup

Overview of the Design Under Verification (DUV)

Verification has to prove that analog design works correctly together with the digital part. The critical elements to verify include:

• Programmable delay lines move data edges with sub-ps resolution

• PLL generates clocks with wide range of programmable frequency

• High-speed data stream at output of analog is correct

These goals can be achieved only if parts of the analog design are represented with fine resolution timing.

Figure 6: Mixed-signal design partitioning for verification

How to Get to a Verilog Model of the Analog Design

There was an existing Verilog cell library with basic building blocks that included:

- Gates, flip-flops, muxes, latches

- Behavioral models of programmable delay elements, PLL, loop filter, phase detector

With a traditional simulation approach, a cell-based netlist of the analog schematic is created. This netlist is integrated with the Verilog description of the digital design and can be simulated with a normal workstation. To use Palladium simulation, the (non-synthesizable) portions of the analog design that require fine resolution timing have to be replaced by digital timing representation. This modeling task is completed by using a combination of the existing Verilog cell library and the newly developed timed cells.

Loop Breaking

One of the chief characteristics of the timed cells is that they contain only combinational cells that propagate logic from inputs to outputs. Any feedback from a cell’s transitive fanout back to an input creates a combinational loop that must be broken to reach a steady state. Although the Palladium XP loop breaking algorithm works correctly, the timed cells provided a unique challenge that led to unpredictable results.  Thus, a process was developed to ensure predictable loop breaking behavior. The user input to the process was to provide a property at the loop origin that the netlister recognized and translated to the appropriate loop breaking directives.

Augmented Netlisting

Ease of use and flow automation were two primary considerations in creating a solution that could be deployed more broadly. That made creating a one-step netlisting process a high-value item. The signal point annotation and automatic hierarchy expansion of the “digital timing” parameter helped achieve that goal. The netlister was enriched to identify the key schematic annotations at any point in the hierarchy, including bit and bus signals.

Consistency checking and annotation reporting created a log useful in debugging and evolving the solution.

Wrapper Cell Modeling and Verification

The netlister generates a list of schematic instances at the designated “netlister stop level” for each instance the requires a Verilog model with fine resolution timing. For the design in this paper there were 160 such instances.

The library of timed cells was created; these cells were actually “wrapper” cells comprised of the primitives for timed cell modeling described above. A new verification flow was created that used the behavior of the primitive cells as a reference for the expected behavior of the composed cells. The testing of the composed cells included had the timing width parameter set to 1 to enable direct comparison to the primitive cells. The Cadence Incisive Enterprise Simullator tool was successfully employed to perform assertion-based verification of the composed cells versus the existing primitive cells.

Mapping and Long Paths

Initial experiments showed that inclusion of the fine resolution timed cells into the digital emulation environment would about double the required capacity per run. As previously pointed out, the timed cells having only combinational forward paths creates a loop issue. This fact also had the result of creating some such paths that were more than 5,000 steps of logic. A timed cell optimization process helped to solve this problem. The basic idea was to break the path up by adding flip-flops in strategic locations to reduce combinational path length. The reason that this is important is that the maximum achievable emulation speed is related to combinational path length.

Results

Once the flow was in place, and some realistic test cases were run through it, some further performance tuning opportunities were discovered to additionally reduce runtimes (e.g., Palladium XP tbrun mode was used to gain speed). The reference used for overall speed gains on this solution was versus a purely software-based solution on the highest performance workstation available.

The findings of the performance comparison were startlingly good:

• On Palladium XP, the simulation speed is 50X faster than on Advantest’s fastest workstation

• Software simulation running 25 days can now be run in 12 hours -> realistic runtime enables long-running tests that were not feasible before

• Now have 500 tests that execute once in more than 48 hours

• They can be run much more frequently using randomization and this will increase test coverage dramatically

Steve Carlson

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This is an article discussing Apache2 Web Server hardening. Written in Turkish.

HardDrive version 2.1 for iOS suffers from an arbitrary file upload vulnerability.

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The Aastra 6753i IP Telephone suffers from a hardcoded telnetd administrative password.

Many Cisco devices such as Cisco RV340, Cisco RV340W, Cisco RV345, Cisco RV345P, Cisco RV260, Cisco RV260P, Cisco RV260W, Cisco 160, and Cisco 160W suffer from having hard-coded credentials, known GNU glibc, known BusyBox, and IoT Inspector identified vulnerabilities.

Supercars may push automotive design and engineering to the extreme, but they still need to follow the same regulations as ordinary sedans and crossovers. Making a supercar street legal is the hardest part of the development process, Christian von Koenigsegg said in a recent interview with Apex One. Here's why that is so hard. While regulations...

IPC 的首位执行董事关注有关人士，以消除其对于本协会在未来 10 年内能否实现其所有目标和倒闭的担忧。此方法帮助 IPC 发展壮大为国际组织。

An observer of Sir Richard Branson over say 20 years might have remarked how much older he looked as the keynote speaker at the BIO convention this week in San Diego. He struggled for words at times and was visibly tired by the end of his hour on stage; but he had lost nothing of his charm, nor had he varied in his iconoclastic approach to building great enterprises or his views on technology in the face of climate change.

Seagate Technology ships tens of millions of hard disk drives every quarter. Ensuring the quality of each one is a top priority, but not easy. The disk drive manufacturing process is incredibly complex. For example, it takes 1,400 steps just to manufacture the drive head. Even the smallest errors can lead to product flaws. “Mistakes Read article >

The post Seagate Provides the RX to Improve Hard Drive Manufacturing appeared first on The Official NVIDIA Blog.

Found this in Jan 2010 Southern Living magazine. A delicious topping for gingerbread, scones or muffins. Store sauce in refrigerator up to 1 week. Let stand 20 minutes before serving. -- posted by Bren in LR

German Foreign Minister Heiko Maas said in a newspaper interview on Saturday there was a growing risk of a hard Brexit in the midst of the coronavirus crisis as negotiations between Britain and the European Union so far on the future trade relationship had yielded hardly any progress.

Little Richard, the self-proclaimed "architect of rock 'n' roll" whose piercing wail, pounding piano and towering pompadour irrevocably altered popular music while introducing black R&B to white America, died Saturday. He was 87.

Little Richard, whose outrageous showmanship and lightning-fast rhythms intoxicated crowds in the 1950s with hits like “Tutti Frutti” and “Long Tall Sally,” has died. He was 87 years old. Citing the rock ‘n’ roll pioneer’s son, Rolling Stone magazine said Saturday the cause of death was unknown. With a distinctive voice that ranged from robust
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The post Little Richard: Founding father of rock dies at 87 appeared first on Vanguard News.

It is simply unfathomable that the National Conventional Arms Control Committee approved the export of military hardware to Turkey when that country is at war, both in Libya and in Syria.

“Not a Dirty Word”: ESMA revisits the impact of its Opinion on delegation for UK managers if there is a “hard” Brexit In the wake of the draft Agreement on the withdrawal of the UK from the EU, a speech by Steven Maijoor, th...

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One of rock 'n' roll's founding fathers, he joined the likes of Chuck Berry and Fats Domino in bringing what was once called 'race music' into the mainstream

NASHVILLE, Tenn. (AP) — Little Richard, the self-proclaimed “architect of rock ‘n’ roll” whose piercing wail, pounding piano and towering pompadour irrevocably altered popular music while introducing black R&B to white America, has died Saturday. He was 87....

German Foreign Minister Heiko Maas has warned that the risk of a hard Brexit is increasingly likely for the United Kingdom as London has so far made almost no progress in talks with the European Union (EU) on the future trade relationship, criticizing Britain for disregarding the agreed political agreement. In an interview with Augsburger Allgemeine newspaper on Saturday, the German top diplomat expressed his concern amid floundering trade talks between London...

Little Richard, who helped shape the future of rock and roll in the 1950s and 1960s, died Saturday at age 87. Rolling Stone confirmed the news of his death and reported the cause of death was unknown. Born Richard Wayne Penniman in Macon, Georgia, Little Richard was known for a series of hits that included “Tutti Frutti,” “Long Tall Sally,” “Rip It Up,” “Lucille” and “Good Golly Miss Molly.” Little Richard’s contributions to the musical world were covered by a series of greats that...

Little Richard, the flamboyant, piano-pounding showman who injected sheer abandon into rock ’n’ roll in its early days, only to abandon the music again and again because it conflicted with his religious yearnings, died Saturday. He was 87. Pastor Bill Minson, a close friend of the singer, confirmed his death to the Associated Press. Minson said he also spoke to Little Richard’s son and brother. Minson added that the family is not releasing the cause of death. In hits such as “Tutti-Frutti,” “Long Tall Sally” and “Good Golly, Miss Molly,” the singer pushed the limits of tempo and vocal intensity, creating frantic explosions of sonic confetti. His records entered a pure, primal realm that...

Little Richard, the self-proclaimed "architect of rock 'n'...

NASHVILLE (AP) — Little Richard, the self-proclaimed “architect of rock ‘n’ roll” whose piercing wail, pounding piano and towering pompadour irrevocably altered popular music while introducing black R&B to white America, has died Saturday. He was 87. Pastor Bill Minson, a close friend of Little Richard’s, told The Associated Press that Little Richard died Saturday morning. Minson said he also spoke to Little Richard’s son and brother. Minson added that the family is not releasing the cause of death. Born Richard Penniman, Little Richard was one of rock ‘n’ roll’s founding fathers who helped shatter the color line on the music charts, joining Chuck Berry and Fats Domino in...

A sea change in shopping habits amid the new coronavirus outbreak could impact marketing and distribution across the country for years to come.

Little Richard, a founding father of Rock 'n' Roll, has died at the age of 87.

Richard influenced legions of performers whose fame would eventually outstrip his own.