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Apple's overhaul of the Mac mini with M4 has been warmly received by reviewers, with many highlighting how it's one of the best values you can get right now — provided you avoid those pricey upgrades.

Apple's 2024 Mac mini stashes the power button underneath, a bold move that executives say aligns with user habits, even if it's left some fans scratching their heads.

Apple's decision to place the power button of the M4 Mac mini underneath has been questioned by users. In some cases, they've come up with their own "solutions" to the problem.

Check out the latest from Bluetti with an exclusive discount on the Elite 200 V2 portable power station capable of generating reliable 2 kWh power for 17 years.

Alcohol tore her family apart, but through turning to God a Moldovan mother finds freedom from addiction and hope of recovering her children.

Martin (Argentina) wasn’t sure whether short-term missions was his idea or God’s—until he went on an unforgettable 14-day outreach to Panama.

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OM Ships is in final preparations for the Power Up Logos Hope technical project as the four millionth visitor comes aboard in Kaohsiung, Taiwan.

OM Ships completes the ‘Power Up’ project and re-launches Logos Hope into active ministry.

On 1 July 350 teens and leaders poured into the University of Queensland, Australia, for five days of fun and discipleship.

Marc Tucker responds to Checker Finn's recent critique of the new international teacher quality study from NCEE and Linda Darling-Hammond, Empowered Educators.

Dr. Marina Mekheal, Penn State York class of 2019, recently spoke at the campus' spring 2024 commencement ceremony.

OM team member Andrea Kolln counsels a young couple struggling in their marriage and leads them to Christ.

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Vukile Property Fund plans to build more solar farms to power its malls and reduce its reliance on Eskom's power by another 5% by the end of March 2023.

Amazing things can be created when you start with small pieces and stack them together. Just ask Bryan Berg. He is the current world record holder for the tallest house of cards. This same principle can be applied to the SGPLOT and SGPANEL procedures. You can take the individual plot [...]

The post The Power of Stacking appeared first on Graphically Speaking.

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Artists, church leaders and business leaders will gather from 3-6 May for OM Arts International's first European Art Forum in Mosbach, Germany.

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India has ambitious plans to set up nuclear reactors across the country, especially in states where thermal power plants have either completed its life, or where access to coal is a challenge.

Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

India has ambitious plans to set up nuclear reactors across the country, especially in states where thermal power plants have either completed its life, or where access to coal is a challenge.

NASA’s Power to Explore Challenge calls on U.S. students to submit ideas for moon missions powered by radioisotope systems. The contest encourages kindergarten through Year 12 students to envision a mission, detail objectives, and apply their unique “power” to achieve mission success. Entries are due by January 31, 2025, and grand prize winners will tour NASA’s Glenn Research Center, gaining insight into the technology and science of space exploration.

Sewage surveillance is emerging as a crucial method in combating antimicrobial resistance (AMR), according to new research from Virginia Tech. Published in Nature Water, the study demonstrates that monitoring wastewater provides a more efficient and comprehensive approach to tracking antibiotic-resistant bacteria than testing individuals. This method holds particular promise for underserved communities, where access to healthcare is limited, and AMR-related diseases are most prevalent. The research team, led by experts such as Dr. Leigh-Anne Krometis and Dr. Marc Edwards, explored sewage samples from 62 countries and found significant correlations between AMR levels and socioeconomic factors, such as healthcare accessibility. By examining wastewater, public health officials could gain early insights into AMR spread, allowing them to take targeted actions to protect vulnerable populations. This approach could revolutionise AMR monitoring, particularly in rural and low-income areas, where AMR poses a growing threat.

Samsung Galaxy Z Flip FE is rumoured to launch next year, joining the South Korean technology conglomerate’s flagship foldable smartphone lineup as an affordable alternative to the Z Flip series model for buyers. Despite the rumour mill suggesting that it might cut down on some features in an attempt to be priced affordably, a tipster has revealed that the purported smartphone could be powered by the same Exynos processor as the flagship Galaxy S24 series.

Google is said to be working on an artificial intelligence (AI) feature that will let users get real-time responses and ask follow-up queries. As per a leak, the new feature is called conversational search, and it is being added to the Google app for Android. With this, when users ask a voice query, the app is said to show real-time responses as well as allow them to ask follow-up questions.

As the world leaders converge in the UAE for the COP28 this week to chalk out strategies for climate mitigation, Adani Power announced it has taken up a green ammonia combustion pilot project at its Mundra plant.

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Today, the Delaware Public Service Commission (PSC) released The Final Report assessing the conduct and results of Delmarva Power’s electric Standard Offer Service (SOS) reverse auction process for the 2021-2022 procurement year; the PSC was assisted by its technical consultant, Siemens PTI. Delmarva Power successfully secured all of the outstanding needs for full-requirement service for […]

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Aumento de tarifa es uno de los más grandes solicitados por la empresa El 15 de diciembre de 2022, Delmarva Power presentó una solicitud ante la Comisión de Servicios Públicos para aumentar sus tarifas de distribución eléctrica en $72,3 millones. De conformidad con la ley estatal, este aumento entrará en vigencia de manera temporal el […]

Attorney General Jennings yesterday joined the Federal Trade Commission and 16 other state attorneys general to sue Amazon.com, Inc. alleging that the online retail and technology company is a monopolist that uses a set of interlocking anticompetitive and unfair strategies to illegally maintain its monopoly power. The FTC and its state partners say Amazon’s actions […]

Read the in depth Review of Xiaomi Redmi 9 Power Mobile Phones. Know detailed info about Xiaomi Redmi 9 Power configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

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Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

Backed by Iran and hated by Israel, Hezbollah chief Hassan Nasrallah is Lebanon's most powerful man. He enjoys cult status among his Shiite supporters and holds sway over the country's institutions.

The upcoming Moto G Power 5G (2025) recently made a pit stop at the FCC where the charging speed and battery size of the phone was revealed.

The post The Moto G Power 5G (2025) was spotted at the FCC appeared first on Phandroid.

The demand for higher-performance computing is greater than ever. Cutting-edge applications in artificial intelligence (AI), big data analytics, and databases require high-speed memory systems to handle the ever-increasing volumes and complexities of data. Advancements in cloud computing and machine virtualization are stretching the limits of current capabilities. AI applications hosted in the cloud rely on fast access and reduced latency in memory systems, which is amplified by an increasing number of CPU and GPU cores.

Introducing the DDR5 Multiplexed Rank DIMM (MRDIMM), the next-generation memory module technology designed to meet the needs of high-performance computing (HPC) and AI in cloud applications. By leveraging existing DDR5 DRAM memory devices, MRDIMM modules not only double the DRAM data rate but also maintain the RAS capabilities of the industry-proven RDIMM modules, setting a new precedent for memory module performance.

Let’s compare RDIMM and MRDIMM modules using the same DRAM parts. Today, high-speed production DDR5 RDIMM modules run at 5600Mbps. Those modules use DDR5 DRAM parts, which also run at 5600Mbps. An MRDIMM module using the same DDR5 5600Mbps DRAM parts will run at a blazing 11.2Gbps.

One key metric for best-in-class performance, low bit error rate (BER), and ease of adoption is the eye diagram. The eye diagram illustrates at-speed system margin and accurately represents DDR system quality when captured with a pseudo-random binary sequence (PRBS)-like pattern. The diagram below illustrates Cadence’s 3nm silicon write eye diagram for DDR5 MRDIMM IP running at 12.8Gbps.

Cadence 3nm DDR5 MRDIMM 12.8Gbps test chip write eye diagram, design kit is available today

The eye diagram is captured using a PRBS-like pattern, incorporating a package and system board representative of a typical MRDIMM channel. Using PRBS-like patterns is crucial for capturing accurate eye diagrams. Repetitive clock-like data patterns create deceptively “open eyes” that do not reflect the real system performance. Effects like intersymbol interference, simultaneous switching, reflections, and crosstalk are not accurately reflected in the eye diagrams for parallel interfaces like DDR using non-random data streams. Relying on improperly captured eye diagrams inevitably leads to a significantly worse real system BER than conveyed by that eye diagram.

Doubling the DDR5 RDIMM data rate is challenging. Achieving high performance while optimizing for area and power requires multiple design techniques. Feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and T-coils are required to reach 12.8Gbps MRDIMM data rates in multi-channel systems. Building a production-worthy 12.8Gbps DDR5 MRDIMM IP requires engineering expertise that comes from many generations of memory interface design and production experience. Cadence has developed this expertise through multiple DDR5/4, LPDDR5X/5, and GDDR6 designs in different technology nodes and foundries. For instance, Cadence’s GDDR6 IP is available in three foundries and ten process nodes, with mass production at speeds exceeding 22Gbps.

For your next project, consider DDR5 12.8Gbps MRDIMM, a technology that not only doubles the bandwidth of DDR5 RDIMM but also promises rapid proliferation into next-generation AI, data center, HPC, and enterprise applications. With its cutting-edge capabilities, the Cadence DDR5 12.8Gbps MRDIMM IP is ready to power the future of computing.

Hi everyone. 

I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence skills.

I have some digital decision logic. Some are combinational logic, some are sequential logic that I would like to import or generate random input combination to the inputs of my decision logic to get the maximum, minimum, and average delay power dissipation and area when feeding the different input combination.

My logic has 8-bit, 16-bit, and 32-bit input. The imported data tends to be decimal numbers.

I would like to ask you:

- which tool(s) are the most appropriate to import and feed the different combination to my decision logic?

- which tool is the most appropriate to synthesis with different number of input? - I have used Genus Synthesis Solution so far. However with my skill right now I can only let Genus synthesize my Verilog code one setup at a time. I'm not sure if I there is anyway I can feed a lot of input at a time and get those results (min, max, average of delay, power dissipation and area)

- which language or scripts I should pick up to use and achieve these results?

-where can I find information to solve my problem? which information shall I look for?

Thank you so much for your time!!

Best Regards

Thermal analysis with the Cadence Celsius Thermal Solver integrated within the AWR Microwave Office circuit simulator gives designers an understanding of device operating temperatures related to power dissipation. That temperature information can be introduced into an electrothermal model to predict the impact on RF performance.(read more)

By David Vye, Senior Product Marketing Manager, AWR, Cadence When designing multi-octave high-power amplifiers, it is a challenge to achieve both broadband gain and power matching using a combination of lumped and distributed techniques. One approach...(read more)

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.(read more)

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.