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BSC Develops AI Model to Predict Stroke Risk Using Mobile Devices

Nov. 8, 2024 — Barcelona Supercomputing Center‘s Innostroke project aims to transform the prevention and monitoring of stroke, one of the leading causes of death and disability worldwide, through artificial […]

The post BSC Develops AI Model to Predict Stroke Risk Using Mobile Devices appeared first on HPCwire.




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Quantum Algorithms Institute Drives Predictive Model Accuracy with Quantum Collaboration

SURREY, British Columbia, Nov. 12, 2024 — Today, the Quantum Algorithms Institute (QAI) announced a partnership with Canadian companies, AbaQus and InvestDEFY Technologies, to solve common challenges in training machine learning […]

The post Quantum Algorithms Institute Drives Predictive Model Accuracy with Quantum Collaboration appeared first on HPCwire.




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Cognitive Behavioral Therapy Model of Perfectionism

Are you a clinician looking to master CBT for Perfectionism? Or, learn more about the CBT model of perfectionism below. CBT Model of Perfectionism Perfectionism is not the same thing as conscientiousness. For example, in a recent study of older adults, perfectionism was both associated with increased risk of mortality whereas conscientiousness was associated with […]

The post Cognitive Behavioral Therapy Model of Perfectionism appeared first on Dr Alice Boyes.




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'Pay for Success' Funding Model Focus of Policy Toolkit

The Urban Institute released a toolkit aimed at policymakers and investors interested in using private dollars to pay for public programs, such as prekindergarten.




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Multiscale Computer Model of the Spinal Dorsal Horn Reveals Changes in Network Processing Associated with Chronic Pain

Laura Medlock
Apr 13, 2022; 42:3133-3149
Systems/Circuits




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On the Role of Theory and Modeling in Neuroscience

Daniel Levenstein
Feb 15, 2023; 43:1074-1088
Viewpoints




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FAO in Review: How the Organization changed its Business Model through innovation

Read the seriesFull Article



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How Henry Ford Found the Right Tires for Model T Cars

Henry Ford was a genius who virtually created the automobile industry as we know it. But what's less lauded was his talent for publicity—and his ability to partner with other pioneers such as Ohio's Harvey Firestone.




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Is Scurvy Making a Comeback? Two Recent Cases Highlight How the Illness Can Appear in the Modern World

Scurvy diagnoses in Australia and Canada suggest doctors should consider testing for vitamin C deficiency in patients experiencing poverty, food insecurity and social isolation




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Archaeologists Discover Breathtaking Wall Paintings Frozen in Time Inside a Modest Home in Ancient Pompeii

Despite its unusually small size, the newly unearthed House of Phaedra is covered in elaborate frescos depicting mythological scenes




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How the Macy's Thanksgiving Day Parade Went From Its Modest Start to an American Tradition Rivaling Stuffing and Pumpkin Pie

A century on, the country’s most beloved Thursday spectacle reaches new heights




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How Captain George Vancouver Mapped and Shaped the Modern Pacific Northwest

The British explorer named dozens of geographical features and sites in the region, ignoring the traditions of the Indigenous peoples who’d lived there for millennia




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Swiss museum exhibit features 1820s Métis saddle alongside modern beaded items

A Métis pad saddle from the early 1800s is on display at the Cantonal Museum of Archaeology and History in Lausanne, Switzerland, sitting alongside contemporary beadwork created by other Red River Métis artists. 




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Powerful observatory camera model wins SOLIDWORKS Design Contest 2008

'One Degree Imager' will help solve the universe's deepest mysteries




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Apple Vision Pro 2 with M5 chip likely to arrive before budget models

Apple is likely to launch a refreshed Apple Vision Pro headset before a cheaper version of the product arrives, according to a new report.


An updated Apple Vision Pro could sport an M5 chip and other improvements.

Apple is believed to be working on "several ideas" for its overall Apple Vision product line and its future intentions. Currently, it is expected that an updated Apple Vision Pro will be the first, ahead of a rumored cheaper "Apple Vision" headset.

The next Apple Vision Pro would likely sport an M5 processor and other internal changes, but would otherwise be very similar to the existing model. It's expected to arrive in late 2025, reports Bloomberg, or the spring of 2026.


Rumor Score: ???? Possible


Continue Reading on AppleInsider | Discuss on our Forums




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MacBook Air 16GB models are on sale from $749.99 right now on Amazon

The lowest prices of the year are here well before Black Friday, with MacBook Air models with 16GB RAM dropping to as low as $749.99.


MacBook Air models with 16GB RAM are priced as low as $749 - Image credit: Apple

Amazon's aggressive early Black Friday deals on current MacBook Air models deliver rock-bottom pricing on specs that include 16GB unified memory.

Buy from $749.99


Continue Reading on AppleInsider | Discuss on our Forums




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Women embark on climb against modern-day slavery

Forty-five women from around the world begin their trek on 9 April to Mt. Everest Base Camp and summit of Kala Patthar Peak in Nepal.




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Can a New Political Campaign to 'Modernize' Teaching Succeed?

40 groups will band together to push principles for "modernizing and elevating" teaching, but many of the groups have contrasting agendas.




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Berks LaunchBox hosts 3D Modeling, Printing Workshop for Manufacturing. Nov. 12

The Berks LaunchBox in partnership with Penn State Berks will host its free 3D Modeling and Printing Workshop for Manufacturing Companies from 3 to 5 p.m. on Tuesday, Nov. 12, in Reading, Pennsylvania.




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Eberly College modernizes science major to reflect interdisciplinary nature

The science major in the Penn State Eberly College of Science has been renamed integrative science as part of a modern refresh to reflect its interdisciplinary nature.




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A Four-box ministry model

OM’s Arabian Peninsula field leader shares stories of ministry among Gulf Arabs using what he calls a "four-box" model.




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A Model for the Reading Crisis




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A Classroom Strategy: Using Models for Scientific Argumentation (Video)

Second grade teacher Kitten Vaa shares how her students develop argumentation skills with the use of scientific modeling.




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Scientific Modeling in the Early Grades (Video)

Kaia Tomokiyo, a kindergarten teacher from Southern Heights Elementary in Seattle and Fallon King, a 1st and 2nd grade teacher from Cedarhurst Elementary in Burien, Wash., share how they engage younger students in scientific modeling through observation and discussion.




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OpenAI’s Next Flagship AI Model Reportedly Struggling to Outperform Older Models in Certain Tasks

OpenAI is rumoured to be working on the next generation of its flagship large language model (LLM), however, it might have hit a bottleneck. As per a report, the San Francisco-based AI firm is struggling to considerably upgrade the capabilities of its next AI model, internally codenamed Orion. The model is said to be outperforming older models when it comes to language-based tasks but is underwhelming in certain tasks such as coding.




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Realme GT 7 Pro Camera Features Revealed Ahead of India Launch; to Get Underwater Photography Mode

Realme GT 7 Pro will launch in India on November 26 at 12pm IST. The phone was unveiled in China earlier this month. The Indian variant is expected to be similar to its Chinese counterpart. Now Realme has revealed several camera specifications and features of the Realme GT 7 Pro.




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Apple Vision Pro 2 to Launch Between Fall of 2025 and Spring 2026 With Same Design as Current Model: Mark Gurman

Apple unveiled its first mixed-reality headset Vision Pro at WWDC last year. Rumours about its successor have been circulating online for a while, and now Bloomberg's Mark Gurman has suggested the launch timeline for the next generation Apple Vision Pro. Gurman claims that the upcoming model will have a similar design as the current model.




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Stellar Blade to Get Nier: Automata DLC, Photo Mode and More in New Update This Month

Stellar Blade is getting a Nier: Automata DLC on November 20, developer Shift Up has announced. The game will get special items from the world of Nier Automata and an in-game shop as part of the collaboration. The update will also add a photo mode, new outfits and more features.




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Epoch AI Launches FrontierMath AI Benchmark to Test Capabilities of AI Models

Epoch AI, a California-based research institute launched a new artificial intelligence (AI) benchmark last week. Dubbed FrontierMath, the new AI benchmark tests large language models (LLMs) on their capability of reseasoning and mathematical problem-solving. The AI firm claims that existing math benchmarks are not very useful due to factors like data contamination and AI models scoring very high scores on them.




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Google DeepMind Open Sources AlphaFold 3 AI Model to Help Researchers in Drug Discovery

Google DeepMind has silently open-sourced its frontier artificial intelligence (AI) model that can predict the interaction between proteins and other molecules. Dubbed AlphaFold 3, the large language model is the successor of AlphaFold 2, whose research led to the creators of the large language model (LLM) Demis Hassabis and John Jumper getting the Nobel Prize in Chemistry in 2024.




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Vivo X200 Series Said to Launch in India Soon, But May Not Include All Models

Vivo X200, Vivo X200 Pro, and Vivo X200 Pro Mini were launched in China last month. Vivo is yet to confirm when the global launch of the trio will take place, but a latest leak suggests that their India launch will happen next month. However, the report suggests that not all Vivo X200 series will be available in India.




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Creating a Marketing Mix Model for a Better Marketing Budget: Analytics Corner

Using R programming, marketers can create a marketing mix model to determine how sustainable their audience channels are, and make better ad spend decisions. Here's how




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Getting Started with Python Integration to SAS Viya for Predictive Modeling - Comparing Logistic Regression and Decision Tree

Comparing Logistic Regression and Decision Tree - Which of our models is better at predicting our outcome? Learn how to compare models using misclassification, area under the curve (ROC) charts, and lift charts with validation data. In part 6 and part 7 of this series we fit a logistic regression [...]

Getting Started with Python Integration to SAS Viya for Predictive Modeling - Comparing Logistic Regression and Decision Tree was published on SAS Users.




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Getting Started with Python Integration to SAS Viya for Predictive Modeling - Fitting a Random Forest

Learn how to fit a random forest and use your model to score new data. In Part 6 and Part 7 of this series, we fit a logistic regression and decision tree to the Home Equity data we saved in Part 4. In this post we will fit a Random [...]

Getting Started with Python Integration to SAS Viya for Predictive Modeling - Fitting a Random Forest was published on SAS Users.




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Getting Started with Python Integration to SAS Viya for Predictive Modeling - Fitting a Gradient Boosting Model

Fitting a Gradient Boosting Model - Learn how to fit a gradient boosting model and use your model to score new data In Part 6, Part 7, and Part 9 of this series, we fit a logistic regression, decision tree and random forest model to the Home Equity data we [...]

Getting Started with Python Integration to SAS Viya for Predictive Modeling - Fitting a Gradient Boosting Model was published on SAS Users.




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Uttering Of Unpleasant Words Against Woman Not Insult To Modesty: Court

The Kerala High Court has quashed a criminal case against film director Sreekumar Menon who was accused by a prominent Malayalam actress of abusing and defaming her.




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SAS Customer Intelligence 360: Identity management, profiling and unified data model for hybrid marketing

Customer data platforms (CDPs), data management platforms (DMPs), people-based marketing, identity graphs, and more overlapping topics represent an important ingredient of any martech brainstorming session in 2020. As your brand spreads out across touchpoints — from web to mobile applications, as well as call centers, email and direct mail — [...]

SAS Customer Intelligence 360: Identity management, profiling and unified data model for hybrid marketing was published on Customer Intelligence Blog.




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Modern infrastructure must include analytics

Throughout its history, the United States has invested in infrastructure that leverages new technologies and helps society and its economy thrive. With the advent of trains in the early 1800s, four of the country’s five transcontinental railroads were built with assistance from the federal government. When cars replaced horses and [...]

The post Modern infrastructure must include analytics appeared first on Government Data Connection.




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COP29 Expected Finalise Financing Model for Developing Economies

[SAnews.gov.za] With the United Nations Framework Convention on Climate Change (COP29) taking place this week, South Africa expects the COP29 Presidency to enhance efforts to finalise the New Collective Quantified Goal on Finance (NCQG), which is a matter of great importance for developing economies.




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Clock doubler SDC modelling

Hi all,

I'm trying to model the clock of a clock doubler. The doubler consists of a delay cell and an XOR gate, which generates a pulse on both the rising and falling edge of the input clock. I've created a simple module to evaluate this. In this case, DEL1 and XOR2 are standard library cells. There is a don_touch constraint on both library cells as well as on clk_d.

module top (
input wire clk,
output reg Q);

//Doubler
wire clk_d;
wire clk_2x;
DEL1 u_delay (.I(clk),.Z(clk_d));
XOR2 u_xor (.A1(clk),.A2(clk_d),.Z(clk_2x));

//FF for connecting the clock to some leaf:
always @(posedge clk_2x) Q<=~Q;

endmodule

My SDC looks like this:

create_clock [get_ports {clk}] -name clk_i -period 100
set_clock_latency -rise 0.1 [get_pins u_xor/Z]
set_clock_latency -fall 0.4 [get_pins u_xor/Z]
create_generated_clock -name clk_2x -edges {1 1 2 2 3} -source clk [get_pins u_xor/Z]

The generated clock is correctly generated but the pulse width is zero. I would be expecting that the pulse width is the difference between fall and rise latency but is not applied:

report_clocks:

report_clocks -generated:

clk_2x is disconnected from the FF after syn_generic. What can I do to model some minimum pulse width? Will innovus later on model this correctly with the delay of DEL1?




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Modern Thermal Analysis Overcomes Complex Design Issues

Melika Roshandell, Cadence product marketing director for the Celsius Thermal Solver, recently published an article in Designing Electronics discussing how the use of modern thermal analysis techniques can help engineers meet the challenges of today’s complex electronic designs, which require ever more functionality and performance to meet consumer demand.

Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very challenging. With the recent introduction of 3D-ICs into the electronic design industry, IC vendors need to optimize the performance and cost of their devices while also taking advantage of the ability to combine heterogeneous technologies and nodes into a single package. While this greatly advances IC technology, 3D-IC design brings about its own unique challenges and complexities, a major one of which is thermal management.

To overcome thermal management issues, a thermal solution that can handle the complexity of the entire design efficiently and without any simplification is necessary. However, because of the nature of 3D-ICs, the typical point tool approach that dissects the design space into subsections cannot adequately address this need. This approach also creates a longer turnaround time, which can impact critical decision-making to optimize design performance. A more effective solution is to utilize a solver that not only can import the entire package, PCB, and chiplets but also offers high performance to run the entire analysis in a timely manner.

Celsius Thermal Management Solutions

Cadence offers the Celsius Thermal Solver, a unique technology integrated with both IC and package design tools such as the Cadence Innovus Implementation System, Allegro PCB Designer, and Voltus IC Power Integrity Solution. The Celsius Thermal Solver is the first complete electrothermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Based on a production-proven, massively parallel architecture, the Celsius Thermal Solver also provides end-to-end capabilities for both in-design and signoff methodologies and delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

By combining finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids (both liquid and gas, as well as airflow), designers can perform complete system analysis in a single tool. For PCB and IC packaging, engineering teams can combine electrical and thermal analysis and simulate the flow of both current and heat for a more accurate system-level thermal simulation than can be achieved using legacy tools. In addition, both static (steady-state) and dynamic (transient) electrical-thermal co-simulations can be performed based on the actual flow of electrical power in advanced 3D structures, providing visibility into real-world system behavior.

Designers are already co-simulating the Celsius Thermal Solver with Celsius EC Solver (formerly Future Facilities’ 6SigmaET electronics thermal simulation software), which provides state-of-the-art intelligence, automation, and accuracy. The combined workflow that ties Celsius FEA thermal analysis with Celsius EC Solver CFD results in even higher-accuracy models of electronics equipment, allowing engineers to test their designs through thermal simulations and mitigate thermal design risks.

Conclusion

As systems become more densely populated with heat-dissipating electronics, the operating temperatures of those devices impact reliability (device lifetime) and performance. Thermal analysis gives designers an understanding of device operating temperatures related to power dissipation, and that temperature information can be introduced into an electrothermal model to predict the impact on device performance. The robust capabilities in modern thermal management software enable new system analyses and design insights. This empowers electrical design teams to detect and mitigate thermal issues early in the design process—reducing electronic system development iterations and costs and shortening time to market.

To learn more about Cadence thermal analysis products, visit the Celsius Thermal Solver product page and download the Cadence Multiphysics Systems Analysis Product Portfolio.




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Aligning Components using Offset Mode in Allegro X APD

Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available.

Follow these steps to Align Components using Offset Mode:

  1. Set Application Mode to Placement Edit.
  2. Drag the components that need to be aligned and right-click and choose Align Components.
  3. Now, in the Options tab, you will notice Spacing Section with Equal Offset. You can equally and individually offset the components by using the +/- buttons for increment or decrement.




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Wild River Collaborates with Cadence on CMP-70 Channel Modeling

Wild River Technology (WRT), the leading supplier of signal integrity measurement and optimization test fixtures for high-speed channels at data rates of up to 224G, has announced the availability of a new advanced channel modeling solution that helps achieve extreme signal integrity design to 70GHz. Read the press release. The CMP-70 program continues the industry-first simulation-to-measurement collaboration with Cadence that was initially established with the CMP-50. Significant resources were dedicated to the development of the CMP-70 by Cadence and WRT over almost three years. The CMP-70 will be on display at DesignCon 2025 , January 28-30, in Cadence booth 827 to benchmark the Cadence Clarity 3D Solver . “I am not a fan of hype-based programs that simply get attention,” remarked Alfred P. Neves, WRT’s co-founder and chief technical officer. “Both Cadence and Wild River brought substantial skills to the table in this project as we continued our industry-first simulation-to-measurement collaboration. The result is a proven, robust and accurate platform that brings extreme signal integrity to 70GHz designs. This application package has also been instrumental in demonstrating the robust 3D EM simulation capability of the Cadence Clarity solver.” “We’re delighted to continue the joint development and validation program with WRT that started with the CMP-50,” said Gary Lytle, product management director at Cadence. “The skilled and experienced signal integrity technologists that both companies bring to the program results in a superior signal integrity solution for our mutual customers.” CMP-70 Solution Features The solution is available both in a standard configuration and as a custom solution for customer-specific stackups and fabrication. The primary target application is to support a 3D EM solver analysis modeling versus the time- and frequency-domain measurement methodologies. The solution features include: The CMP-70 platform, assembled and 100% TDR NIST traceable tested, with custom stands Material Identification overview web-based meeting including anisotropic 3D material identification A cross-section PCB report and structures for using as-fabricated geometries Measured S-parameters, pre-tested for quality (passivity/causality and resampled for time domain simulations) A host of novel crosstalk structures suited for 112G HD level project analysis PCB layout design files (NDA required) An EDA starter library including loss models with industry-first accurate surface roughness models Comprehensive training available for 3D EM analysis – correspondence, material ID in X-Y and Z axis for a host of EDA tools Industry-First Hausdorff Technique The WRT application package also includes an industry-first modified Hausdorff (MHD) technique , included as MATLAB code. This algorithmic approach provides an accurate way to compare two sets of measurements in multi-dimensional space to determine how well they match. The technique is used to compare the results simulated by the Clarity solver with those measured on the CMP-70 platform. The methodology and initial results are shown in the figure below, where the figure of merit (FOM) is calculated from 10, 35, and finally to 50GHz. The MHD algorithm requires a MATLAB license, but WRT also accommodates customer data as another option, where WRT provides the comparison between measured and simulated data. Additional Resources If you are attending DesignCon 2025 , be sure to stop by Cadence booth 827 to see WRT’s CMP-70 advanced channel modeling solution in action with the Clarity 3D Solver. Check out our on-demand webinar, " Validating Clarity 3D Solver Accuracy Through Measurement Correlation ." Learn more about the CMP-70 solution and the Clarity 3D Solver . For more information about Cadence’s full suite of integrated multiphysics simulation solutions, download our Multiphysics System Analysis Solutions Portfolio .




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Versatile Use Case for DDR5 DIMM Discrete Component Memory Models

DDR5 DIMM Architectures The DDR5 generation of Double Data Rate DRAM memories has experienced rapid adoption in recent years. In particular, the JEDEC-defined DDR5 Dual Inline Memory Module (DIMM) cards have become a mainstay for systems looking for high-density, high-bandwidth, off-chip random access memory[1]. Within a short time, the DIMM architecture evolved from an interconnected hierarchy of only SDRAM memory devices (UDIMM[2]) to complex subsystems of interconnected components (RDIMM/LRDIMM/MRDIMM[3]). DIMM Designs and Popular Verification Use Cases The growing complexity of the DIMMs presented a challenge for pre-silicon verification engineers who could no longer simply validate against single DDR5 SDRAM memory models. They needed to consider how their designs would perform against DIMMs connected to each channel and operating at gigahertz clock speeds. To address this verification gap, Cadence developed DDR5 DIMM Memory Models that encapsulated all of the architectural complexities presented by real-world DIMMs based on a robust, easy-to-use, easy-to-debug, and easy-to-reconfigure methodology. This memory-subsystem-in-a-single-instance model has seen explosive adoption among the traditional IP Developer and SOC Integrator customers of Cadence Memory Models. The Cadence DIMM models act as a single unit with all of the relevant DIMM components instantiated and interconnected within, and with all AC/Timing parameters among the various components fully matched out-of-the-box, based on JEDEC specifications as well as datasheets of actual devices in the market. The typical use-case for the DIMM models has been where the DUT is a DDR5 Memory Controller + PHY IP stack, and the validation plan mandated compliance with the JEDEC standards and Memory Device vendor datasheets. Unique Use Case for the DIMM Discrete Component Models Although the Cadence DIMM models have enjoyed tremendous proliferation because of their cohesive implementation and unified user API, the actual DIMM Models are built on top of powerful, flexible discrete component models, each of which was designed to stand on its own as a complete SystemVerilog UVM-based VIP. All of these discrete component models exist in the Cadence VIP Catalog as standalone VIPs, complete with their own protocol compliance checking capabilities and their own configuration mappings comprehensively modeling individual AC/Timing parameters. Because of this deliberate design decision, the Cadence DIMM Discrete Component Models can support a unique use-case scenario. Some users seek to develop IC Designs for the various DIMM components. Such users need verification environments that can model the individual components of a DIMM and allow them the option to replace one or another component with their Component Design IP. They can then validate that their component design is fully compatible with the rest of the components on the DIMM and meets the integrity of the overall DIMM compliance with JEDEC standards or Memory Vendor datasheets. The Cadence Memory VIP portfolio today includes various examples that demonstrate how customers can create DIMM “wrappers” by selecting from among the available DIMM discrete component models and “stitching” them together to build their own custom testbench around their specific Component Design IP. A Solution for Unique Component Scenarios The Cadence DDR5 DIMM Memory Models and DIMM Discrete Component Models can provide users with a flexible approach to validating their specific component designs with a fully populated pre-silicon environment. Augmented Verification Capabilities When the DIMM “wrapper” model is augmented with the Cadence DFI VIP[4] that can simulate an MC+PHY stack and offers a SystemVerilog UVM test API to the verification engineer, the overall testbench transforms into a formidable pre-silicon validation vehicle. The DFI VIP is designed as a combination of an independent DFI MC VIP and a DFI PHY VIP connected to each other via the DFI Standard Interface and capable of operating seamlessly as a single unit. It presents a UVM Sequence API to the user into the DFI MC VIP with the Memory Interface of the PHY VIP connected to the DIMM “wrapper” model. With this testbench in hand, the user can then fully take advantage of the UVM Sequence Library that comes with the DFI VIP to enable deep validation of their Component Design inside the DIMM “wrapper” model. Verification Capabilities Further Enhanced A possible further enhancement comes with the potential addition of an instance of the Cadence DIMM Memory Model in a Passive Monitor mode at the DRAM Memory Interface. The DIMM Passive Monitor consumes the same configuration describing the DIMM “wrapper” in the testbench, and thus can act as a reference model for the DIMM wrapper. If the DIMM Passive Monitor responds successfully to accesses from the DFI VIP, but the DIMM wrapper does not, then it exposes potential bugs in the DUT Components or in the settings of their AC/Timing parameters inside the DIMM wrapper. Debuggability, Interface Visibility, and Protocol Compliance One of the key benefits of the DIMM Discrete Component Models that become manifest, whether in terms of the unique use-case scenario described here, or when working with the wholly unified DDR5 DIMM Memory Models, is the increased debuggability of the protocol functionality. The intentional separation of the discrete components of a DIMM allows the user to have full visibility of the memory traffic at every datapath landmark within a DIMM structure. For example, in modeling an LRDIMM or MRDIMM, the interface between the RCD component and the SDRAM components, the interface between the RCD component and the DB components, and the interface between the SDRAM components and the DB components—all are visible and accessible to the user. The user has full access to dump the values and states of the wire interconnects at these interfaces to the waveform viewer and thus can observe and correlate the activity against any protocol violations flagged in the trace logs by any one or more of the DIMM Discrete Component Models. Access to these interfaces is freely available when using the DIMM Discrete Component Models. On the unified DDR5 DIMM Memory Models, a feature called Debug Ports enables the same level of visibility into the individual interconnects amidst the SDRAM components, RCD components, and DB components. When combined with the Waveform Debugger[5] capability that comes built-in with the VIPs and Memory Models offered by Cadence and used with the Cadence Verisium Debug[6] tool, the enhanced debuggability becomes a powerful platform. With these debug accesses enabled, the user can pull out transaction streams, chip state and bank state streams, mode register streams, and error message streams all right next to their RTL signals in the same Verisium Debug waveform viewer window to debug failures all in one place. The Verisium Debug tool also parses all of the log files to probe and extract messages into a fully integrated Smart Log in a tabbed window fully hyperlinked to the waveform viewer, all at your fingertips. A Solution for Every Scenario Cadence's DDR5 DIMM Memory Models and DIMM Discrete Component Models , partnered with the Cadence DFI VIP, can provide users with a robust and flexible approach to validating their designs thoroughly and effectively in pre-silicon verification environments ahead of tapeout commitments. The solution offers unparalleled latitude in debuggability when the Debug Ports and Waveform Debugger functions of the Memory Models are switched on and boosted with the use of the Cadence Verisium Debug tool. [1] Shyam Sharma, DDR5 DIMM Design and Verification Considerations , 13 Jan 2023. [2] Shyam Sharma, DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM) , 23 Sep 2024. [3] Kos Gitchev, DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers , 26 Aug 2024. [4] Chetan Shingala and Salehabibi Shaikh, How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device? , 29 Mar 2022. [5] Rahul Jha, Cadence Memory Models - The Gold Standard , 15 Apr 2024. [6] Manisha Pradhan, Accelerate Design Debugging Using Verisium Debug , 11 Jul 2023.




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LM117 Spice Model

I am looking for LM117 Pspice model. Can someone send me the file. Thank you




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How to design enhancement mode eGaN (EPC8002) switch in cadence

Hi,

I need to design EPC8002 eGaN switch in cadence. Can someone provide me step by step guide on hoe to add EPC8002 into my cadence. I am working on BCD180.

Thank you 

Ihsan




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Specman Mode for Emacs

Attached is the latest emacs mode for e/Specman - version 1.23


Please follow the install instructions in the top section of the actual file
(after unzipping it) to install/load this package with your emacs.




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Overcoming Thermal Challenges in Modern Electronic Design

Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more)