Additionally, Workplace Safety Program eligibility changes will help more companies stay safe and save money Insurance Commissioner Trinidad Navarro announced today that workers’ compensation insurance rates will decrease for the eighth year in a row, effective December 1. The voluntary market is expected to decrease average loss costs by 8.4%, and the residual market will […]

The Delaware Department of Transportation’s (DelDOT) “Name That Plow Contest” returns for its fourth year! As winter approaches, we are excited to host this contest again and give kids (K-5) across Delaware the opportunity to name some of our snowplows. There were over 200 entries last year and the winning names were Ice Ice Bladey, […]

Delaware is experiencing dry conditions with an open burning ban in effect.

Beach-nesting piping plovers – a federally-listed threatened species and Delaware state-listed endangered species – experienced a decrease in adult pair numbers but increased nesting success in Delaware during 2024.

Attorney General Kathy Jennings has secured a six-month suspension from a former Delaware investment adviser for viewing current financial account information of former Delaware clients while unregistered. The Investor Protection Unit (the “Unit”), the state securities regulator for Delaware, received a complaint from a former client of Robert Brandon Prettyman, an unregistered investment advisor that the Unit had previously suspended for making false statements […]

Kindergarteners across Delaware are participating in the Kindergarten Oral Health Screening Program for the first time this school year, provided by the Bureau of Oral Health and Dental Services (BOHDS) within the Delaware Division of Public Health (DPH). This new annual program is intended to improve the oral health of Delaware children and prepare them for […]

Attorney General Kathy Jennings today joined a coalition of 50 states and territories announcing two significant cooperation agreements and settlements with Heritage Pharmaceuticals and Apotex totaling $49.1 million to resolve allegations that both companies engaged in widespread, long-running conspiracies to artificially inflate and manipulate prices, reduce competition, and unreasonably restrain trade with regard to numerous generic prescription […]

The Delaware Department of Transportation (DelDOT) announces that Moody’s Investors Service, Inc. has assigned an Aaa rating to the Delaware Transportation Authority, their highest rating, and S&P Global Ratings assigned its second highest rating of AA+ long-term rating to the department’s $150.5 million series 2024 transportation system senior revenue bond sale that will be issued […]

DEPARTMENT OF JUSTICE: Fraud and Consumer Protection Division

Read the in depth Review of AMD Ryzen 9 3900XT Desktop Processor PC Components. Know detailed info about AMD Ryzen 9 3900XT Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of AMD Ryzen 9 5950X Desktop Processor PC Components. Know detailed info about AMD Ryzen 9 5950X Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Intel Core i9-11900K Desktop Processor PC Components. Know detailed info about Intel Core i9-11900K Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of AMD Ryzen 7 5700G Desktop Processor PC Components. Know detailed info about AMD Ryzen 7 5700G Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of AMD Ryzen 9 7950X Desktop Processor PC Components. Know detailed info about AMD Ryzen 9 7950X Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Intel Core i9-13900K Desktop Processor PC Components. Know detailed info about Intel Core i9-13900K Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of AMD Ryzen 9 7900 Desktop Processor PC Components. Know detailed info about AMD Ryzen 9 7900 Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of AMD Ryzen 9 7950X3D Desktop Processor PC Components. Know detailed info about AMD Ryzen 9 7950X3D Desktop Processor configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

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A man climbed an electric tower in Uttar Pradesh's Noida Sector 76 on Sunday afternoon. After nearly two hours, he was brought down by the police and fire department officials.

A body of a man has been found in a plastic bag in seven pieces on Mumbai's Gorai beach, the police said today.

Founded in 1868, Tatas have become one of largest and most diverse global conglomerates. It is a name heard in almost every home in India and tens of millions overseas.

Samsung is running some Black Friday deals for its foldables like the Galaxy Z Fold 6 and Flip 6, so what are you waiting for?

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Samsung has an early Black Friday deal for its accessories and wearables, so don’t miss out if you want some savings!

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If you're an iPhone user, then you might want to check the Chrome app for new updates.

The post Google Adds Some Nifty Features for Chrome on iOS Devices appeared first on Phandroid.

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

I'm trying to do what I believe should be a very simple and straightforward thing but after much reading appears to be quite complicated.

I'm test-benching the digital portion of a mixed-signal circuit that's instantiated a few hundred times. Each instance has some digital controls, and an analog portion. To greatly speed up the simulation, I'd like to hide the analog portion, which is neatly contained in one or two cell views deep down the hierarchy, and then unhide it after simulation has ended so it doesn't mess up other peoples' sims

Just as an example, say there's an op-amp that from the top level is contained in instance "I<0:511>/I3/I15/I0". First off, I don't know how to iterate through the 512 instantiations of the top level cell, but let's say we're just working with the I0 instance. I thought it would just be

schIgnore(?objectId "I<0:511>/I3/I15/I0" ?setIgnore t)

Of course this doesn't work. I can get the top level cell dbId with

cv = dbOpenCellViewByType("library" "cell" "schematic" "" "a")

And then I can grab the instance ID with

inst = dbFindAnyInstByName(cv "I0")

This gives me something, but then I'm lost from here. If I use the ~>master to get an Id from inst, I cannot recursively use dbFindAnyInstByName to traverse down the hierarchy. Also the value this returned seems to be meaningless, it can't be used by the schIgnore command. I'm not sure what the schIgnore command is actually even looking for.

So I guess I'm trying to loop through two things, one is to traverse down the hierarchy and grab the ID of a child instance so I can schIgnore it, and another is to iterate through all the top level instances to hide the child instance within each of them.

Hi,

My query is regarding importing of layout.

After importing, we see that the imported transistor instances and vias are all referring to the library in which they are imported, instead of referring to the technology library.

Please let me know how we can refer them to the technology library.

Will surely provide more details if my query is unclear.

Thanks,

Mallikarjun.

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog covers the user interface (UI) and simulation considerations designers should note prior to starting a design.(read more)

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog, part 2, covers the layout and component library considerations designers should note prior to starting a design.(read more)

Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup?   

Starting SPB 23.1, a handy feature Transmission Line Calculator, is built into Allegro X Advanced Package Designer (Allegro X APD). This feature will require either an SiP Layout license or can be accessed through SiP Layout Bundle. 

From the Analyze dropdown menu in the 23.1 Allegro X APD toolbar, you can choose Transmission Line Calculator. 

You can use this calculator to help decide constraints and stackup for laminate-based PCB or Packages. You can calculate the correct stackup material and width/spacing to meet any requirements that may be later entered in a constraint. This is truly a calculated number and not a true field solver. 

The different types of calculations that the Transmission Line Calculator can provide are Microstrip, Embedded microstrip, Stripline, CPW (Coplanar), FGCPW (frequency-dependent Coplanar), Asymmetric stripline, Coupled microstrip (Differential Pair), Coupled stripline (Differential Pair), and Dual striplines. 

This feature is important for customers relying on fabricators/spreadsheets to provide this information or need to test a quick spacing/width as per the impedance value. 

Let us know your comments on this new feature in 23.1 Allegro X APD. 

Verisium Debug, the Cadence unified debug platform, offers a variety of debugging capabilities, including RTL debug, UVM testbench debug, UPF debug, and DMS debug. From IP to SoC level debug, the user can take the benefits of the rich debugging features to reduce the time for debug.

Not only the common and advanced debug features, Verisium Debug also provides Python-based interface API, which enables capabilities allowing users to customize functions with Verisium Debug Python API to access from design, waveform databases and add functions to Verisium Debug’s GUI for visualization purposes. With Verisium Debug’s Python API, users can turn repetitive works into automatic programs or reduce efforts to create in-house utilities with well-established infrastructure from Verisium Debug.

Here is an example of how the user uses Python API to create a customized function. Users can write a Python program to extract signals in a specific design scope and report the values of the extracted signals. From Fig 1., you can understand the procedure of the traversal steps.

1. Import Python library in Verisium Debug package.
2. Setup the database for traversal.
3. Search the scope with the hierarchy information in the design DB.
4. Query the signal list and the values of the signals.
5. Print out the results.

Fig 1. Procedure of Verisium Debug Python Program

The result from the Verisium Debug Python App can be used for post-process design checking or fed into other utilities in the design flow.

The concept is very straightforward. With Verisium Debug and the Python API environment enabled, you can easily query any information that is stored in the databases of Verisium Debug. The result can be outputted in text format, or you can also use the API to display the results back to Verisium Debug’s GUI.

The Verisium Debug Python API is an important capability and resource for Verisium Debug users. To make Verisium Debug Python API easier to access, from Verisium Debug 24.10 release, Verisium Debug introduced the new Verisium Debug Python App Store.

Fig 2. Verisium Debug App Store

The Python App Store includes ready-to-use Python App examples with the availabilities of original source code documents, which help the user to understand how to start writing an app that fits their use case.

Fig 3. Example apps in Verisium Debug App Store

The Verisium Debug Python App Store can also be used by a team as an app management system. App creators can share the developed apps across teams within their companies. The in-house created apps will become easy to manage, and engineers can easily access the apps from the central location, which makes it possible for users to see the updated available Verisium Debug Apps from the Verisium Debug App Store.

Check the following videos for more information about Verisium Debug Python API:

Customize Verisium Debug with Python API

Verisium Debug Customized Apps with Python API

Celebrated for their unparalleled engineering expertise and pioneering mindset, McLaren stands at the forefront of innovation. Theirs is a story of engineering excellence, a symphony of speed driven by the relentless pursuit of aerodynamic perfection. In 2022, Cadence was named an Official Technology Partner of the McLaren Formula 1 Team. The multi-year partnership between McLaren and Cadence has helped redefine the boundaries of what’s possible in Formula 1 aerodynamics. Shaving off a fraction of a second per lap can make all the difference in a podium finish, and track conditions bring layers of complexity to the design process. That’s where Cadence steps in with Fidelity CFD Software. The Cadence Fidelity CFD software is a comprehensive suite of computational fluid dynamics (CFD) solutions. Access to this solution allows the McLaren F1 team to accelerate their CFD workflow, enabling them to assess designs faster and more precisely. It also allows them to investigate airflows and tackle design projects that require advanced compute power and precision. With Fidelity Flow’s solver capabilities and Python-driven automation, Cadence’s CFD software aids the advancement of aerodynamic simulations that go into McLaren’s F1 cars. With a customized, high-quality, multi-block meshing strategy and optimized workflow, Fidelity CFD makes design exploration more automated, thereby helping establish a strong foundation for McLaren’s future success on the track. Lando Norris, F1 driver for McLaren, said, “As a driver, I saw the impact of every decision made in the design room in every simulation run. The work on aerodynamics directly translates to the confidence I have on track, the grip in every turn, and the speed on every straight. This partnership, this technology, is what will give us the edge. It's not just about battling opponents; it's about mastering the airflow around the car in every driving condition on every track.” If you’re interested in learning more about the importance of CFD in McLaren’s racing success, be sure to attend our upcoming webinar, “CFD and Experimental Aerodynamics in McLaren F1 Engineering.” Christian Schramm, McLaren’s director of advanced projects, and Cadence’s Benjamin Leroy will be the main speakers for the event. Register today to secure your spot! For more insights on the Formula 1 car design process, take a look at the case study, “ McLaren Formula 1 Car Aerodynamics Simulation with Cadence Fidelity CFD Software .” Learn more about how McLaren and Cadence are engineering success . “Designed with Cadence” is a series of videos that showcases creative products and technologies that are accelerating industry innovation using Cadence tools and solutions. For more Designed with Cadence videos, check out the Cadence website and YouTube channel .

An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want to quantify the impact of the number of cores, local memory size, system memory latency, and interconnect bandwidth. Software teams wish to have a practical development platform that is not excruciatingly slow. This blog shares a recipe for simulating Cadence DSPs in a multi-core design as separate x86 processes. The purpose is to reduce simulation time for customers with simple multi-core models where cores interact only through shared memory. It uses a Vision Q8 multi-core design to share details of the XTSC (Xtensa SystemC) model, software application, commands, and debugging. Note the details shared are for a simulation run on an Ubuntu Linux machine, Xtensa tools version RI-2023.11, and core configuration XRC_Vision_Q8_AODP. Complex vs. Simple Model A complex model (Figure 1) is one in which one core accesses another core's local memory, or there are inter-core interrupts. Simulation runs as a single x86 process. Figure 1 A simple model (Figure 2) is one in which cores interact only through shared memory. Shared memory is a file on the Linux host. Figure 2 Multiple x86 Process – Simple Model As depicted in Figure 3, each core is simulated using a separate x86 process. Cores use barriers and locks placed in shared memory for synchronization and data sharing. Locks are placed in un-cached memory that support exclusive subordinate access. The XTSC memory component, xtsc_memory , supports exclusive subordinate access. Cadence software tools provide a way to define memory regions as cached or uncached. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK . Figure 3 Demo Application A demo application performs a 128x128 matrix multiplication. Work is divided so that each of the 32 cores computes four rows of the 128x128 result matrix. Cores use barriers to synchronize. Cadence tools provide APIs for synchronization and locking. Please refer to Cadence's System Software Reference Manual for more details. Note without a higher-level lock, prints from all cores will get mixed up. Therefore, in the demo application, only core#0 prints. SystemC Simulation The following sample command runs the 32-core simulation in such a way that each core is a separate x86 process. It runs a matrix multiplication application in cycle-accurate mode with logging off. >>for (( N=0; N >xtsc-run -define=NumCores=32 -define=N=0 -define=LOGGING=0 -define=TURBO=0 --xxdebug=sync -i=coreNN.inc -sc_main=sc_main.cpp -no_sim Modify the sc_main.cpp generated for core#0 to create a generic sc_main.cpp to build a single simulation executable for all cores. The Xtensa SDK includes Makefile targets to build custom simulations. By default, the simulation runs in cycle-accurate mode. Fast functional (Turbo) mode provides additional improvement over cycle-accurate mode. Note that the fast functional mode has an initialization phase, so gains are visible only when running an application with longer run times. Simulation Wall Time The table captures simulation wall time improvements. Note that these are illustrative wall time numbers. Actual wall time numbers and improvements will depend on your host machine's performance and your application. Simulation Type Wall Time Comments Single process cycle accurate mode 17500 seconds Multiple x86 processes cycle accurate mode 1385 seconds 12X faster than single process Multiple x86 processes turbo mode 415 seconds 3X faster than cycle accurate mode Debugging Attaching a debugger to each of the individual x86 core simulation processes is possible. Synchronous stop/resume and core-specific breakpoints are also supported. Configure the Xplorer launch configuration and attach it to the running simulation processes as follows (Figure 5) Figure 5 Figure 6 shows 32 debug contexts. Figure 6 As shown, using Xtensa SDK, you can create a multi-core simulation that functions as a practical software development platform. Please visit the Cadence support site for information on building and simulating multi-core Xtensa systems.

Hello,

I'm reading the Design specification for IP6514E.

We will use the DAC mode.

It would seem to be very simple but I don't see any code sequence, i.e.

  1.Write 03(Basic Read) to this register

  2, Write start adress to this register

  3. Write "execute" to this register

  4. Read the data from this register

Thanks,

Stefan

I have tried replicating the setup described in a previous post (here), with the proposed solution.

The MDL measurements return a value of 0 for all exported result but the first.

Using Viva I can actually see the correct value for each contribution.

I am using :
- Spectre 23.1.0.538.isr10
- Viva IC23.1-64b.ISR8.40

What should I do differently?

Thanks!

**** test.measure ****

Measurement Name   :  noi_test
Analysis Type      :  noise
noi_total             =  6.9282e-06
r1_flicker            =  0
r1_thermal            =  0
r1_total              =  0
r2_flicker            =  0
r2_thermal            =  0
r2_total              =  0

Hi,

Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? 

Cheers,

Antonio

Dr Samir Hamrouni, CEO of the World Free Zones Organization, outlines the attributes that are essential to flourishing free zones.

Stevens Mokgalapa talks about foreign investment opportunities and challenges in South Africa’s administrative capital, and the balancing act of development and environmental needs in the developing world.

Up to 18 countries across Latin America have joined China’s new Belt and Road Initiative, hoping to boost their infrastructure development and investment.  

Embodied by its huge historic port and diverse population, Antwerp has long embraced globalisation. Renewed impetus from stakeholders across Belgium’s second most populous city is ensuring ample opportunities for foreign investors.

Over the past three years, the UK has led Europe for financial services FDI, with the US as top investor. Emma McCoy reports.

The Egyptian capital Cairo led Africa in 2018, attracting 10 foreign business services investment projects, in its strongest performance since 2012. Joshua Crawford reports.

Israel Aerospace Industries (IAI) has entered into a joint venture with Australia’s Bis to launch Auto-mate, a new company that will provide autonomous systems to the mining industry.

Australia’s demand for cyber services has prompted PwC Australia to open a new onshore delivery centre in Adelaide, South Australia.

The US has granted new market access for Australian roasted macadamia nuts.

New rule changes mean Australian dairy establishments exporting to Chile will no longer be required to undergo periodic in-country audits by Chilean officials.