Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution....

[[ Click on the title to access the full blog on the Cadence Community site. ]]

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Cadence has a new white paper out on Computational Software . I've written on these topics in Breakfast Bytes, most recently in the posts: Computational Software System Analysis: Computational...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out on the full speed-up potential that Palladium can provide.

Altair’s HERO is here for you. With its help, your Palladium unit can be even more amazing for your productivity than before.

HERO (that’s Hardware Emulator Resource Optimizer) adds emulator support to Altair’s Accelerator. You already know and love Altair’s scheduling tools; so why not make them do more for you, so you can be one of those people who are making the most out of their Palladium system?

Emulators are kind of like big computers, but it’s a lot harder to manage leftover resources on an emulator than it is on, say, a CPU. A scheduler like HERO neatly sidesteps this problem by more intelligently using the resources available to ensure that there’s a minimal patchwork of leftover resources to begin with.

HERO supports past generations of Palladium as well, so if you’re still using an older version, you can still take advantage of the upgrades HERO provides. There’s a wide variety of features HERO has that make your emulator easier to use. HERO separates a job into a “select” section and a “run” section: the “select” part makes a last-minute decision on which domains or boards to use, while the “run” part is the actual job. This makes it easier to ensure that your Palladium emulator is being used as efficiently as possible. Jobs are placed using “shapes”, which are a set of job types; these can be selected from a list of pre-defined ones by the user. Shapes can have special constraints if those are needed.

A new reservation system also helps HERO organize Palladium’s processing power better. HERO offers both “hard” reservations and “soft” reservations. A hard reservation locks other users out of reserving any part of the emulator at all, while a soft reservation allows a user to reserve a part of the emulator for a later use. Think of it like this: a soft reservation is like grabbing a ticket from the deli counter, while a hard reservation stops you from ever entering the market.

When using HERO, you can manage your entire verification workload. You’ll find that your utilization of your emulator vastly increases—it’s been reported that some users using only 30% of the capabilities of their Palladium unit(s) saw a massive increase to over 90% once they made the switch to HERO.

If you’re ready to take your Palladium productivity to the next level, Altair has a HERO for you.

To see the full presentation given by Andrea Casotto in the Cadence Theater at DAC 2019, check here.

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)

The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program. Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done and is in the past now.

There is a Chinese saying "好事多磨" which means "good things take time to happen." I forgot the exact time when I first joined the working group for the new standard -- about two and half years ago -- but I do remember long hours of meetings and many "lively" debates and discussions. Since the "hard time" has passed us, I would like to share some fun facts about the working group and the standard.

• The 1801 working group is the largest entity based ballot group in IEEE-SA history.
• The new standard was initially planned for 2012, but was delayed purely due to the large amount of work required.
• At one point, the group was debating on whether the new standard should be called UPF 2.1 or 3.0. It may sound weird now but we spent quite some time discussing this. Eventually we settled on 2.1 as it was the original plan.
• The 1801-2013 document has 358 pages which is 53% thicker than previous version (the sheer amount of changes in the new standard indicate that this is more than just a normal incremental update of the previous version as suggested by naming it 2.1)
• Around 300 real issues were reported over the previous version and a majority of them were fixed in the new release.
• This is the first release with constructs and semantics coming from Common Power Format (CPF), a sign of convergence of the two industry leading power formats.
• There are about 100 working group meetings in my Outlook calendar since 2011, with meeting times ranging from 2 hours to 8 hours.
• We extensively used Google Drive (which was called Google Docs when the working group started), a great tool for productivity. I cannot imagine how any standard could have been done before Google existed!

Personally, I had an enjoyable journey, especially from having the privilege to work with many industry experts who are all passionate about low power. I do have one more thing to share though. My older daughter went from middle school to high school during the period of the development of the new standard. Since most of the meetings took place in the early morning California time, she had to endure the pain of listening to all these discussions on power domain, power switches, etc. on her way to school.

I asked her if she learned anything. She told me that other than being able to recognize the voices of Erich, John and Joe on the line, she also learned that she would never want to become an electrical or computer engineer! She was so happy that the meetings stopped a couple of months ago. But what I did not tell her is that the meetings will resume after DAC! Well, I am sure this will be a big motivation for her to get her own driving license in the summer.

If you want to get some quick technical insights into the new standard, check out my recent EE Times article IEEE 1801-2013: A bold step towards power format convergence.

Qi Wang

DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921.

For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for:

• The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week!
• A sneak preview of the eBook version of the Mixed-signal Methodology Guide
• Customer presentations at the Cadence DAC Theater
  • 9am, Tuesday, June 4  ARM  Low-Power Verification of A15 Hard Macro Using CLP 
  • 10:30am, Tuesday, June 4  Silicon Labs  Power Mode Verification in Mixed-Signal Chip
  • 12:00pm, Tuesday, June 4  IBM  An Interoperable Flow with Unified OA and QRC Technology Files
  • 9am, Wednesday, June 5  Marvell  Low-Power Verification Using CLP
  • 4pm, Wednesday, June 5  Texas Instruments  An Inter-Operable Flow with Unified OA and QRC Technology Files
• Partner presentations at the Cadence DAC Theater
  • 10am, Monday, June 3  X-Fab  Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
  • 3:30pm, Monday, June 3  TSMC TSMC Custom Reference Flow for 20nm -  Cadence Track
  • 9:30am,Tuesday, June 4  TowerJazz   Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow
  • 12:30pm, Wednesday, June 5  GLOBALFOUNDRIES  20nm/14nm Analog/Mixed-signal Flow
  • 2:30pm, Wednesday, June 5  ARM  Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications
• Technology sessions at suites
  • 10am, Monday, June 3    Low-power Verification of Mixed-signal Designs
  • 2pm, Monday, June 3      Advanced Implementation Techniques for Mixed-signal Designs
  • 2pm, Monday, June 3      LP Simulation: Are You Really Done?
  • 4pm, Monday, June 3      Power Format Update: Latest on CPF and IEEE 1801  
  • 11am, Wednesday, June 5   Mixed-signal Verification
  • 11am, Wednesday, June 5   LP Simulation: Are You Really Done?
  • 4pm, Wednesday, June 5   Successful RTL-to-GDSII Low-Power Design (FULL)
  • 5pm, Wednesday, June 5   Custom/AMS Design at Advanced Nodes

We will also have three presentations at the Si2 booth (#1427):

• 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
• 11:30am, Tuesday, June 4   Low-power Verification for Mixed-signal Designs Using CPF
• 10:30am, Wednesday, June 5   System-level Low-power Verification Using Palladium

We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC!     

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Hello, i need to test the  parameter Kf under some conditions in subthreshold.i cannot just plot the OP param,becasue i need to derive it under certain conditions.

Spectre(of Cadence) like BSIM(of Berkley) has developed a method for deriving each parameter in their model.

Is there a way to help me with such manual where i can test in cadence virtuoso the Kf parameter shown in the formula bellow?

Thanks.

We have many legacy board designs which have non-standard films. I'm writing SKILL code to automatically align a board's film records with our internal standard.

While I'm sure there will be multiple questions, here are the first two I've run into:

1. It seems the polyCutLayer parameter of axlFilmCreate() doesn't work. You can easily see this for yourself. Try typing "axlFilmCreate("test" ?polyCutLayer nil)" on the command window in Allegro. I'm returned "nil", indicating the film could not be created, and I see "*WARNING* (axlFilmCreate): Invalid option type: ?polyCutLayer" in the command window. Just to try a different parameter and see that it works, try "axlFilmCreate("test" ?negative t)". I'm returned a "t" and the film is created. Page 139 of 17.4-2019 algroskill.pdf shows this parameter and I can see it listed if I inspect an existing from from the DB, so what gives? Is the polyCutLayer parameter broken when creating films?

2. In conjunction with the above, if I loop through all current films and use axlDeleteObject() to remove them all, and then try to create new films but give an argument to the polyCutLayer parameter, films containing copper layers seem to be automatically created. There are four films (my test board has four layers) with the ETCH/, PIN/, and VIA CLASS/ subclasses. I am able to manually delete all films and see absolutely no films at all. Is there something weird going on here or is this to be expected for some reason?

I'm running Allegro 17.4s002.

Hi experts,

I have a problem with my design as below

ERROR: in SHAPE (-2.3622 2.3622)

  class = ETCH

  subclass = TOP 

  Part of Symbol Def SHAPE_4725X4725.

      Which is part of a padstack as a SHAPE symbol.

  ERROR(SPMHDB-187): SHAPE boundary may not cross itself.

   Error cannot be fixed.

       Object has first point location at (-2.3622 2.3622).

Can you tell me how to solve my problem?

Thanks a lot.

I would like to generate the comparison report of database footprint with library footprint if any mismatch available.

Is there a way to take if it possible means can anyone please guide me or share me the skill code please.

Thanks,

Pradeep

Other tools allow a sanity check of placement density vs available board space.  There is an older post "Skill code to evaluate all components area (Accumulative Place bound area)"  (9 years ago) that has a couple of examples that no longer work or expired.

This would be useful to provide feedback to schismatic and project managers regarding the component density on the PCB and how it will affect the routing abilities.  Thermal considerations can be evaluated as well 

Has anyone attempted this or still being done externally in spread sheets?

I'm in the process of weeding a regression test list. I have a coverage database from the full regression list and would like to diff it with the coverage database from the new reduced regression test list. If possible I would than like to trace back any buckets covered with the full list, but not with the partial list, into the original tests that covered them.

Is that possible using IMC? if not, is it possible to do from Specman itself?

(Note that we're not using vManager)

Thanks,

Avidan

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...(read more)

I've redesigned a custom TO220FLAT Package

First I created a TO220shape.ssm  with PCB Editor. Then I created a surface mount T220build.pad in Padstack Editor using TO220shape.ssm. Then I created a TO220FLAT.psm in PCB Editor. I placed 3 Connect pins and 9 Mechanical pins for the TO220 TAB, using standard through-hole pads for better current handling.

Adding those Mechanical pins created many DRC errors caused by the proximity of those pads attached to the TO220shape.

Thru Pin to SMD Pin Spacing (-200.0 0.0) 5 MIL OVERLAP DEFAULT NET SPACING CONSTRAINTS Mechanical Pin "Pad50sq30d" Pin "T220build, 2"

I corrected the situation (so I though) by Waiving those DRC errors, thinking that they could not cause any problem and because that’s what I want, i.e.: 9 through-holes under the TO220 device. The idea being that when this device is mounted flat on the PCB it could carry lots of current via 9 pads that could make a good high current conductor to inner layers.

I then saved the Package and updated all related footprint schematic parts  in Capture. Created a new Netlist. Then I imported the new logic into PCB Editor to reflect that change. When the File > Import > Logic is finished I get no feedback error! (which, for me is a substantial achievement in itself)

Now, in the Design Window I see all those DRC errors popping up again, despite the fact that I waived those DRCs back in the Padstack edition. If I run a Design Rule Check (DRC) Report I will see all those DRC listed again. Now, I understand that I can go ahead and waive all those DRCs (100 in total) but I’m thinking there is got to be a better way of doing this.

Please, any advise is welcome. Thanks

Hi,

I want to convert ircx file(which from TSMC) to ict or emDataFile for Voltus-fi.

I tried many way, but I can not make it.

and I  do not installed QRC.

below is some tools installed my server. 

IC617-64b.500.21 is used.

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.(read more)

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کورونا وائرس کے پیش نظر مسجد حرام اور مسجد نبوی میں سماجی فاصلہ کے اصول اور صحت سے متعلق جاری کردہ پروٹوکول پرعمل درآمد شروع کرا دیا گیا ہے ۔

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پٹنہ کے مسلم علاقوں جیسے سبزی باغ ، سلطان گنج ، عالم گنج ، لال باغ ، پٹنہ سٹی ، عظیم آباد ، پٹنہ جنکشن ، ہارون نگر، سمن پورا اور پھلواری شریف کی گلیوں میں قرآن پڑھنے کی آوازیں صاف طور سے سنائی دیتی ہیں ۔

رمضان المبارک میں تراویح کی نماز یوں تو دو دو رکعت  کرکے پڑھی جاتی ہے ، مگر اگر کوئی شخص چار رکعت کی نیت ایک ہی ساتھ باندھ  لے تو کیا یہ درست ہے ؟ جانئے کہتے ہیں علما کرام ۔

رمضان المبارک کا مقدس مہینہ سایہ فگن ہے ۔ اس بابرکت مہینہ میں مردوں کے مقابلہ میں خواتین پر کام کاج کا زیادہ بوجھ ہوتا ہے ۔ ایسے میں دیکھئے خواتین کس طرح کی عبادات کرکے زیادہ سے زیادہ ثواب کما سکتی ہیں ۔

رمضان المبارک کا مقدس ماہ سایہ فگن ہے ۔ دنیا بھر کے مسلمان اس بابرکت ماہ میں روزہ رکھ رہے ہیں اورعبادات میں مصروف ہیں ۔ جانئے ماہ رمضان میں دن میں روزہ رکھ کر زیادہ سونا کیسا ہے اور اس بارے میں علما کرام کا کیا کہنا ہے ؟

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14 ફેબ્રુઆરીને વેલેન્ટાઈન ડે તરીકે ઉજવવામાં આવે છે. યુવાન હૈયાઓ આ દિવસની આતુરતાથી રાહ જોતા હોય છે. આ દિવસે યુવક યુવતીઓ પોતાના પ્રીય પાત્રને ગીફ્ટ આપીને પ્રેમનો એકરાર કરતા હોય છે. પરંતુ ગિફ્ટ આપવી અથવા લેવી અલગ અલગ ગ્રહો ઉપર અલગ અલગ અસર કરે છે.

માં બ્રહ્મચારિણીએ શ્વેત વસ્ત્ર પહેર્યા છે. એમના એક હાથમાં અષ્ટદળની જપમાળા અને બીજા હાથમાં કમંડલ સુશોભિત છે.

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Shaktikanta Das: દુનિયામાં સૌથી મોટી મંદીનું અનુમાન, 1929 બાદ સૌથી મોટું આર્થિક સંકટ

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