1 Dominican Peso = 1.3336 Russian Ruble

1 Dominican Peso = 0.4566 Czech Republic Koruna

1 Papua New Guinean Kina = 21.3981 Russian Ruble

1 Papua New Guinean Kina = 7.3265 Czech Republic Koruna

1 Brunei Dollar = 51.9393 Russian Ruble

1 Brunei Dollar = 17.7834 Czech Republic Koruna

I’m coming to the party late—last weekend, for the first but not the last time, I watched Manish Acharya’s comedy, Loins of Punjab Presents. Behan____, what a film! 

I will not rehearse the synopsis or plot, partly because of the lateness of the hour, but also because it is available here. Instead, let me note quickly that the comedy keeps ticking, and the attention to detail in all matters, from the plot to the casting, makes this film a pleasure to watch.

Let me use one scene to make a point about where the film is coming from. Ishitta Sharma, playing a demure, Gujju girl called Preeti Patel, is one of the competitors in the Desi Idol competition in New Jersey. We have watched her sing beautifully, and we have watched her stay silent, eyes downcast, as her family-members make fools of themselves. But there’s a moment later in the film, when an older, wily competitor, played with classy ease by Shabana Azmi, tries to manipulate her. And suddenly, in the blink of an eye, Preeti Patel turns upon the Shabana character. It’s as if she always had a dagger hiding in her hand.

When I saw that, I thought that there was a similar strength in the movie I was watching. It’s all laughs but it has a quicksilver intelligence within. It is a declaration of independence by the desi diaspora—and what is great is that it celebrates this freedom by mocking, and loving, almost everything in sight.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 21st installment of The Rationalist, my column for the Times of India.

When all political parties agree on something, you know you might have a problem. Giriraj Singh, a minister in Narendra Modi’s new cabinet, tweeted this week that our population control law should become a “movement.” This is something that would find bipartisan support – we are taught from school onwards that India’s population is a big problem, and we need to control it.

This is wrong. Contrary to popular belief, our population is not a problem. It is our greatest strength.

The notion that we should worry about a growing population is an intuitive one. The world has limited resources. People keep increasing. Something’s gotta give.

Robert Malthus made just this point in his 1798 book, An Essay on the Principle of Population. He was worried that our population would grow exponentially while resources would grow arithmetically. As more people entered the workforce, wages would fall and goods would become scarce. Calamity was inevitable.

Malthus’s rationale was so influential that this mode of thinking was soon called ‘Malthusian.’ (It is a pejorative today.) A 20th-century follower of his, Harrison Brown, came up with one of my favourite images on this subject, arguing that a growing population would lead to the earth being “covered completely and to a considerable depth with a writhing mass of human beings, much as a dead cow is covered with a pulsating mass of maggots.”

Another Malthusian, Paul Ehrlich, published a book called The Population Bomb in 1968, which began with the stirring lines, “The battle to feed all of humanity is over. In the 1970s hundreds of millions of people will starve to death in spite of any crash programs embarked upon now.” Ehrlich was, as you’d guess, a big supporter of India’s coercive family planning programs. ““I don’t see,” he wrote, “how India could possibly feed two hundred million more people by 1980.”

None of these fears have come true. A 2007 study by Nicholas Eberstadt called ‘Too Many People?’ found no correlation between population density and poverty. The greater the density of people, the more you’d expect them to fight for resources – and yet, Monaco, which has 40 times the population density of Bangladesh, is doing well for itself. So is Bahrain, which has three times the population density of India.

Not only does population not cause poverty, it makes us more prosperous. The economist Julian Simon pointed out in a 1981 book that through history, whenever there has been a spurt in population, it has coincided with a spurt in productivity. Such as, for example, between Malthus’s time and now. There were around a billion people on earth in 1798, and there are around 7.7 billion today. As you read these words, consider that you are better off than the richest person on the planet then.

Why is this? The answer lies in the title of Simon’s book: The Ultimate Resource. When we speak of resources, we forget that human beings are the finest resource of all. There is no limit to our ingenuity. And we interact with each other in positive-sum ways – every voluntary interactions leaves both people better off, and the amount of value in the world goes up. This is why we want to be part of economic networks that are as large, and as dense, as possible. This is why most people migrate to cities rather than away from them – and why cities are so much richer than towns or villages.

If Malthusians were right, essential commodities like wheat, maize and rice would become relatively scarcer over time, and thus more expensive – but they have actually become much cheaper in real terms. This is thanks to the productivity and creativity of humans, who, in Eberstadt’s words, are “in practice always renewable and in theory entirely inexhaustible.”

The error made by Malthus, Brown and Ehrlich is the same error that our politicians make today, and not just in the context of population: zero-sum thinking. If our population grows and resources stays the same, of course there will be scarcity. But this is never the case. All we need to do to learn this lesson is look at our cities!

This mistaken thinking has had savage humanitarian consequences in India. Think of the unborn millions over the decades because of our brutal family planning policies. How many Tendulkars, Rahmans and Satyajit Rays have we lost? Think of the immoral coercion still carried out on poor people across the country. And finally, think of the condescension of our politicians, asserting that people are India’s problem – but always other people, never themselves.

This arrogance is India’s greatest problem, not our people.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

I have completed physical design of a block in innovus. I want to extract rc of that block using quantus .  It will be very helpful if you give step by step procedure and command to run quantus to extract rc of that block.

Hi,

I am trying to write a skill code where it takes form inputs by default and just displays tree directly.

i have written below code,

procedure( create_tree()
let(()

leHiTree()
leTreeForm->treeOption->value="Current to user level"
leTreeForm->userLevel->value= 31
ipcSleep(1)
hiFormDone(leTreeForm)

))

the form takes in values but it is not closing.

tried with regtimer in place of ipc sleep, didn't work.

how to close form(should be same as pressing OK)? 

Thanks in advance,

vishwas 

Inside the scope of isCallable there is code which I don't want to be executed.

The procedure named in isCallable to-day is callable.

I want to make that procedure so it cannot be called.  How do I do that?

I can't change the isCallable line or the scope.  I want to change its behavior by making sure that the procedure does not exist (obviously this would be done before the code is executed).

Can anybody assist with a Skill code /function to disable all callbacks

As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning...(read more)

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...(read more)

It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...(read more)

The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more)

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more)

CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...(read more)

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more)

I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. 

The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Do you have a set of Bluetooth earbuds yet? If not, you will. The iPhone was the first to kill the ubiquitous 3.5mm headphone jack, but many other manufacturers have quietly followed. Of course,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3:

According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

1. Visual Studio Code 34.9%
2. Visual Studio 34.3%
3. Notepad++ 34.2%
4. Sublime Text 28.9%
5. Vim 25.8%
6. IntelliJ 24.9%
7. Android Studio 19.3%
8. (DVT) Eclipse 18.9%
9. …

15. Emacs 4.1%

Of these, only Vim, (DVT) Eclipse, and Emacs support editing in e-language (at least, last time I checked). Kate, which comes with KDE and also has a Specman mode, is not on this list.

I started using Sublime Text 3 some time ago. It offers packages that support a number of programming languages.

Though there is an e-language syntax available from Tsvi Mostovicz, it is unfinished work, and there are many syntactic constructs are missing. So, I created a fork of his project and finished it (it will eventually be merged back here).

It is a never-ending task because my code base for testing is limited and e is still undergoing development. The project is available through ST3's Package Control and you can contribute to it via Github.

I am eagerly waiting for your pull requests and/or comments and contributions!

So, what if you can figure out all that can go wrong when your product is being assembled early on? Not guess but know and correct at an early stage – not wait for the fabricator or manufacturer to send you a long report of what needs to change. That’s why Design for Assembly (DFA) rules(read more)

All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check.  

The power structure integrity of a mixed-signal, low-power block is verified via Conformal Low Power integrated into the Virtuoso Schematic Editor Power Intent Export Assistant (VSE-PIEA). Here is the flow.

Applying the flow iteratively from lower to higher levels can verify the power structure.

Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: Mixed-Signal Low Power Structural Verification.

• To read the overview presentation, click on following link: PIEA Overview
• To download this PIEA RAK click on following link: PIEA RAK Download

The RAK includes Rapid Adoption Kit with demo design (instructions are provided on how to setup the user environment). It Introduces the Power Intent Export Assistant (PIEA) feature that has been implemented in the Virtuoso IC615 release.  The power intent extracted is then verified by calling Conformal Low Power (CLP) inside the Virtuoso environment.

• Last Update: 11/15/2012.
• Validated with IC 6.1.5 and CLP 11.1

The RAK uses a sample test case to go through PIEA + CLP flow as follows:

• Setup for PIEA
• Perform power intent extraction
• CPF Import: It is recommended to Import macro CPF, as oppose to designing CPF for sub-blocks. If you choose to import design CPF files please make sure the design CPF file has power domain information for all the top level boundary ports
• Generate macro CPF and design CPF
• Perform low power verification by running CLP

It is also recommended to go through older RAKs as prerequisites.

• Conformal Low Power, RTL Compiler and Incisive: Low Power Verification for Beginners
• Conformal Low Power: CPF Macro Models
• Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users

To access all these RAKs, visit our RAK Home Page to access Synthesis, Test and Verification flow

Note: To access above docs, use your Cadence credentials to logon to the Cadence Online Support (COS) web site. Cadence Online Support website https://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you can receive new solutions, Application Notes (Technical Papers), Videos, Manuals, and more.

You can send us your feedback by adding a comment below or using the feedback box on Cadence Online Support.

Sumeet Aggarwal

I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here. In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430^TM microcontrollers at Texas Instruments, the group's line-up is an impressive "who's who" of the microcontroller space, including Analog Devices, ARM, Atmel, Cypress, Energy Micro, Freescale, Fujitsu, Microchip, Renesas, Silicon Labs, STMicro, and TI.

As the press release explains, unlike usual processor benchmark suites which focus on performance, the ULP benchmark will focus on measuring the energy consumed by microcontrollers running various computational workloads over an extended time period. The benchmarking methodology will allow the microcontrollers to enter into their idle or sleep modes during the majority of time when they are not executing code, thereby simulating a real-world environment where products must support battery life measured in months, years, and even decades.

Processor performance benchmarks seem to be as widely criticized as EPA fuel consumption figures for cars - and the criticism is somewhat related. There is a suspicion that manufacturers can tune the performance for better test results, rather than better real-world performance. On the face of it, the task to produce meaningful ultra low power benchmarks seems even more fraught with difficulties. For a start, there is a vast range of possible energy profiles - different ways that computing is spread over time - and a plethora of low power design techniques available to optimize the system for the set of profiles that particular embedded system is likely to experience. Furthermore, you could argue that, compared with performance in a computer system, energy consumption in an ultra low power embedded system has less to do with the controller itself and more to do with other parts of the system like the memories and mixed-signal real-world interfaces.

EEMBC cites that common methods to gauge energy efficiency are lacking in growth applications such as portable medical devices, security systems, building automation, smart metering, and also applications using energy harvesting devices. At Cadence, we are seeing huge growth in these areas which, along with intelligence being introduced into all kinds of previously "dumb" appliances, is becoming known as the "Internet of Things." Despite the difficulties, with which the parties involved are all deeply familiar, I applaud this initiative. While it may be difficult to get to apples-to-apples comparisons for energy consumption in these applications, most of the time today we don't even know where the grocery store is. If the EEMBC effort at least gets us to the produce department, we're going to be better off.

Pete Hardee 

There is no better way other than a self-help training kit -- (rapid adoption kit, or RAK) -- to demonstrate the Incisive Enterprise Simulator's IEEE 1801 / UPF low-power features and its usage. The features include:

• Unique SimVision debugging 
• Patent-pending power supply network visualization and debugging
• Tcl extensions for LP debugging
• Support for Liberty file power description
• Standby mode support
• Support for Verilog, VHDL, and mixed language
• Automatic understanding of complex feedthroughs
• Replay of initial blocks
• ‘x' corruption for integers and enumerated types
• Automatic understanding of loop variables
• Automatic support for analog interconnections

Mickey Rodriguez, AVS Staff Solutions Engineer has developed a low power UPF-based RAK, which is now available on Cadence Online Support for you to download.

• This rapid adoption kit illustrates Incisive Enterprise Simulator (IES) support for the IEEE 1801 power intent standard. 

Patent-Pending Power Supply Network Browser. (Only available with the LP option to IES)

• In addition to an overview of IES features, SimVision and Tcl debug features, a lab is provided to give the user an opportunity to try these out.

The complete RAK and associated overview presentation can be downloaded from our SoC and Functional Verification RAK page:

We are covering the following technologies through our RAKs at this moment:

Synthesis, Test and Verification flow
Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
Silicon-Package-Board Design
Verification IP
SOC and IP level Functional Verification
System level verification and validation with Palladium XP

Please visit https://support.cadence.com/raks to download your copy of RAK.

We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for learning more about Cadence tools, technologies, and methodologies as well as getting help in resolving issues related to Cadence software. If you are signed up for e-mail notifications, you're likely to notice new solutions, application notes (technical papers), videos, manuals, etc.

Note: To access the above documents, click a link and use your Cadence credentials to log on to the Cadence Online Support https://support.cadence.com/ website.

Happy Learning!

Sumeet Aggarwal and Adam Sherer

Hello, i have a realy mistick thing going with copying libraries in cadence virtuoso,

When i copy straight forwart the whole library it gives me a warning that accsess was denied,but when i go into the library and copy it as a single file, then it goes fine.

another problem is it doesnt show in the massage console  ALL the files which could not be copied.(which is the much bigger problem,becuase i would have to pass threw all the subdirectories to verify if all files are there)

Is there a way to see which files wasnt able to be copied?

Thanks. 

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hello, I am trying to use two inductors in my LNA as shown bellow to have a S-PARAM response so i will have S11 with lowerst possible values and tweak them for matching network. However when i ran EXPLORER live tuning with SParam as shown bellow i get no change in the response.

I know that Cgs and Cgd with the inductors having a resonance so by Varying L value i should have seen the change in resonance location,

But there is no change.Where did i go wrong?

Thanks. 

Hello, i have built a matching network of 13dB gain and  NF as shown bellow step by step.(including all the plots and matlab )

its just not working at all,i am doing it exacly by the thoery

taking a point inside the circle-> converting its gamma to Z_source->converting gamma_s into gamma_L with the formulla bellow as shown in the matlab->converting the gamma_L into Z_L-> building the matching network for conjugate of Z_L and Z_c.Its just not working.

where did i got  wrong?

Thanks.

gamma_s=75.8966*exp(deg2rad(280.88)*i);
z_s=gamma2z(gamma_s,50);
s11=0.99875-0.03202*i
s12=721.33*10^(-6)+8.622*10^(-3)*i
s21=-188.37*10^(-3)+30.611*10^(-3)*i
s22=875.51*10^(-3)-100.72*10^(-3)*i
gamma_L=conj((s22+(s12*s21*gamma_s)/(1-s11*gamma_s)))
z_L=gamma2z(gamma_L,50)

I am trying to understand why axlDBTextBlockCompact(nil) on my test case says it can compact the text blocks down to 38, whereas I find only a total of 26 unique text block references in axlDBGetDesign()->text, axlDBGetDesign()->symbols and axlDBGetDesign()->symdefs. Where else are text blocks used besides these three?

Hi 

I'm trying to find the location of the assembly line in the design automatically without using "Show Element". And also I want to find the end points of that line. The line exists in "Package Geometry/Assembly_Top" Layer. So is there any code snippet to find the location of assembly line?

This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 21st installment of The Rationalist, my column for the Times of India.

When all political parties agree on something, you know you might have a problem. Giriraj Singh, a minister in Narendra Modi’s new cabinet, tweeted this week that our population control law should become a “movement.” This is something that would find bipartisan support – we are taught from school onwards that India’s population is a big problem, and we need to control it.

This is wrong. Contrary to popular belief, our population is not a problem. It is our greatest strength.

The notion that we should worry about a growing population is an intuitive one. The world has limited resources. People keep increasing. Something’s gotta give.

Robert Malthus made just this point in his 1798 book, An Essay on the Principle of Population. He was worried that our population would grow exponentially while resources would grow arithmetically. As more people entered the workforce, wages would fall and goods would become scarce. Calamity was inevitable.

Malthus’s rationale was so influential that this mode of thinking was soon called ‘Malthusian.’ (It is a pejorative today.) A 20th-century follower of his, Harrison Brown, came up with one of my favourite images on this subject, arguing that a growing population would lead to the earth being “covered completely and to a considerable depth with a writhing mass of human beings, much as a dead cow is covered with a pulsating mass of maggots.”

Another Malthusian, Paul Ehrlich, published a book called The Population Bomb in 1968, which began with the stirring lines, “The battle to feed all of humanity is over. In the 1970s hundreds of millions of people will starve to death in spite of any crash programs embarked upon now.” Ehrlich was, as you’d guess, a big supporter of India’s coercive family planning programs. ““I don’t see,” he wrote, “how India could possibly feed two hundred million more people by 1980.”

None of these fears have come true. A 2007 study by Nicholas Eberstadt called ‘Too Many People?’ found no correlation between population density and poverty. The greater the density of people, the more you’d expect them to fight for resources – and yet, Monaco, which has 40 times the population density of Bangladesh, is doing well for itself. So is Bahrain, which has three times the population density of India.

Not only does population not cause poverty, it makes us more prosperous. The economist Julian Simon pointed out in a 1981 book that through history, whenever there has been a spurt in population, it has coincided with a spurt in productivity. Such as, for example, between Malthus’s time and now. There were around a billion people on earth in 1798, and there are around 7.7 billion today. As you read these words, consider that you are better off than the richest person on the planet then.

Why is this? The answer lies in the title of Simon’s book: The Ultimate Resource. When we speak of resources, we forget that human beings are the finest resource of all. There is no limit to our ingenuity. And we interact with each other in positive-sum ways – every voluntary interactions leaves both people better off, and the amount of value in the world goes up. This is why we want to be part of economic networks that are as large, and as dense, as possible. This is why most people migrate to cities rather than away from them – and why cities are so much richer than towns or villages.

If Malthusians were right, essential commodities like wheat, maize and rice would become relatively scarcer over time, and thus more expensive – but they have actually become much cheaper in real terms. This is thanks to the productivity and creativity of humans, who, in Eberstadt’s words, are “in practice always renewable and in theory entirely inexhaustible.”

The error made by Malthus, Brown and Ehrlich is the same error that our politicians make today, and not just in the context of population: zero-sum thinking. If our population grows and resources stays the same, of course there will be scarcity. But this is never the case. All we need to do to learn this lesson is look at our cities!

This mistaken thinking has had savage humanitarian consequences in India. Think of the unborn millions over the decades because of our brutal family planning policies. How many Tendulkars, Rahmans and Satyajit Rays have we lost? Think of the immoral coercion still carried out on poor people across the country. And finally, think of the condescension of our politicians, asserting that people are India’s problem – but always other people, never themselves.

This arrogance is India’s greatest problem, not our people.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

I'm in the process of weeding a regression test list. I have a coverage database from the full regression list and would like to diff it with the coverage database from the new reduced regression test list. If possible I would than like to trace back any buckets covered with the full list, but not with the partial list, into the original tests that covered them.

Is that possible using IMC? if not, is it possible to do from Specman itself?

(Note that we're not using vManager)

Thanks,

Avidan

I am using PCB Editor v17.2-2016.

I tried to do placement by schematic page but not all pages are displayed.

Earlier, I successfully do the placement by schematic pages and it was showing all the pages. But then I decided to delete all placed components and to do placement again.

When I try to do placement by schematic page again, I noticed that only the pages that I have successfully do all the placement previously are missing.

Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will store and charge the pucks when not in use.

I'm trying to work out the best way to charge the battery. I'm thinking of having metal "pads" on the rr.com puck that pass through the puck's plastic shell and then make contact with the PCB on the inside, and having a similar system on the charging dock. I'm thinking of having SMD "contact sprints" mounted to the underside of the PCB and have these mate against metal pins that protrude through the puck, but it's the later of which I'm struggling to find. For a visual, think about "restaurant pagers" and how they charge.

I would like to add these components to the component bank in ORCAD simulation. Even an accessible or free course that explained how to create these components.

Hi everybody,

The attached package is a tiny code example with a demo for an upcoming Team Specman blog post about writing macros.

Hilmar

In a nutshell, tags allows you to navigate through program code distributed over multiple files effectively. e.g if you see a function call or a struct in e-code and want to "jump" to the definition (which may be in a different file) then you just hit CTRL+] in Vim! Pressing CTRL+t will take you back where you came from. Check out http://vim.wikia.com/wiki/Browsing_programs_with_tags#Using_tags if you want to learn more about how to use tags with Vim.

This utility can generate tags file for your e files. It can either walk through e import order, a directory recursively or all directories on SPECMAN_PATH recursively! The tags file will have tags for struct, unit, types, events, defines, fields, variables, etc.

For help and some examples, just run ctags4e -help.

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

I put some stimulus in the simulation file section : 

_vpd_data_enb (pu_data_enb 0) vsource wave=[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl
_vpu_data_enb (pd_data_enb 0) vsource dc=pu_enb type=dc

I get the following error. 

ERROR (OSSGLD-18): The command character after '[' in the NLP expression '[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl

' is not a valid

character. The command character is the first character after '[' in the NLP

expression. It must be '?', '!', '#', '$', 'n', '@', '.', '~' or '+'. Enter a

valid character as the command character.

si: simin did not complete successfully.

I dont see anything wrong with the stimulus syntax

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.(read more)

The IC6.1.8 ISR10 and ICADVM18.1 ISR10 production releases are now available for download.(read more)