soc verification Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of 3) By feedproxy.google.com Published On :: Mon, 16 Oct 2017 08:10:00 GMT Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspecâ„¢ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key...(read more) Full Article uvm Perspec coherent perspec system verifier coherency library coherency Accellera mediatek ARM pss portable stimulus
soc verification Integrating AMS IP in SoC Verification Just Got Easier By feedproxy.google.com Published On :: Tue, 06 Feb 2018 18:37:00 GMT Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations. But, what about other direction: selecting proper AMS IP views for SoC Verification? Manually export netlist from Virtuoso and then manually assemble together all of the files for use with in command line driven flow? Often, there are multiple views for the same instance (RNM, analog behavioral model, transistor netlist). Which one to pick? Who is supposed to update configuration files? We often work concurrently and update the AMS IP views frequently. Obviously, manually selecting correct and most up-to-date AMS IP views for SoC Verification is tedious and error prone. Thanks to Cadence Innovation, there is a better way! Cadence has developed a Command-Line IP Selector (CLIPS) product as part of the Virtuoso® environment, which: Bridges the gap between MS SoC command-line setup and the Virtuoso-based analog mixed-signal configuration Allows seamless importing of AMS IP from the Virtuoso environment into an existing digital verification setup Provides a GUI-based and command-line use model, flexible to fit into an existing design flow methodologyCLIPS reads MS SoC command (irun) files, identifies required AMS IP modules, uses Virtuoso ADE setup files to properly netlist required modules, and pulls the AMS IP out of the Virtuoso environment. All necessary files are properly extracted/prepared and package as required for the MS SoC command line verification run. CLIPS setup can be saved and rerun as a batch process to ensure the latest IP from the hierarchy is being simulated. For more details, please see CLIPS Rapid Adoption Kit at Cadence Online Support page Full Article AMS mixed signal solution Mixed-Signal analog/mixed-signal Virtuoso mixed signal Virtuoso environment mixed-signal verification