Visual Abstract

Astrid M. Moerman
Dec 23, 2020; 0:jlr.RA120000974v1-jlr.RA120000974
Research Articles

Carotid atherosclerosis is a risk factor for ischemic stroke, one of the main causes of mortality and disability worldwide. The disease is characterized by plaques, heterogeneous deposits of lipids and necrotic debris in the vascular wall, which grow gradually and may remain asymptomatic for decades. However, at some point a plaque can evolve to a high-risk plaque phenotype, which may trigger a cerebrovascular event. Lipids play a key role in the development and progression of atherosclerosis, but the nature of their involvement is not fully understood. Using matrix-assisted laser desorption/ionization mass spectrometry imaging, we visualized the distribution of approximately 200 different lipid signals, originating of > 90 uniquely assigned species, in 106 tissue sections of 12 human carotid atherosclerotic plaques. We performed unsupervised classification of the mass spectrometry dataset, as well as a histology-directed multivariate analysis. These data allowed us to extract the spatial lipid patterns associated with morphological plaque features in advanced plaques from a symptomatic population, revealing spatial lipid patterns in atherosclerosis and their relation to histological tissue type. The abundances of sphingomyelin and oxidized cholesteryl ester species were elevated specifically in necrotic intima areas, while diacylglycerols and triacylglycerols were spatially correlated to areas containing the coagulation protein fibrin. These results demonstrate a clear co-localization between plaque features and specific lipid classes, as well as individual lipid species in high-risk atherosclerotic plaques.

Advanced technologies in the face of war 24 October 2022 — 1:00PM TO 2:00PM Anonymous (not verified) 5 October 2022 Online

How is NATO strengthening its technological edge?

Russia’s invasion of Ukraine has brought with it a heavy focus on technology and weaponry, particularly as casualties mount and large numbers of equipment are lost on both sides. The conflict has highlighted how states and their militaries seek technological superiority and how access to advanced capabilities can help shape the course of the war.

Aiming to sharpen the Alliance’s technological edge, NATO is working to support the development of emerging and potentially disruptive technologies such as artificial intelligence (AI), autonomous systems, biotechnologies and quantum technologies that are seen as presenting both risks and opportunities for the Alliance.

As part of this work, NATO’s newly formed Defence Innovation Accelerator for the North Atlantic (DIANA), hosted by both the UK and Estonia, brings together academia, industry and government to support the development of critical technologies to deter and defend against existing and future threats.

Key questions to be considered by the panel include:

• How will the technologies that form the focus of DIANA’s efforts strengthen the Alliance and prepare it to better deal with threats to peace and security across the region?

• How will these technologies be applied and used in war?

• To what extent can a war be won by technology?

• Is Ukraine, and other future conflict zones, in danger of becoming a testing ground for emerging technologies?

• What has the war in Ukraine taught NATO about modern warfare and how should the Alliance respond to this?

• After the commotion of AUKUS, how will the Alliance manage the sharing of technologies and IP among member states?

As with all members events, questions from the audience drive the conversation.

Read the transcript. 

Neoadjuvant therapy in patients with locally advanced rectal cancer (LARC) has achieved good pathologic complete response (pCR) rates, potentially eliminating the need for surgical intervention. This study investigated preoperative methods for predicting pCR after neoadjuvant short-course radiotherapy (SCRT) combined with immunochemotherapy. Methods: Treatment-naïve patients with histologically confirmed LARC were enrolled from February 2023 to July 2023. Before surgery, the patients received neoadjuvant SCRT followed by 2 cycles of capecitabine and oxaliplatin plus camrelizumab. ⁶⁸Ga-labeled fibroblast activation protein inhibitor ([⁶⁸Ga]Ga-FAPI-04) PET/MRI, [¹⁸F]FDG PET/CT, and contrast-enhanced MRI were performed before treatment initiation and before surgery in each patient. PET and MRI features and the size and number of lesions were also collected from each scan. Each parameter’s sensitivity, specificity, and diagnostic cutoff were derived via receiver-operating-characteristic curve analysis. Results: Twenty eligible patients (13 men, 7 women; mean age, 60.2 y) were enrolled and completed the entire trial, and all patients had proficient mismatch repair or microsatellite-stable LARC. A postoperative pCR was achieved in 9 patients (45.0%). In the visual evaluation, both [⁶⁸Ga]Ga-FAPI-04 PET/MRI and [¹⁸F]FDG PET/CT were limited to forecasting pCR. Contrast-enhanced MRI had a low sensitivity of 55.56% to predict pCR. In the quantitative evaluation, [⁶⁸Ga]Ga-FAPI-04 change in SUL_peak percentage, where SUL_peak is SUV_peak standardized by lean body mass, had the largest area under the curve (0.929) with high specificity (sensitivity, 77.78%; specificity, 100.0%; cutoff, 63.92%). Conclusion: [⁶⁸Ga]Ga-FAPI-04 PET/MRI is a promising imaging modality for predicting pCR after SCRT combined with immunochemotherapy. The SUL_peak decrease exceeding 63.92% may provide valuable guidance in selecting patients who can forgo surgery after neoadjuvant therapy.

HANOVER, Md., Nov. 5, 2024 — Ciena has announced that its optical and routing and switching innovations will once again support the SCinet network at SC24, taking place November 17–22 […]

The post Ciena Powers SC24’s SCinet with High-Speed Connectivity and Advanced Optical Solutions appeared first on HPCwire.

How can manufacturers apply lessons learned from the dawn of the “Exascale Era” to Computer-Aided Engineering to achieve results like never before? Join Addison Snell, CEO, Intersect360 Research, Bill Mannel, VP, High Performance […]

The post Leveraging Exascale Era Technology for Advanced Computer-Aided Engineering appeared first on HPCwire.

IBM and NASA have developed a new AI foundation model for a wide range of climate and weather applications, with contributions from the Department of Energy’s Oak Ridge National Laboratory. […]

The post IBM and NASA Launch Open-Source AI Model for Advanced Climate and Weather Research appeared first on HPCwire.

WALLISELLEN, Switzerland, Nov. 15, 2023 — Hewlett Packard Enterprise (HPE) today announced that Sauber Motorsport AG is partnering with HPE to advance aerodynamics of its Formula One race cars. The […]

The post HPE Unveils Advanced Computational Fluid Dynamics Solutions for Sauber Motorsport appeared first on HPCwire.

Nov. 8. 2024 — High-performance computing (HPC) has been an indispensable research tool for accessing physical realms difficult, or impossible, to achieve with experiment alone. For several decades, the Department […]

The post ECP: ‘Forward’ Projects Boost US Leadership in Advanced Computing and AI appeared first on HPCwire.

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In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

As vehicles transition into interconnected ecosystems, artificial intelligence and advanced technologies become increasingly crucial. Infotainment systems have evolved beyond mere music players to become central hubs for connectivity, entertainment, and navigation. With global demand for comfort, convenience, and safety rising, the automotive infotainment market is experiencing significant growth. Valued at USD14.99 billion in 2023, it is projected to grow at a compound annual growth rate (CAGR) of 9.9% from 2024 to 2030.

To keep pace with this evolution, infotainment systems must accommodate a range of workloads, including audio, voice, AI, and vision technologies. This requires a flexible, scalable Digital Signal Processor (DSP) solution that acts as an offload engine for the main application processor. Integrating a single DSP for varied functions offers a cost-effective solution for high-performance, low-power processing, which aligns well with the needs of Electric Vehicles (EVs).

If you missed the detailed presentation by Casey Ng, Product Marketing Director at Cadence at CadenceLIVE 2024, register at the CadenceLIVE On-Demand site to access it and other insightful presentations. Stay ahead of the curve and explore the future of innovative electronics with us.

Cadence Infotainment Solution: Leading the Charge

Cadence Tensilica HiFi DSPs play a crucial role in enhancing audio capabilities in vehicle infotainment systems. They support applications like voice recognition, hands-free calling, and deliver immersive audio experiences. This technology is also paramount for features such as active noise control, which reduces road and cabin noise, and acoustic event detection for identifying unusual sounds like broken glass. One notable innovation is the "audio bubble," enabling personalized audio zones within the vehicle, ensuring passengers enjoy distinct audio settings.

Cadence HiFi DSP technology enriches the driving experience for electric vehicles by mimicking traditional engine sounds, while its advanced audio processing ensures optimal performance across various digital radio standards. It significantly contributes to noise reduction, hence improving the cabin experience. Integrating a Double Precision Floating Point Unit (FPU) stands out, as it upgrades audio performance and Signal-to-Noise Ratio (SNR) through efficient 64-bit processing, allowing control over numerous speakers without hitches.

These advancements distinguish the DSP as an essential tool in evolving infotainment systems, offering unmatched performance and adaptability. Tensilica HiFi processors, crucial to advanced infotainment SoCs, serve as efficient offload processors, augmenting real-time execution and energy efficiency. Cadence’s ecosystem, with over 200 codecs and software partnerships, propels the evolution of innovative infotainment systems. Introducing the HiFi 5s DSP marks a new era in connected car experiences, setting the stage for groundbreaking advancements.

Exploring Tomorrow with HiFi 5s DSP Technology

The HiFi 5s represents the apex of audio and AI digital signal processing performance. Built on the Xtensa LX8 platform, it introduces capabilities like auto-vectorization, which allows standard C code to be automatically optimized for performance. This synergy of hardware and software co-design marks a significant step forward in DSP technology. By leveraging its extended Single Instruction, Multiple Data (SIMD) capabilities alongside features like a double-precision floating-point unit (DP_FPU), the HiFi 5s delivers unparalleled precision and speed improvements in signal and audio processing tasks. Equally notable are its branch prediction and L2 cache enhancements, which optimize system performance by refining the control code execution and recognizing codec efficiency. The application of such enhancements are particularly beneficial in real-world scenarios.

AI-Powered Audio

Cadence's focus on AI integration with the HiFi 5s demonstrates significant improvements in audio clarity through AI-powered solutions.

• AI models learn from real-world data and adapt dynamically, while classic DSP algorithms rely on fixed rules.
• AI can be fine-tuned for specific scenarios, whereas classic DSP lacks flexibility.
• AI handles extreme and marginal noise patterns better, generalizes well across different environments, and is robust against varying noise characteristics.

Cadence's dedication to artificial intelligence marks a pivotal shift in audio processing. Traditional DSP algorithms, bound by rigid rules, are eclipsed by AI's ability to learn dynamically from real-world data. This adaptability equips AI models to tackle challenging noise patterns and offer unmatched clarity even in noisy environments, making them ideal for automotive and consumer audio applications.

Realtime AI-Optimized Speech Enhancements by OmniSpeech and ai|coustics

OmniSpeech

Our partner, OmniSpeech, has advanced AI-based audio processing that enhances the performance of audio software, specifically for omnidirectional and dipole microphones. Impressively, their technology operates with less than 32MHz and requires only 418kB of memory.

Test results show that background noise is significantly reduced when AI employs a single omnidirectional microphone, outperforming non-AI solutions. Additionally, when using a dipole microphone with AI, there is a 3.5X improvement in the weighted Signal-to-Noise Ratio (SNR) and more than a 28% increase in the Global Mean Opinion Score (GMOS) across various background noise.

ai|coustics

ai|coustics, a Cadence partner specializing in advanced audio technologies, utilizes real-time AI-optimized speech enhancement algorithms. They leverage an extensive speech-quality dataset containing thousands of hours and 100 languages to transform low-quality audio into studio-grade audio. Their process includes:

• De-reverb, which eliminates room resonances, echoes, and reflections

• Removing artifacts from downsampling and codec compression

• Dynamic and adaptive background noise removal

• Reviving audio materials with analog and digital distortions

• Providing support for all languages, accents, and a variety of speakers

Applications include:

• Automotive: Enhances clarity of navigation commands and communication for driver safety

• Consumer audio: Improves voice clarity for better dialogue understanding in TV programs. Optimizes speech intelligibility in communication for both uplink and downlink audio streams

• Smart IoT: Boosts voice command detection and response quality

Performance Enhancements

The advancements in branch prediction and L2 cache integration have significantly boosted performance metrics across various systems. With HiFi 5s, branch prediction increases codec efficiency by an average of 5%, reaching up to 16% in optimal conditions. L2 cache improvements have drastically enhanced system-level performance, evidenced by a 2.3X boost in EVS decoder efficiency. Adding MACs and imaging ISA in imaging use cases has led to substantial advancements. When comparing HiFi 5s to HiFi 5, imaging ISA performance improvements range with >60% average performance improvements.

The Crescendo of the Future

As Cadence continues to blaze trails in DSP technology, the HiFi 5s emerges as the quintessential solution for consumer and automotive audio use cases. With a robust framework for auto-vectorization, an unmatched double-precision FPU, AI-driven audio solutions, and comprehensive system enhancements, Cadence is orchestrating the next era of audio processing, where every note is clearer, every sound richer, and every experience more engaging. It is not just the future of audio—it's the future of how we experience the world around us.

 Discover how Cadence Automotive Solutions can transform your business today!

Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD).

The splash screen for Allegro X APD will appear as shown below, instead of showing APD+ 2023:

For the Windows Start menu in 23.1, it will display as Allegro X APD 2023 instead of APD+ 2023, as shown below

23.1 Start menu 

In the Product Choices window for 23.1, you will see Allegro X Advanced Package Designer in the place of Allegro Package Designer +, as shown below: 

23.1 product title

Have you heard that starting SPB 23.1, Allegro Package Designer Plus (APD+) will be renamed as Allegro X Advanced Package Designer (Allegro X APD)? 

Allegro X APD offers multiple new features and enhancements on topics like Via Structures, Wirebond, Etchback, Text Wizards, 3D Canvas, and more. 

This post presents the new 3DX Canvas introduced in SPB 23.1. This can be invoked from Allegro X APD (from the menu item View > 3DX Canvas). 

Some of the key benefits of the new canvas: 

• This canvas addresses the scale and complexity in large modern package designs. It provides highly efficient visual representation and implementation of packages. 
  
• The new architecture enables high-performance 3D incremental updates by utilizing GPU for fast rendering. 
  
  
• Real-time 3D incremental updates are supported, which means that the 3D view is in sync with all changes to the database. 
  
  
• The new canvas provides 3D visualization support for packaging objects such as wire bonds, ball, die bump/pillar geometries, die stacks, etch back, and plating bar. 
  
  
• This release also introduces the interactive measurement tool for a 3D view of packages. Once you open 3DX Canvas, press the Alt key and you can select the objects you want to measure. 
  
• 3DX Canvas provides new 3D DRC Bond Wire Clearances with Real 3D DRC Checks. True 3D DRC in Constraint Manager has been introduced. If you open Constraint Manager, there will be a new worksheet added. Following DRC checks are supported: 

  Wire to Wire 
  Wire to Finger 
  Wire to Shape 
  Wire to Cline 
  Wire to Component

The Cadence Palladium Emulation Platform is a hardware system that implements the design, accelerating its execution and verification. Itoffers the highest performance and fastest bring-up times for pre-silicon validation of billion-gate designs, using a custom processor built by Cadence.

This Palladium Introduction course is based on the Palladium 23.03 ISR4 version and covers the following modules:

• Introduction
• Palladium flow
• Running a design on the Palladium system

This course starts with an “Introduction” module that explains Palladium and other verification platforms to show its place in the big picture. It also compares Palladium with Protium and simulation and discusses its usage and limitations.

The “Palladium Flow” module includes two stages at a high level, which are Compile and Run. Then, it covers these stages in detail. First, it covers the ICE compile flow and IXCOM compile flow steps in detail. Then it explains Run, which is common for both ICE and IXCOM modes.

The third module, “Running Design on the Palladium System,” covers all the items required for running your design on the Palladium system, including:

• Software stack requirements
• Basic concepts required to understand the flow
• Compute machine requirements

In addition, this course contains labs for both the ICE and IXCOM flows with detailed steps to exercise the features provided by the Palladium system. The lab explains a practical example of multiple counters and exercising their signals for force, monitor, and deposit features, along with frequency calculation using a real-time clock. The course is available on the Cadence support page:

There is also a Digital Badge available. You will find the Badge exam opportunity when you enroll in the Online training or after you have taken the training as "live" training.

For questions and inquiries, or issues with registration, reach out to us at Cadence Training. Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offerings, visit the Cadence Training website.

Related Training Bytes

• Palladium: What Are Verification Platforms
• Palladium: What Is Processor Based Emulation
• Palladium: Comparing Emulation (Z2) and Prototyping (X2)
• Palladium: What Are ICE and IXCOM Compile Flow
• Palladium: How to Process a Design to Run on Palladium
• Palladium: XCOM Compile Flow (TB+RTL to Palladium Database)
• Palladium: ICE Compile Flow (RTL to Palladium Database)
• Palladium: Legacy ICE Compile Flow
• Palladium: Cadence Software Releases for Palladium and Protium Flow
• Palladium: Setting of PATHs for Using Palladium
• Palladium: Z2 Hardware Structure (Blade and Boards)
• Palladium: What Is Sourceless and Loadless nets
• Palladium: Design Clocks
• Palladium: Step Count and Step Clock
• Palladium: Steps for Running the Design on Palladium Z2

Related Courses

• Verilog Language and Application Training
• SystemVerilog for Design and Verification
• Xcelium Simulator

Related Blogs

• Training Insights – A New Free Online Course on the Protium System for Beginner and Advanced Users
• It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!
• Training Insights - Free Online Courses on Cadence Learning and Support Portal

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Netflix’s Ancient Apocalypse peddles the idea that we have overlooked an extraordinary ancient civilisation. Flint Dibble explains why that is wrong, and why real archaeology is more exciting

Spear-throwing tools called atlatls allow humans to launch projectiles over great distances, but Neanderthals apparently never used them – and an experiment involving a 9-metre-tall platform may explain why

Netflix’s Ancient Apocalypse peddles the idea that we have overlooked an extraordinary ancient civilisation. Flint Dibble explains why that is wrong, and why real archaeology is more exciting

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Title: New Drug May Treat Advanced Melanoma
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Drug–drug interaction (DDI) assessment of therapeutic peptides is an evolving area. The industry generally follows DDI guidelines for small molecules, but the translation of data generated with commonly used in vitro systems to in vivo is sparse. In the current study, we investigated the ability of advanced human hepatocyte in vitro systems, namely HepatoPac, spheroids, and Liver-on-a-chip, to assess potential changes in regulation of CYP1A2, CYP2B6, CYP3A4, SLCO1B1, and ABCC2 in the presence of selected therapeutic peptides, proteins, and small molecules. The peptide NN1177, a glucagon and GLP-1 receptor co-agonist, did not suppress mRNA expression or activity of CYP1A2, CYP2B6, and CYP3A4 in HepatoPac, spheroids, or Liver-on-a-chip; these findings were in contrast to the data obtained in sandwich cultured hepatocytes. No effect of NN1177 on SLCO1B1 and ABCC2 mRNA was observed in any of the complex systems. The induction magnitude differed across the systems (e.g., rifampicin induction of CYP3A4 mRNA ranged from 2.8-fold in spheroids to 81.2-fold in Liver-on-a-chip). Small molecules, obeticholic acid and abemaciclib, showed varying responses in HepatoPac, spheroids, and Liver-on-a-chip, indicating a need for EC₅₀ determinations to fully assess translatability data. HepatoPac, the most extensively investigated in this study (3 donors), showed high potential to investigate DDIs associated with CYP regulation by therapeutic peptides. Spheroids and Liver-on-a-chip were only assessed in one hepatocyte donor and further evaluations are required to confirm their potential. This study establishes an excellent foundation toward the establishment of more clinically-relevant in vitro tools for evaluation of potential DDIs with therapeutic peptides.

Recent studies have demonstrated promising results of fibroblast activation protein (FAP) inhibitor (FAPI) PET in prognosticating and monitoring interstitial lung diseases (ILDs). As a first step toward successful translation, our primary aim was to validate the FAPI PET uptake through immunohistochemistry in patients with advanced ILD who underwent lung transplantation after a FAPI PET scan. Methods: This is a preliminary analysis of a single-center, open-label, single-arm, prospective exploratory biodistribution study of ⁶⁸Ga-FAPI-46 PET imaging in patients with ILD (NCT05365802). Patients with ILD confirmed by high-resolution CT and scheduled for lung transplant were included. Tissue samples of explanted lungs were obtained from both the central and peripheral lung parenchyma of each lobe. Additional samples were obtained from areas of the lung corresponding to regions of FAPI PET activity. Immunohistochemical staining was performed with an anti-FAP antibody. Percentages of FAP immunohistochemistry-positive area were measured semiautomatically using QuPath software. SUVs in the areas of pathologic samples were measured on FAPI PET/CT by referencing the gross photomap of the explanted lung. A Spearman correlation coefficient test was used to assess the relationship between FAPI PET uptake and FAP immunohistochemical expression in each specimen. Results: Four patients with advanced ILD who underwent FAPI PET/CT before lung transplantation were included. The types of ILD were idiopathic pulmonary fibrosis (n = 2), rheumatoid arthritis–associated ILD (n = 1), and nonspecific interstitial pneumonia (n = 1). FAPI uptake was visualized mainly in the fibrotic area on CT. Twenty-nine surgical pathology samples from 3 patients were analyzed. FAP staining was predominantly positive in fibroblastic foci. FAPI PET SUV_max and SUV_mean showed a positive correlation with the immunohistochemical FAP expression score (SUV_max: r = 0.57, P = 0.001; SUV_mean: r = 0.54, P = 0.002). Conclusion: In this analysis conducted in patients who underwent lung transplantation after a FAPI PET scan, FAPI PET uptake was positively correlated with FAP immunohistochemistry. These findings provide a rationale for further investigation of FAPI PET as a potential imaging biomarker for ILD.

The plane is hailed as 'one of the most advanced aircraft available on the market'

Indian and multinational pharma companies are leading the charge by investing in digital transformation and aligning Indian operations with global standards. Essentially, pharmaceutical water systems are

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After a chip manufactured by Taiwan Semiconductor Manufacturing Company (TSMC) was found inside a Huawei processor, the U.S. Department of Commerce has ordered the company to halt shipments of advanced chips to Chinese customers, according to a report in Reuters. Huawei faces significant trade restrictions from the U.S., so the pause on shipments is supposed […]

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