Amid the massive row over his alleged racist remark against Union minister HD Kumaraswamy, Karnataka minister BZ Zameer Ahmed Khan has said he called the JDS leader "Kaalia" out of affection and that he was ready to apologise

Google's Gmail update went live this week. Here's what marketers need to know

According to the SAS Experience 2030 global study, by the year 2030 67% of in-person customer engagements (think sales assistance and information queries) will be completed by smart machines rather than humans. And while it may seem a bit ironic, the most personalized customer experiences could involve no people at [...]

SAS Customer Intelligence 360: Make better decisions with analytically driven marketing was published on Customer Intelligence Blog.

“What’s our plan if we get hit by a big flood?” While this question may be plenty familiar to emergency management professionals, city administrators, legislators, and other leaders in coastal regions that are known for their exposure to potentially disastrous weather events, these days it’s being asked in some unexpected [...]

The post Four technology tips for government leaders preparing for flood disasters appeared first on Government Data Connection.

Read the in depth Review of Jak and Daxter Collection [PS3] Gaming. Know detailed info about Jak and Daxter Collection [PS3] configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of D-Link DIR-X6060 AX6000 Wi-Fi 6 Router Networking. Know detailed info about D-Link DIR-X6060 AX6000 Wi-Fi 6 Router configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router Networking. Know detailed info about TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

I've never been much of a fan of forecasting approaches to intermittent demand. In situations like intermittent demand (or other areas where we have little hope of reasonably accurate forecasts), my thinking is "why bother?" If we can't expect to solve the problem with forecasting, we need a different approach. [...]

The post Intermittent Demand Forecasting (new book by Boylan and Syntetos) appeared first on The Business Forecasting Deal.

SAS software supports two kinds of procedures: interactive and non-interactive. Most SAS procedures are non-interactive. They begin with a PROC statement, include one or more additional statements, and end with a RUN statement. When SAS encounters the RUN statement, the procedure executes all statements, then exits. On the other hand, [...]

The post Interactive procedures in SAS appeared first on The DO Loop.

Some businesses overlook alternative data. That's probably a mistake.

The post Alternative data may feel risky: Here's why it's not appeared first on The Data Roundtable.

At least five people were killed this morning after their speeding car rammed a truck that had broken down and was parked on the roadside in Noida.

A Bengaluru couple found themselves in legal trouble after they posted videos of their balcony garden on Facebook. The posts included images of plants later identified as ganja.

Police on Monday arrested Manisha, wife of jailed gangster Kaushal Chaudhary, for allegedly trying to extort Rs 2 crores from a hotel owner, officials said.

Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

Jimmy Carter celebrated his 100th birthday on Tuesday - the first ever US president to reach the century mark and another extraordinary milestone for the one-time peanut farmer who found his way to the White House.

US President-elect Donald Trump has named Mike Waltz, a Congressman from Florida and co-chair of the India Caucus, as the new National Security Adviser.

1. Nasa Alert: Massive 'God of Chaos' asteroid Apophis nears earth in closest pass yet  CNBCTV18
2. NASA alert! 'God of Chaos' asteroid approaching Earth on November 13 sparks worldwide concern  The Times of India
3. Giant Meteorite To Hit Earth On November 13? What We Know  News18
4. 'Astonishingly close': A colossal space rock could wreak havoc on Earth in 2029  Business Today
5. Giant 'God of Darkness' Asteroid May Not Escape Earth Unscathed  ScienceAlert

1. Ricky Ponting hits back at Gautam Gambhir, calls him 'prickly character'  The Times of India
2. Ricky Ponting Fires Back At Gautam Gambhir After India Coach's Press Conference Remarks  NDTV Sports
3. A fired-up Virat Kohli is Australia's worry after Ricky Ponting's 'bad move'  The Times of India
4. Gambhir a prickly character, never took dig at Kohli: Ponting  The Hindu
5. Border-Gavaskar Trophy: Why Gautam Gambhir comes across as abrasive at times  The Indian Express

1. Magnus Carlsen interview: I probably will have the most fun playing Gukesh  Hindustan Times
2. "It's Chaotic": Chess World No. 1 Magnus Carlsen Reveals Why He Does Not Play In India  NDTV Sports
3. Tata Steel Chess set for a Carlsen-Pragg opening  Hindustan Times
4. Magnus Carlsen returns to Kolkata after almost five years at Tata Steel India Rapid and Blitz 2024  ChessBase India
5. King Carlsen hails growth of Indian chess, praises Praggnanandhaa's fighting spirit  Telegraph India

1. Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
2. Mahavatar First Poster: Vicky Kaushal Takes On The Role Of "The Eternal Warrior Of Dharma"- Parashurama  NDTV Movies
3. Vicky Kaushal drops powerful FIRST LOOK as Lord Parashurama for ‘Mahavatar’  TOI Etimes
4. entertainment News Live Today November 13, 2024: Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
5. Vicky Kaushal to play Chiranjeevi Parashurama in Amar Kaushik’s Mahavatar  India Today

1. Best smartphones under ₹30,000 with good battery life and cameras | Mint  Mint
2. Best smartphones under 20,000 with good cameras: Redmi Note 13 Pro, Vivo T3 5G and others  Hindustan Times
3. 5 Affordable Camera Phones To Make Instagram Reels  Times Now
4. Best Smartphones Under Rs 20,000 With Excellent Cameras, Redmi Note 13 Pro, Vivo T3 5G & More  NewsX

1. Battered Reliance Shares To Make A Comeback? This Analyst Sees 29% Upside Ahead  Benzinga India
2. Reliance Industries shares may see 30% upside according to CLSA, who cites this key trigger  CNBCTV18
3. RIL shares are down 20% from record high, oversold on charts; here's what analysts say  Business Today
4. Six of India’s top 10 most valuable firms shed Rs 1.55 lakh crore in market value  Moneycontrol
5. Reliance Industries Share Price Today on 13-11-2024: Reliance Industries share price are down by -0.63%, Nifty down by -0.8%  Mint

Valve says that customers are limited to one purchase per account.

The post You can Soon Get the Steam Deck OLED in White, but You’d Better Hurry appeared first on Phandroid.

The video features models dressed in the latest fashion, strutting like mannequins on a moving runway outside the designer store ITIB.

The $20 Merry Multiplier scratch-off ticket she chose turned out to be a $250,000 top prize winner.

The couple, together for nine years, had announced the wedding date in January and were eagerly looking forward to their long-awaited special day.

IFTTT (If This Than That), a web-based software that automates and connects over 600 online services/software raised a $24M Series C led by Salesforce. Other investors include IBM and the Chamberlain Group and Fenox Venture Capital.

The latest round brings IFTTT’s funding to $63M and it will use the funding proceeds to provide integration for enterprise and IoT services and hiring. In IFTTT’s platform, applets are code/script users need to deploy to integrate two or more services (such Google Drive’s integration with Twitter/Facebook).

Investment in IFTTT reveals that Salesforce is consolidating its presence in enterprise IoT space. It also acquired Mulesoft, an integration platform that rivals Microsoft’s BizTalk.

IBM’s investment in IFTTT is also noteworthy as the former is pushing its IBM Watson IoT platform. The following statement also shows its keen interest in IFTTT.

Other recent investments in IoT companies include $30M Series B of Armis and Myriota's $15M for its IoT satellite-based connectivity platform.

For latest IoT funding and product news, please visit our IoT news section.

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[Daily Maverick] Office of the Chief Justice reveals Constitutional Court has been unable to sit because of unreliable water supply. This article is free to read.Sign up for free or sign in to continue reading.Unlike our competitors, we don't force you to pay to read the news but we do need your email address to make your experience better.Create your free account or sign in FAQ | Contact Us Nearly there! Create a password to finish signing up with us: You want to receive First Thing, our flagship daily newsletter. Opt

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

The demand for higher-performance computing is greater than ever. Cutting-edge applications in artificial intelligence (AI), big data analytics, and databases require high-speed memory systems to handle the ever-increasing volumes and complexities of data. Advancements in cloud computing and machine virtualization are stretching the limits of current capabilities. AI applications hosted in the cloud rely on fast access and reduced latency in memory systems, which is amplified by an increasing number of CPU and GPU cores.

Introducing the DDR5 Multiplexed Rank DIMM (MRDIMM), the next-generation memory module technology designed to meet the needs of high-performance computing (HPC) and AI in cloud applications. By leveraging existing DDR5 DRAM memory devices, MRDIMM modules not only double the DRAM data rate but also maintain the RAS capabilities of the industry-proven RDIMM modules, setting a new precedent for memory module performance.

Let’s compare RDIMM and MRDIMM modules using the same DRAM parts. Today, high-speed production DDR5 RDIMM modules run at 5600Mbps. Those modules use DDR5 DRAM parts, which also run at 5600Mbps. An MRDIMM module using the same DDR5 5600Mbps DRAM parts will run at a blazing 11.2Gbps.

One key metric for best-in-class performance, low bit error rate (BER), and ease of adoption is the eye diagram. The eye diagram illustrates at-speed system margin and accurately represents DDR system quality when captured with a pseudo-random binary sequence (PRBS)-like pattern. The diagram below illustrates Cadence’s 3nm silicon write eye diagram for DDR5 MRDIMM IP running at 12.8Gbps.

Cadence 3nm DDR5 MRDIMM 12.8Gbps test chip write eye diagram, design kit is available today

The eye diagram is captured using a PRBS-like pattern, incorporating a package and system board representative of a typical MRDIMM channel. Using PRBS-like patterns is crucial for capturing accurate eye diagrams. Repetitive clock-like data patterns create deceptively “open eyes” that do not reflect the real system performance. Effects like intersymbol interference, simultaneous switching, reflections, and crosstalk are not accurately reflected in the eye diagrams for parallel interfaces like DDR using non-random data streams. Relying on improperly captured eye diagrams inevitably leads to a significantly worse real system BER than conveyed by that eye diagram.

Doubling the DDR5 RDIMM data rate is challenging. Achieving high performance while optimizing for area and power requires multiple design techniques. Feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and T-coils are required to reach 12.8Gbps MRDIMM data rates in multi-channel systems. Building a production-worthy 12.8Gbps DDR5 MRDIMM IP requires engineering expertise that comes from many generations of memory interface design and production experience. Cadence has developed this expertise through multiple DDR5/4, LPDDR5X/5, and GDDR6 designs in different technology nodes and foundries. For instance, Cadence’s GDDR6 IP is available in three foundries and ten process nodes, with mass production at speeds exceeding 22Gbps.

For your next project, consider DDR5 12.8Gbps MRDIMM, a technology that not only doubles the bandwidth of DDR5 RDIMM but also promises rapid proliferation into next-generation AI, data center, HPC, and enterprise applications. With its cutting-edge capabilities, the Cadence DDR5 12.8Gbps MRDIMM IP is ready to power the future of computing.

IR criteria:

Static IR (STD) ~2%

Static IR (MEM) ~1%

Dynamic IR (STD) ~10%

Dynamic IR (MEM) ~5%

Anyone knows the reason behind this criteria? >.<

Is there a skill command for "Assign Layout Instance terminals", this form appears when i click on define device correspondence and Bind the devices.

Also,

Problem Statement : i have a schematic with a couple of transistor symbols and and i alos have a corresponding layout view with respective layout transistors but they all are inside a pCell(created by me) i.e layout transistor called inside a custom Pcell. Now i have multiple symbols in schematic view and a single instance(pCell) in layout view. 
Is there a way how i can bind these schematic symbols with layout symbols inside the pCell(custom)? Even if i have to use cph commands i'm fine with it. need help here.

The idea here is to establish XL connectivity between the schematic symbols and corresponding layout transistors(inside the pCell).

Thanks,

Shankar

Hi to all,

I am trying to write an SKILL code to create a schematic. In my code I use "instTerms" to obtain the terminals of an instantiated cell (Let's imagine it is a simple NMOS which is given as a predesigned cell), and then I will connect a wire to each of the terminals. When I run the whole code by command line, the returned terminals by "instTerms" are empty(nil) but when I try to debug it line by line it works properly. As more information, I call it for the instantiated cell, and I should say the cell is instantiated without any problem. This is just the problem of finding its terminals. 

Does anybody have any idea?

Thank you very much in advance.

Amir

Hi,

I have a string "[@global_vddi:%:vddi!]" which I need to process to remove "@[]" chars. The desired result is "global_vddi:%:vddi!". I tried the following in CIW

netExpr = "[@global_vddi:%:vddi!]"
rexCompile("\([a-zA-Z0-9_:!%]+\)")
t
rexExecute(netExpr)
t
rexSubstitute( "\0" )
"global_vddi:%:vddi!"

and I achieved the desired value. I added the same code to my script but it didn't work. In my script rexExecute returns 't' but rexSubstitute returns 'nil' 

Here is the snippet from my script

netExpr = dbGetTermNetExpr(term)
if(netExpr then
rexCompile("\([a-zA-Z0-9_:!%]+\)")
rexExecute(netExpr)
netExpr1 = rexSubstitute( "\0" )

...

. ..)  and trace log showing the variable values as the code executes

stopped before evaluating dbGetTermNetExpr(term)
after evaluating dbGetTermNetExpr(term)==> "[@global_vddi:%:vddi!]"
after evaluating (netExpr = dbGetTermNetExpr(term))==> "[@global_vddi:%:vddi!]"
stopped before evaluating if(netExpr then rexCompile("\([a-zA-Z0-9_:!%]+\)") rexExecute(netExpr) (netExpr1 = rexSubstitute("\0")) ... )
stopped before evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")
after evaluating rexCompile("\([a-zA-Z0-9_:!%]+\)")==> t
stopped before evaluating rexExecute(netExpr)
after evaluating rexExecute(netExpr)==> t
stopped before evaluating (netExpr1 = rexSubstitute("\0"))
stopped before evaluating rexSubstitute("\0")
after evaluating rexSubstitute("\0")==> nil
|[2]netExpr1 set to nil, was nil

Any help or suggestions as to why the code executes differently in CIW and when called from a SKILL script file will be much appreciated.

I also tried a different approach using rexReplace instead of rexSubstitute but couldn't get the regex pattern correct. The code I tried in CIW using rexReplace is as follows

a = "[@global_vddi:%:vddi!]"
"[@global_vddi:%:vddi!]"
rexCompile("\([@\[\]]*\)")
t
rexReplace(a "" 0)
"global_vddi:%:vddi!]"

Only '@[' get replaced and ']' is still present. The regex pattern contains '\]' to match the closing square bracket yet it is not replaced. Please let me know what I'm missing in these 2 scenarios.

Any help is much appreciated!!

Regards,

Confused SKILL user 

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing everything from III-V 5G chips, to RF systems in board and package technologies. These types of designs require close interaction between the schematic and its layout. A new Training Byte demonstrates how the schematic-layout connections is built into Microwave Office.(read more)

Data sets are a powerful and easy-to-use feature in Microwave Office. Data can be effortlessly be swapped in graphs, and circuit schematics.(read more)

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3-compatible rates of 10.3125 Gbps (for Gen 2) and 20.625 Gbps (for Gen 3). It becomes very important to verify the Thunderbolt  backward compatibility with the designs. Though the support of USB4 Interoperability with Thunderbolt  3 (TBT3) is optional in USB4 host or USB4 peripheral device and required USB4 Hub and USB4 Based Dock but it is very essential to work in the existing ecosystem. 

Few Main features of USB4 Interoperability with Thunderbolt  3 (TBT3) Systems

• Support for Bi-Directional Pins & Retimers: TBT3 Active Cables can contain two bidirectional Re-timers which have the capability to send AT Responses on its RX channel. Router connected directly to such Retimer needs to support A Router that is connected directly to a bidirectional Re-timer shall support reception of Transactions on both TX and RX channels. 

• Bounce Mechanism: This feature is used by Router to access the Register Space of a Cable Re-timer that can only be accessed by its Link Partner.
• Asymmetric Negotiation: The Router which connects with Cable Retimers needs to follow Asymmetric TxFFE in Phase 5 of Lane Initialization. 
• USB4 Link Transitions: In TBT3 mode, the configuration of two independent Single Lane Links can be used non-transient state or Single Lane Link just using the Lane1 Adapter.

Cadence has a mature USB4 Verification IP solution that can help in the verification of USB4 designs with TBT3. Cadence has taken an active part in the Cairo group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members. If you plan to have a USB4-compatible design, you can reduce the risk of adopting new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team, for more details.

PHY Interface for the PCI Express (PCIe), SATA, USB, DisplayPort, and USB4 Architectures (PIPE) enables the development of the Physical Layer (PHY) and Media Access Layer (MAC) design separately, providing a standard communication interface between these two components in the system.

In recent years, the PIPE interface specification has incorporated many enhancements to support new features and advancements happening in the supported protocols. As the supported features increase, so does the count of signals on PIPE interface. To address the issue of increasing signal count, the message bus interface was introduced in PIPE 4.4 and utilized for PCIe lane margining at the receiver and elastic buffer depth control.

In PIPE 5.0, all the legacy PIPE signals without critical timing requirements were mapped into message bus registers so that their associated functionality could be accessed via the message bus interface instead of implementing dedicated signals. It was decided that any new feature added in the new version of PIPE specification will be available only via message bus accesses unless they have critical timing requirements that need dedicated signals.

Message Bus Interface

The message bus interface provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. It also enables future PIPE operations to be added without adding additional wires. The use of this interface requires the device to be in a power state with PCLK running.

Control and status bits used for PIPE operations are mapped into 8-bit registers that are hosted in 12-bit address spaces in the PHY and the MAC. The registers are accessed using read-and-write commands driven over the signals M2P_MessageBus[7:0] and P2M_MessageBus[7:0]. These signals are synchronous with the PCLK and are reset with Reset#.

Message Bus Interface Commands

The 4-bit commands are used for accessing the PIPE registers across the message bus. A transaction consists of a command and any associated address and data.

All the following are time multiplexed over the bus from MAC and PHY:

1. Commands (write_uncommitted, write_committed, read, read completion, write_ack)
2. 12-bit address used for all types and read and writes
3. 8-bit data, either read or written

There can be cases where multiple PIPE interface signals can change on the same PCLK. To address such cases, the concept of write_uncommitted and write_committed is introduced.

The uncommitted write should be saved into a write buffer, and its associated data values are updated into the relevant PIPE register at a future time when a write_committed is received, taking effect during the same PCLK cycle. Once a write_committed is sent, no new writes, whether committed or uncommitted, and any read command may be sent until a write_ack is received. Also, it is allowed to send NOP commands between write uncommitted and write committed. 

A simple timing demonstration of message bus:

Message Address Space

MAC and PHY each implement unique 12-bit address spaces. These address spaces will host registers associated with the PIPE operations. MAC accesses PHY registers using M2P_MessageBus[7:0], and PHY accesses the MAC registers using the M2P_MessageBus[7:0].

The MAC and PHY access specific bits in the registers to: initiate operations, Initiate handshakes, and Indicate status.

Each 12-bit address space is divided into four main regions: the receiver address region, the transmitter address region, the common address region, and the vendor-specific address region.

Each register field has an attribute description of either level or 1-cycle assertion. When a level field is written, the value written is maintained by the hardware until the next write to that field or until a reset occurs. When a 1-cycle field is written to assert the value high, the hardware maintains the assertion for only a single cycle and then automatically resets the value to zero on the next cycle.

Cadence has a mature Verification IP solution for the verification of various aspects and topologies of PIPE PHY design. For more details, you may refer to the Simulation VIP for PIPE PHY | Cadence page, or you may send an email to support@cadence.com.

The demand for higher compute performance, energy efficiency, and faster time-to-market drove the conversations at this year's Open Compute Project (OCP) Global Summit in San Jose, California. It was the scene of showcasing groundbreaking innovations, expert-led sessions, and networking opportunities to drive the future of data center technology. For those who didn't get to attend or stop by our booth, here's a recap of Cadence's comprehensive solutions that enable next-generation compute technology, AI data center design, analysis, and optimization. Optimized Data Center Design and Operations As the data center community increasingly faces demands for enhanced efficiency, thermal management, sustainability, and performance optimization, data center operators, IT managers, and executives are looking for solutions to these challenges. At the Cadence booth, attendees explored the Cadence Reality Digital Twin Platform and Celsius EC Solver. These technologies are pivotal in achieving high-performance standards for AI data centers, providing advanced digital twin modeling capabilities that redefine next-generation data center design and operation. The Celsius EC Solver demonstration showed how it solves challenging thermal and electronics cooling management problems with precision and speed. CadenceCONNECT: Take the Heat Out of Your AI Data Center Cadence hosted a networking reception on October 16 titled "Take the Heat Out of Your AI Data Center." In today's AI era, managing the heat generated by high-density computing environments is more critical than ever. This reception offered insights into current and emerging data center technologies, digital twin cooling strategies that deliver energy-saving operations, and a chance to engage with industry leaders, Cadence experts, and peers to explore the latest cooling, AI, and GPU acceleration advancements. Here's a recap: Researcher, author, and entrepreneur Dr. Jon Koomey highlighted the inefficiency of data centers in his talk "The Rise of Zombie Data Centers," noting that 20-30% of their capacity is stranded and unused. He advocated for organizational changes and technological solutions like digital twins to reduce wasted energy and improve computational effectiveness as AI deployments increase. In "A New Millennium in Multiphysics System Analysis," Cadence Corporate VP Ben Gu explained the company's significant strides in multiphysics system analysis, evolving from chip simulation to a broader application of computational software for simulating various physical systems, including entire data centers. He noted that the latest Cadence venture, a digital twin platform for data center optimization, opened the opportunity to use simulation technology to optimize the efficiency of data centers. Senior Software Engineering Group Director Albert Zeng highlighted the Cadence Reality DC suite's ability to transform data center operations through simulation, emphasizing its multi-phase engine for optimal thermal performance and the integration of AI capabilities for enhanced design and management. A panel discussion titled "Turning AI Factory Blueprints into Reality at the Speed of Light" featured industry experts from NVIDIA, Norman Wright Precision Environmental and Power, NV5, Switch Data Centers, and Cadence, who explored the evolving requirements and multidimensional challenges of AI factories, emphasizing the need for collaboration across the supply chain to achieve high-performing and sustainable data centers. Watch the highlights. Transforming Designs from Chips to Data Centers The OCP Global Summit 2024 has reaffirmed its status as a pivotal event for data center professionals seeking to stay at the forefront of technological advancements. Cadence's contributions, from groundbreaking digital twin technologies to innovative cooling strategies, have shed light on the path forward for efficient, sustainable data centers. For data center professionals, IT managers, and engineers, the insights gained at this summit are invaluable in navigating the challenges and opportunities presented by the burgeoning AI era. Partnering with Arm Arm Total Design Cadence is a member of the Arm Total Design program. At an invitation-only special Arm event, Cadence's VP of Research and Development, Lokesh Korlipara, delivered a presentation focusing on data center challenges and design solutions with Arm Neoverse Compute Subsystem (CSS). The session highlighted: Efficient integration of Arm Neoverse CSS into system on chips (SoCs) with pre-integrated connectivity IP Performance analysis and verification of the Neoverse CSS integration into the SoC through Cadence's System VIP verification suite and automated testbench creation, enhancing both quality and productivity Jumpstarting designs through Cadence's collaboration with Arm for 3D-IC system planning, chiplets, and interposers Design Services readiness and global scale to support and/or deliver the most demanding Arm Neoverse CSS-based SoC design projects Cadence Supports Arm CSS in Arm Booth During the event, Cadence conducted a demo in the Arm booth that showcased the Cadence System VIP verification suite. The demo highlighted automated testbench creation and performance analysis for integrating the Arm CSS into SoCs while enhancing verification quality and productivity. Summary Cadence offers data center solutions for designing everything from the compute and networking chips to the board, racks, data centers, and campuses. Stay connected with Cadence and other industry leaders to continue exploring the innovations set to redefine the future of data centers. Learn More Cadence Joins Arm Total Design Cadence Arm-Based Solutions Cadence Reality Digital Twin Platform

On November 5, 2024, the Cadence Bangalore Toastmasters Club celebrated a significant milestone by hosting its 50th meeting. Established in December 2020, the club was created to provide a supportive environment for individuals looking to improve their communication and leadership skills. Over the years, the club has evolved into a vibrant community filled with success stories of personal development and newfound confidence. A testament to the club's dedication is its achievement of the "Select Distinguished Club" status during the 2023-2024 program year. By fulfilling 7 out of 10 distinguished goals, the club highlighted its commitment to excellence—a success driven by its vibrant members' relentless focus and perseverance. The strategic insight gained from regular Toastmasters committee meetings and the influential "Moments of Truth" sessions held in 2023 and 2024 are key to this success. Our club members have consistently demonstrated strong performance in various speech contests, with notable achievements across multiple levels. In 2023, members excelled in Evaluation and Table Topics contests, reaching the district level while advancing to the Division Level in the International Speech Contest. Continuing their success into 2024, members again qualified for area-level contests, securing third-place positions in the Evaluation and Table Topics categories, highlighting the club's dedication and competitive spirit. The 50th meeting was based on the theme of serendipity. It was not only a milestone celebration but also a vibrant festival of achievements and growth. The day buzzed with energy as activities like a spirited Treasure Hunt injected enthusiasm and camaraderie among attendees. Distinguished guests, including Kripa Venkitachalam and Madhavi Rao, enriched the occasion with inspiring speeches. Madhavi reignited the club's spirit, while Kripa's discourse on the Growth Mindset and the "Power of Yet" encouraged members to pursue continuous self-improvement. The Cadence Bangalore Toastmasters Club is enthusiastic about its promising future and is committed to creating an environment that promotes personal and professional growth. Many members are close to completing their Toastmasters levels and pathways, and this term, a new group of approximately 30 individuals has joined, bringing the total membership to 52. This vibrant community is just beginning its journey and is eager to reach new milestones together through mutual support and a shared commitment to excellence. The transformations experienced by many club members are truly compelling. They often share how the club has significantly improved their communication skills and boosted their confidence. One member recalls, "Before joining, I found public speaking intimidating. Now, I embrace every opportunity to share my ideas." Another member highlights how the club's supportive environment helped him overcome his fear of public speaking, propelling his career to new heights. This culture of constructive feedback and continuous improvement has inspired countless members to pursue their dreams with renewed determination and optimism. The Cadence Bangalore Toastmasters Club's journey is a living testament to the power of community and the potential within each of us to grow and achieve greatness. As the club continues to evolve and inspire, it serves as a beacon for those aspiring to transform their skills and seize their moment in the spotlight. Learn more about life at Cadence.

Each November, we are reminded of the bravery and dedication of those who have served our country. At Cadence, we thank our Veteran employees for their patriotism by reaffirming our commitment to honoring their sacrifices and recognizing their contributions to our business success. Our diverse and inclusive culture is strengthened by the unique perspective of our Veteran employees, and we are proud to support the Veterans Inclusion Group as a space for community members and their allies to connect. In celebration of Veterans Day, we were excited to catch up with Johnathan Edmonds, Veterans Inclusion Group Lead and Design Engineering Director, for a heartfelt chat on his journey through military service to leadership within Cadence. Throughout the conversation, he shared the importance of creating space for Veterans, the skills they offer, and his aspirations for what the Veterans Inclusion Group will achieve in the years ahead. Oh yeah, and he flies planes, too! Join us as we dive into what makes this holiday special for so many across the nation and how we can respectfully commemorate it together. Johnathan, you’re a retired Air Force Reservist, pilot, and now a Design Engineering Director. Can you tell us about your journey from the military to your current role at Cadence? I started my military and electronics journey in the Navy. I enlisted at 18 and served for six years as an aviation electronics technician. During this time, I was able to learn about and repair electronics on planes. This set me up for success, and when I was honorably discharged, I attended Virginia Tech to study computer engineering. Once I graduated, I continued my career as an engineer, but I still wanted to be a military pilot. From my past experience, I knew the reserves were an option where I could learn to fly and still have a civilian career. Not only was I lucky enough to get selected to go to pilot training, but after I returned from flight school, my luck grew, and I was hired at Cadence. Cadence has supported me throughout my military career, which has been a great benefit, as many companies don’t support reservists. The best thing about serving and being employed at Cadence is how I could blend my skill sets to further the Air Force’s mission and achieve great things in engineering. As the first lead of Cadence’s Veterans Inclusion Group, you played an integral part in growing our culture and building community at the company since launching the group four years ago. What inspired you to take on the role of Inclusion Group Lead? I was inspired by three things: camaraderie, service, and outreach. I wanted to see if we could achieve a similar sense of community through the Veterans Inclusion Group as we had during our service life. I also wanted to see how we could better serve our Veterans here at Cadence. I wanted to explore any benefits that could be expanded, roles that could be developed by Vets, and, lastly, I wanted to serve a broader community. COVID-19 put a damper on some of the community support, but we are getting back on track with Veteran employment programs and volunteer efforts like Carry the Load and Gold Star Families. Why is it important to have this space dedicated to Veteran employees? There are many reasons! Networking, for one, creates a stronger, more unified Cadence culture. Two, Vets face a variety of issues not generally understood by those who have not served, such as PTSD, where to get help for disabilities, how to get an old medical record, etc. As I mentioned, I’m also passionate about connecting Veterans with employment and job opportunities. It is so nice to work for a company that actively recruits Vets. We have our own “language,” if you will, so it’s nice to have a space to talk in the language that we are familiar with. What have been some of your favorite moments leading this group over the past few years? Are there any “wins” that you would like to recognize? We have a lot of wins. Events held during COVID-19 and getting past COVID-19, donating to worthwhile causes, and hosting guest speakers are all fantastic milestones and accomplishments. That said, the biggest win is the hiring of new Veteran employees. Mark Murphy, Corporate VP of Sales Operations, and I have both welcomed Vets to our team during this time, and it is such a joy to watch what someone can do when given the opportunity to succeed in the right environment. As you are set to transition out of the lead role next year, what do you hope to see the Veterans Inclusion Group accomplish next? My hope is that the Veterans Inclusion Group partners with other companies, expanding our reach externally and exploring new opportunities to engage Veterans outside of Cadence. Johnathan (left) speaks on an inclusion group panel, along with David Sallard (center), lead of Cadence's Black Inclusion Group and Sr. Principal Application Engineer; Christina Jamerson (on screen), lead of Cadence's Abilities Inclusion Group and Demand Generation Director; and Dianne Rambke (right), lead of Cadence's Latinx Inclusion Group and Marketing Communications Director. What are the important ways that people can signal inclusion and respectfully honor Veterans at work? What are the most meaningful or impactful actions employees everywhere can take to support Veteran coworkers? I think there is one answer to both questions. I recommend that people engage with their companies’ employee resource groups (ERGs) and have conversations with them. Opening up the lines of communication will lead to new paths in their journeys. What are you looking forward to in 2025, both personally and professionally? In 2025, professionally, I am looking forward to taking mixed-signal systems and verification to another level by including emulation, automatic model generation, and seeing which boundaries we can push in our SerDes and Chiplets products. Personally, I am looking forward to making my SXS street legal so I can drive places without getting a ticket, seeing my children participate in sports, church, and school, and taking my wife on vacation to Europe or somewhere else we can unplug. Learn more about Cadence’s Inclusion Groups, diverse culture, and commitment to belonging.

This is the 15th installment of The Rationalist, my column for the Times of India.

It’s election season, and promises are raining down on voters like rose petals on naïve newlyweds. Earlier this week, the Congress party announced a minimum income guarantee for the poor. This Friday, the Modi government released a budget full of sops. As the days go by, the promises will get bolder, and you might feel important that so much attention is being given to you. Well, the joke is on you.

Every election, HL Mencken once said, is “an advance auction sale of stolen goods.” A bunch of competing mafias fight to rule over you for the next five years. You decide who wins, on the basis of who can bribe you better with your own money. This is an absurd situation, which I tried to express in a limerick I wrote for this page a couple of years ago:

POLITICS: A neta who loves currency notes/ Told me what his line of work denotes./ ‘It is kind of funny./ We steal people’s money/And use some of it to buy their votes.’

We’re the dupes here, and we pay far more to keep this circus going than this circus costs. It would be okay if the parties, once they came to power, provided good governance. But voters have given up on that, and now only want patronage and handouts. That leads to one of the biggest problems in Indian politics: We are stuck in an equilibrium where all good politics is bad economics, and vice versa.

For example, the minimum guarantee for the poor is good politics, because the optics are great. It’s basically Garibi Hatao: that slogan made Indira Gandhi a political juggernaut in the 1970s, at the same time that she unleashed a series of economic policies that kept millions of people in garibi for decades longer than they should have been.

This time, the Congress has released no details, and keeping it vague makes sense because I find it hard to see how it can make economic sense. Depending on how they define ‘poor’, how much income they offer and what the cost is, the plan will either be ineffective or unworkable.

The Modi government’s interim budget announced a handout for poor farmers that seemed rather pointless. Given our agricultural distress, offering a poor farmer 500 bucks a month seems almost like mockery.

Such condescending handouts solve nothing. The poor want jobs and opportunities. Those come with growth, which requires structural reforms. Structural reforms don’t sound sexy as election promises. Handouts do.

A classic example is farm loan waivers. We have reached a stage in our politics where every party has to promise them to assuage farmers, who are a strong vote bank everywhere. You can’t blame farmers for wanting them – they are a necessary anaesthetic. But no government has yet made a serious attempt at tackling the root causes of our agricultural crisis.

Why is it that Good Politics in India is always Bad Economics? Let me put forth some possible reasons. One, voters tend to think in zero-sum ways, as if the pie is fixed, and the only way to bring people out of poverty is to redistribute. The truth is that trade is a positive-sum game, and nations can only be lifted out of poverty when the whole pie grows. But this is unintuitive.

Two, Indian politics revolves around identity and patronage. The spoils of power are limited – that is indeed a zero-sum game – so you’re likely to vote for whoever can look after the interests of your in-group rather than care about the economy as a whole.

Three, voters tend to stay uninformed for good reasons, because of what Public Choice economists call Rational Ignorance. A single vote is unlikely to make a difference in an election, so why put in the effort to understand the nuances of economics and governance? Just ask, what is in it for me, and go with whatever seems to be the best answer.

Four, Politicians have a short-term horizon, geared towards winning the next election. A good policy that may take years to play out is unattractive. A policy that will win them votes in the short term is preferable.

Sadly, no Indian party has shown a willingness to aim for the long term. The Congress has produced new Gandhis, but not new ideas. And while the BJP did make some solid promises in 2014, they did not walk that talk, and have proved to be, as Arun Shourie once called them, UPA + Cow. Even the Congress is adopting the cow, in fact, so maybe the BJP will add Temple to that mix?

Benjamin Franklin once said, “Democracy is two wolves and a lamb voting on what to have for lunch.” This election season, my friends, the people of India are on the menu. You have been deveined and deboned, marinated with rhetoric, seasoned with narrative – now enter the oven and vote.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Read on to know about the Operating Point Parameters Summary window that gives you a one-stop view of the categorized and tabulated details on all operating point parameters in your design. This window improves your review cycle with its many benefits.(read more)

Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Maybe you've been curious about the role of rule deck writers in creating high-quality designs ready for tape-out.

If any of these questions interest you, there is good news: the latest version (v23.1) of the Physical Verification Rules Writer (PVLRW) course is designed to teach you rule deck writing. This free 16-hour online course includes audio and labs designed to make your learning experience comfortable and flexible. Whether you are new to the concept or an experienced CAD/PDK engineer, the course is structured to enhance your rule deck writing skills.

The PVLRW course covers six core modules: Layer Processing, DRC Rules, Layout Extraction, ERC and LVS Rules, Schematic Netlisting, and Coloring Rules. There are also three optional appendix sections. Each module explains relevant rules with syntax, concepts, graphics, examples, and case studies.

This course is based on tool versions PEGASUS231 and Virtuoso Studio IC231.

Pegasus Input and Output

Pegasus is a cloud-ready physical verification signoff solution that enables engineers to support faster delivery of advanced-node integrated circuits (ICs) to market.

Pegasus requires input data in the form of layout geometry, schematic netlists, and rules that direct the tool operation. The rules fall into two categories: those that describe the fabrication process and those that control the job-specific operation.

Pegasus provides log and report files, netlists, databases, and error databases as output.

Overview of Pegasus Rule File

The rule decks written in Physical Verification Language (PVL) work for the Cadence PV signoff tools Pegasus and PVS (Physical Verification System).   

The PVL rules are placed in a file that gets selected in a run from the GUI or the command line, as the user directs. PVL rules may be on separate lines within the file and can also be contained in named rule blocks.

Each line of code starts with a PVL rule that uses prefix type notation. It consists of a keyword followed by options, input layer or variable names, and output layer or variable names.

A rule block has the format of the keyword rule, followed by a rule name you wish to give it, followed by an opening curly brace. You enter the rules you wish to perform, followed by a closing curly brace on the last separate line.

  Sample Rule deck with individual lines of code and rule blocks.

DRC Rules

The first step in a typical Pegasus flow is a Design Rule Check (DRC), which verifies that layout geometries conform to the minimum width, spacing, and other fabrication process rules required by an IC foundry. Each foundry specifies its own process-dependent rules that must be met by the layout design.

There are three types of DRC rules: layer definition rules, layer derivation rules, and DRC design check rules. Layer definition rules identify the layers contained in the input layout database, and layer derivation rules derive additional layers from the original input layers, allowing the tool to test the design against specific foundry requirements using the design check rules.

A sample DRC Rule deck

A layout view displaying the DRC violations

LVS Rules

The Pegasus Layout Versus Schematic (LVS) tool compares the layout netlist with the schematic netlist to check for discrepancies.

There are two essential LVS rule sets: LVS extraction rules and comparison rules. LVS extraction rules help extract drawn devices and connectivity information from the input layout geometry data and outputs into a layout netlist. The LVS extraction rule set also includes the layer definition, derivation, extraction, connectivity, and net listing rules.

LVS comparison rules are associated with comparing the extracted layout netlist to a schematic netlist.

A sample LVS Rule deck. 

TCL, Macros, and Conditional commands

Tcl is supported and used in various Pegasus functionalities, such as Pegasus rule files and Pegasus configurator. Macros are functional templates that are defined once and can be used multiple times in a rule file. Conditional Commands are used to process or skip specific commands in the rule file.

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• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
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About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts.