In SAS, range attribute maps enable you to specify the range of values that determine the colors used for graphical elements. There are various examples that use the GTL to define a range attribute map, but fewer examples that show how to use a range attribute map with PROC SGPLOT. [...]

The post Automate the creation of a range attribute map in SAS appeared first on The DO Loop.

Learn why integrating EHR data with pharmacy and claims data improves patient care.

The post Closing data gaps to promote integrated health care appeared first on The Data Roundtable.

The Congress will begin a month-long 'Delhi Nyay Yatra' from Rajghat on Friday to corner the Aam Aadmi Party government on various issues affecting the city.

A man was arrested in Noida on Monday for allegedly fabricating a Transfer Certificate (TC) for his son to show that he was a juvenile when he was arrested in a rape and murder case in 2016, police said.

Japan's next prime minister, Shigeru Ishiba, says he reads three books a day and would rather do that than mingle with the ruling party colleagues who picked him as their new leader today

1. Nasa Alert: Massive 'God of Chaos' asteroid Apophis nears earth in closest pass yet  CNBCTV18
2. NASA alert! 'God of Chaos' asteroid approaching Earth on November 13 sparks worldwide concern  The Times of India
3. Giant Meteorite To Hit Earth On November 13? What We Know  News18
4. 'Astonishingly close': A colossal space rock could wreak havoc on Earth in 2029  Business Today
5. Giant 'God of Darkness' Asteroid May Not Escape Earth Unscathed  ScienceAlert

1. Pushpa 2: Sreeleela’s ‘Kissik’ song shoot wrapped up  123telugu
2. Sreeleela Earns 60 Percent Less Than Samantha Ruth Prabhu For Pushpa 2 Song? Fee Details Out  News18
3. Sreeleela's Remuneration For Pushpa 2 Item Song: Hottie Gets Only 40% Of What Samantha Got For Oo Antava  Oneindia
4. Sreeleela's renumeration for 'Pushpa 2' item song revealed; Is way lower than Samantha's 'Oo Antava'  TOI Etimes
5. Meet Sreeleela who has replaced Samantha Ruth Prabhu in Pushpa 2's hot item song; her photo with Allu Arjun l  India.com

1. Google Chrome on iPhones gets new features with Drive, Maps integration  Business Standard
2. Stop Using Chrome On Your iPhone, Warns Apple—Millions Of Users Must Now Decide  Forbes
3. 4 new Chrome improvements for iOS  The Keyword
4. Chrome on iOS now lets you search using images and text at the same time  TechCrunch
5. Google rolls out new features in Chrome for iPhone users  Moneycontrol

1. Telangana train accident: Goods train derails near Peddapalli. Check full list of cancelled, diverted trains today | Today News  Mint
2. Goods train derails in Telangana's Peddapalli; 20 trains cancelled, 10 diverted  The Economic Times
3. 11 coaches of goods train derail in Telangana  The Times of India
4. Goods train derailment in Telangana affects rail traffic between Delhi and Chennai  Telangana Today
5. Goods train derails in Telangana's Peddapalli; 30 trains cancelled, several diverted  The Hindu

1. Delhi: India's capital chokes as air pollution turns 'severe'  BBC.com
2. Several flights diverted due to low visibility conditions at Delhi airport  The Times of India
3. Delhi's toxic air: Why you should not take your cough lightly  India Today
4. Delhi air pollution: Visibility near-zero amid thick smog; CPCB says AQI 'very poor', IQAir shows 'hazardous' | Details  Hindustan Times
5. Delhi's IGI airport sees flight diversions as season's first dense fog hits national capital  Moneycontrol

Xiaomi has recently shown off a demo for their HyperConnect feature, allowing users to share files with Apple users.

The post Xiaomi plays nice with Apple with its new HyperConnect feature appeared first on Phandroid.

Positioned near the side of her head, the eye provides an expansive field of vision, while a thick layer of protective blubber shields it from harm and maintains warmth.

The video features models dressed in the latest fashion, strutting like mannequins on a moving runway outside the designer store ITIB.

[SAPS] - A former company Director (57) is expected to appear in the Thabamoopo Magistrates Court in Lebowakgomo on 11 November 2024 for allegedly defrauding a pensioner an amount of R378 000.00 in the name of business.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[allAfrica] We are excited to share the momentous news that Cape Town Pride has officially won the bid to host WorldPride 2028. This significant event is a global celebration of LGBTQ+ pride and rights, marking a pivotal milestone not only for the LGBTQ+ community in the city but also for the entire African continent. This victory positions Cape Town as a leading symbol of inclusivity and diversity, showcasing its commitment to advancing a welcoming environment for all.

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

As vehicles transition into interconnected ecosystems, artificial intelligence and advanced technologies become increasingly crucial. Infotainment systems have evolved beyond mere music players to become central hubs for connectivity, entertainment, and navigation. With global demand for comfort, convenience, and safety rising, the automotive infotainment market is experiencing significant growth. Valued at USD14.99 billion in 2023, it is projected to grow at a compound annual growth rate (CAGR) of 9.9% from 2024 to 2030.

To keep pace with this evolution, infotainment systems must accommodate a range of workloads, including audio, voice, AI, and vision technologies. This requires a flexible, scalable Digital Signal Processor (DSP) solution that acts as an offload engine for the main application processor. Integrating a single DSP for varied functions offers a cost-effective solution for high-performance, low-power processing, which aligns well with the needs of Electric Vehicles (EVs).

If you missed the detailed presentation by Casey Ng, Product Marketing Director at Cadence at CadenceLIVE 2024, register at the CadenceLIVE On-Demand site to access it and other insightful presentations. Stay ahead of the curve and explore the future of innovative electronics with us.

Cadence Infotainment Solution: Leading the Charge

Cadence Tensilica HiFi DSPs play a crucial role in enhancing audio capabilities in vehicle infotainment systems. They support applications like voice recognition, hands-free calling, and deliver immersive audio experiences. This technology is also paramount for features such as active noise control, which reduces road and cabin noise, and acoustic event detection for identifying unusual sounds like broken glass. One notable innovation is the "audio bubble," enabling personalized audio zones within the vehicle, ensuring passengers enjoy distinct audio settings.

Cadence HiFi DSP technology enriches the driving experience for electric vehicles by mimicking traditional engine sounds, while its advanced audio processing ensures optimal performance across various digital radio standards. It significantly contributes to noise reduction, hence improving the cabin experience. Integrating a Double Precision Floating Point Unit (FPU) stands out, as it upgrades audio performance and Signal-to-Noise Ratio (SNR) through efficient 64-bit processing, allowing control over numerous speakers without hitches.

These advancements distinguish the DSP as an essential tool in evolving infotainment systems, offering unmatched performance and adaptability. Tensilica HiFi processors, crucial to advanced infotainment SoCs, serve as efficient offload processors, augmenting real-time execution and energy efficiency. Cadence’s ecosystem, with over 200 codecs and software partnerships, propels the evolution of innovative infotainment systems. Introducing the HiFi 5s DSP marks a new era in connected car experiences, setting the stage for groundbreaking advancements.

Exploring Tomorrow with HiFi 5s DSP Technology

The HiFi 5s represents the apex of audio and AI digital signal processing performance. Built on the Xtensa LX8 platform, it introduces capabilities like auto-vectorization, which allows standard C code to be automatically optimized for performance. This synergy of hardware and software co-design marks a significant step forward in DSP technology. By leveraging its extended Single Instruction, Multiple Data (SIMD) capabilities alongside features like a double-precision floating-point unit (DP_FPU), the HiFi 5s delivers unparalleled precision and speed improvements in signal and audio processing tasks. Equally notable are its branch prediction and L2 cache enhancements, which optimize system performance by refining the control code execution and recognizing codec efficiency. The application of such enhancements are particularly beneficial in real-world scenarios.

AI-Powered Audio

Cadence's focus on AI integration with the HiFi 5s demonstrates significant improvements in audio clarity through AI-powered solutions.

• AI models learn from real-world data and adapt dynamically, while classic DSP algorithms rely on fixed rules.
• AI can be fine-tuned for specific scenarios, whereas classic DSP lacks flexibility.
• AI handles extreme and marginal noise patterns better, generalizes well across different environments, and is robust against varying noise characteristics.

Cadence's dedication to artificial intelligence marks a pivotal shift in audio processing. Traditional DSP algorithms, bound by rigid rules, are eclipsed by AI's ability to learn dynamically from real-world data. This adaptability equips AI models to tackle challenging noise patterns and offer unmatched clarity even in noisy environments, making them ideal for automotive and consumer audio applications.

Realtime AI-Optimized Speech Enhancements by OmniSpeech and ai|coustics

OmniSpeech

Our partner, OmniSpeech, has advanced AI-based audio processing that enhances the performance of audio software, specifically for omnidirectional and dipole microphones. Impressively, their technology operates with less than 32MHz and requires only 418kB of memory.

Test results show that background noise is significantly reduced when AI employs a single omnidirectional microphone, outperforming non-AI solutions. Additionally, when using a dipole microphone with AI, there is a 3.5X improvement in the weighted Signal-to-Noise Ratio (SNR) and more than a 28% increase in the Global Mean Opinion Score (GMOS) across various background noise.

ai|coustics

ai|coustics, a Cadence partner specializing in advanced audio technologies, utilizes real-time AI-optimized speech enhancement algorithms. They leverage an extensive speech-quality dataset containing thousands of hours and 100 languages to transform low-quality audio into studio-grade audio. Their process includes:

• De-reverb, which eliminates room resonances, echoes, and reflections

• Removing artifacts from downsampling and codec compression

• Dynamic and adaptive background noise removal

• Reviving audio materials with analog and digital distortions

• Providing support for all languages, accents, and a variety of speakers

Applications include:

• Automotive: Enhances clarity of navigation commands and communication for driver safety

• Consumer audio: Improves voice clarity for better dialogue understanding in TV programs. Optimizes speech intelligibility in communication for both uplink and downlink audio streams

• Smart IoT: Boosts voice command detection and response quality

Performance Enhancements

The advancements in branch prediction and L2 cache integration have significantly boosted performance metrics across various systems. With HiFi 5s, branch prediction increases codec efficiency by an average of 5%, reaching up to 16% in optimal conditions. L2 cache improvements have drastically enhanced system-level performance, evidenced by a 2.3X boost in EVS decoder efficiency. Adding MACs and imaging ISA in imaging use cases has led to substantial advancements. When comparing HiFi 5s to HiFi 5, imaging ISA performance improvements range with >60% average performance improvements.

The Crescendo of the Future

As Cadence continues to blaze trails in DSP technology, the HiFi 5s emerges as the quintessential solution for consumer and automotive audio use cases. With a robust framework for auto-vectorization, an unmatched double-precision FPU, AI-driven audio solutions, and comprehensive system enhancements, Cadence is orchestrating the next era of audio processing, where every note is clearer, every sound richer, and every experience more engaging. It is not just the future of audio—it's the future of how we experience the world around us.

 Discover how Cadence Automotive Solutions can transform your business today!

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

I have a standard cell library containing LEF, GDS, and spice models but no OA views. I'm unable to import these files into Virtuoso without a LayerMap file. How can I obtain or generate this required LayerMap file?

I'm trying to write a generic piece of code that will return the layermap file location, with file name, for a variety of projects (which could potential have different layermap file naming conventions. The below code is what I've used to date, but this assumes the file name is xxxx.layermap. I can obviously do some string matching to find it, assuming the various files all contain some common characters. I thought I'd ask if there is a simpler way to find it, I know that this information is automatically loaded into the Xstream out gui, so maybe I can use the same approach to find it.

techLibName=techGetTechFile(cv)~>libName

techLibLayerMap=strcat(ddGetObj(techLibName)~>readPath "/" techLibName ".layermap")

Hello Community,

Is there any simple way how i can get the coordinates of all the shapes in a layout view?

Currently i'm flattening the layout, getting all the lpps from CV and using setof to get all the shapes of a layer and looping through them to get the coordinates.

Is there a way to do it without having to flatten the layout view and shapes merged or any other elegant way to do it if we flatten it?

Also, dbWriteSkill doesn't give output how i desired

Thanks,

Shankar

Disappearing toolbar or docked menu

Is there a way for the toolbar or floating menu from disappearing when a cells tab is added to a window?

I have created a skill toolbar and it disappeared when I add another cell or tab to a window.

The only toolbars that stay are the ones I have defined in the Layout.toolbar file.

Do I have to add a trigger to keep the toolbars visible or not disappearing from the window?

Cadence version IC23.1-64b.ISR7.27

Paul

A new Python library has been written to facilitate an interface between Python and AWR software using a command structure that adheres more closely to Python coding conventions. This library is labeled "pyawr-utils" and it is installed using the standard Python pip command. Comprehensive documentation for installing and using pyawr-utils is available.(read more)

Thermal analysis with the Cadence Celsius Thermal Solver integrated within the AWR Microwave Office circuit simulator gives designers an understanding of device operating temperatures related to power dissipation. That temperature information can be introduced into an electrothermal model to predict the impact on RF performance.(read more)

Hi ,

 I am using conformal v23.2 for LEC checking b/w netlist vs Netlist. I am getting 8 not mapped points(z) in revised but when i check in mapping manager it showing 0 Not mapped points and showing this 8 not mapped points in extra unmapped section z(f) snps_scan_out_6 .How to resolve this issue Pls help

regards,

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement(read more)

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.(read more)

Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...(read more)

Explore Impacts of Finite Interconnect Impedance on PDN Characterization

Over the past few decades, many details have been worked out in the power distribution network (PDN) in the frequency and time domains. We have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior. We also have frequency- and time-domain test methods to measure the steady-state and transient behavior of the built-up systems.

All of these pieces in our current toolbox have their own assumptions, limitations, and artifacts, and they constantly raise the challenging question that designers need to answer: How to select the design process, simulation, measurement tools, and processes so that we get reasonable answers within a reasonable time frame with a reasonable budget.

Read this award-winning DesignCon 2024 paper titled “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.” Led by Samtec’s Istvan Novak and written with a team of nine authors from Cadence, Amazon, and Samtec, the paper discusses a series of continually evolving challenges with PDN requirements for cutting-edge designs.

Read the full paper now: “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.”

Cadence is super excited to announce SPB 23.1 release —Your freedom to design boldly!  

These tools help engineers build better PCBs faster with the new 3D engine and optimized interface.  

We have been hard at work to bring you this release and believe that it will help you take control of the PCB design process with the powerful new features in Allegro X APD like: 

• Packaging Support in 3DX Canvas 

• 3DX Wire DRCs 

• Aligning Components by Offset 

• Text Wizard Enhancements 

• Device File Reuse for Existing Components for Netlist and Logic Import 

Watch this space to know all about What’s New in SPB 23.1.  

Regards 

Team PCBTech 

Cadence Design System 

For individuals, small businesses, or teams, START YOUR FREE TRIAL. 

Starting SPB 23.1, in Allegro X PCB Editor and Allegro X Advanced Package Designer, you can align components by using offset mode. Earlier only spacing mode was available.

Follow these steps to Align Components using Offset Mode:

1. Set Application Mode to Placement Edit.
2. Drag the components that need to be aligned and right-click and choose Align Components.
3. Now, in the Options tab, you will notice Spacing Section with Equal Offset. You can equally and individually offset the components by using the +/- buttons for increment or decrement.

Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD).

The splash screen for Allegro X APD will appear as shown below, instead of showing APD+ 2023:

For the Windows Start menu in 23.1, it will display as Allegro X APD 2023 instead of APD+ 2023, as shown below

23.1 Start menu 

In the Product Choices window for 23.1, you will see Allegro X Advanced Package Designer in the place of Allegro Package Designer +, as shown below: 

23.1 product title

Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup?   

Starting SPB 23.1, a handy feature Transmission Line Calculator, is built into Allegro X Advanced Package Designer (Allegro X APD). This feature will require either an SiP Layout license or can be accessed through SiP Layout Bundle. 

From the Analyze dropdown menu in the 23.1 Allegro X APD toolbar, you can choose Transmission Line Calculator. 

You can use this calculator to help decide constraints and stackup for laminate-based PCB or Packages. You can calculate the correct stackup material and width/spacing to meet any requirements that may be later entered in a constraint. This is truly a calculated number and not a true field solver. 

The different types of calculations that the Transmission Line Calculator can provide are Microstrip, Embedded microstrip, Stripline, CPW (Coplanar), FGCPW (frequency-dependent Coplanar), Asymmetric stripline, Coupled microstrip (Differential Pair), Coupled stripline (Differential Pair), and Dual striplines. 

This feature is important for customers relying on fabricators/spreadsheets to provide this information or need to test a quick spacing/width as per the impedance value. 

Let us know your comments on this new feature in 23.1 Allegro X APD. 

Hi，

There are mang components in BGA ball side of flipchip package.

Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga  soldermask in allegro APD?

I only find space of compont to compont in APD DFA. 

In a package design, designers often need to perform degassing. This is typically done at the end of the design process before sending the design to the manufacturer.

Degassing is a process where you perforate power planes, voltage planes, and filled shapes in your design. Degassing holes let the gas escape from beneath the metal during manufacturing of the substrate. The perforations or holes for degassing are generally small, having a specified size and shape, and are spaced regularly across the surface of the plane. If the degassing process is not done, it may result in the formation of gas bubbles under the metal, which may cause the surface of the metal to become uneven. After you degas the design, it is recommended to perform electrical verification.

Allegro X APD has degassing features that allow users to automate the process and place holes in the entire shape.

In today’s topic, we will talk about how to avoid adding  degassing holes on a particular shape.

Sometimes, a designer may need to avoid adding degassing holes to a particular shape on a layer. All other shapes on the layer can have degassing holes but not this shape. Using the Layer Based Degassing Parameters option, the designer can set the degassing parameters for all shapes on the layer. Now, the designer would like to defer adding degassing holes for this particular shape.

You may wonder if there is an easy way to achieve this. We will now see how this can be done with the tool.

Once the degassing parameters are set, performing Display > Element on any of the shapes on that layer will show the degassing parameters set.

You can apply the Degas_Not_Allowed property to a shape to specify that degassing should not be performed on this shape, even if the degassing requirements are met. Select the shape and add the property as shown below.

Switch to Shape Edit application mode (Setup > Application mode > Shape Edit) and window-select all shapes on the layer. Then, right-click and select Deferred Degassing > All Off.

Now, all shapes on the layer will have degassing holes except for the shape which has the Degas_Not_Allowed property attached to it.

By default, a dielectric must separate each pair of conductor layers in the cross-section of a design. In rare cases, this does not represent the real, manufactured substrate.

If your design requires you to have conductor layers that are not separated by a dielectric (such as, for half-etch designs), there is a variable that needs to be set in Allegro X APD. You must set this by enabling the variable icp_allow_adjacent_conductors. This entry, and its location in the User Preferences Editor, are shown in the following image.

The Objects on adjacent conductor layers do not electrically connect together, automatically. A via must be used to establish the inter-layer connections.

When enabling this option, it is recommended to exercise caution because excluding dielectric layers from your cross-section can lead to inaccurate calculations, including the calculations for signal integrity and via heights. It is important that your cross-section accurately reflect the finished product to ensure the most accurate results possible. Any dielectric layers present in the manufactured part need to be in the cross-section for accurate extraction, 3D viewing, and so on.

Let us know your comments on the various designs that would require adjacent conductor layers.

When working on a complex design, it is common to have very many net ratlines. Quantities like 1000 ratlines are possible. It can result in a cluttered view while routing. Therefore, it is useful to make all other ratlines invisible while routing interactively. You would like to make all ratlines visible again when each route action is completed.

You can easily do this by enabling the Auto-blank other rats option during routing. When enabled, all rats other than the primary ones are suppressed during the Add Connect command.

Hello, SKILL experts. 

I'm studying SKILL language to build some useful function in APD+.

Now, I want to execute 'Import Sub-drawing' function in new form.

But I cannot find how to do execute APD+ embedded function in a field of new form. 

Has anyone experienced this or idea to solve this problem? 

Verisium Debug, the Cadence unified debug platform, offers a variety of debugging capabilities, including RTL debug, UVM testbench debug, UPF debug, and DMS debug. From IP to SoC level debug, the user can take the benefits of the rich debugging features to reduce the time for debug.

Not only the common and advanced debug features, Verisium Debug also provides Python-based interface API, which enables capabilities allowing users to customize functions with Verisium Debug Python API to access from design, waveform databases and add functions to Verisium Debug’s GUI for visualization purposes. With Verisium Debug’s Python API, users can turn repetitive works into automatic programs or reduce efforts to create in-house utilities with well-established infrastructure from Verisium Debug.

Here is an example of how the user uses Python API to create a customized function. Users can write a Python program to extract signals in a specific design scope and report the values of the extracted signals. From Fig 1., you can understand the procedure of the traversal steps.

1. Import Python library in Verisium Debug package.
2. Setup the database for traversal.
3. Search the scope with the hierarchy information in the design DB.
4. Query the signal list and the values of the signals.
5. Print out the results.

Fig 1. Procedure of Verisium Debug Python Program

The result from the Verisium Debug Python App can be used for post-process design checking or fed into other utilities in the design flow.

The concept is very straightforward. With Verisium Debug and the Python API environment enabled, you can easily query any information that is stored in the databases of Verisium Debug. The result can be outputted in text format, or you can also use the API to display the results back to Verisium Debug’s GUI.

The Verisium Debug Python API is an important capability and resource for Verisium Debug users. To make Verisium Debug Python API easier to access, from Verisium Debug 24.10 release, Verisium Debug introduced the new Verisium Debug Python App Store.

Fig 2. Verisium Debug App Store

The Python App Store includes ready-to-use Python App examples with the availabilities of original source code documents, which help the user to understand how to start writing an app that fits their use case.

Fig 3. Example apps in Verisium Debug App Store

The Verisium Debug Python App Store can also be used by a team as an app management system. App creators can share the developed apps across teams within their companies. The in-house created apps will become easy to manage, and engineers can easily access the apps from the central location, which makes it possible for users to see the updated available Verisium Debug Apps from the Verisium Debug App Store.

Check the following videos for more information about Verisium Debug Python API:

Customize Verisium Debug with Python API

Verisium Debug Customized Apps with Python API

In SoC development, the verification cycle is a crucial phase that ensures products meet their specifications and function correctly. However, the complexity of modern SoC projects, with their constant data flow, multiple validation teams working in parallel, and tight schedules, presents significant challenges. This article explores these challenges and introduces Verisium Manager as a solution that embodies the 'One Tool Fits All' concept. This means that Verisium Manager is designed to handle all aspects of the verification process for SoC development, from planning to coverage analysis to regression testing, thereby addressing the complex needs of SoC verification.

The Hurdles in Traditional Validation Cycles

 A typical validation process involves planning, coverage analysis, and regression testing. This complexity is compounded by using separate tools for each activity, leading to multiple control environments, APIs, and databases, not to mention the array of tool owners. Such fragmentation results in constant data transfer and translation between systems, from the planning tool to the coverage analysis tool and then to the regression testing tool. This continuous movement of data causes delays, system instability, poor user experiences, and, ultimately, a dip in the quality of the validation process.

The use of multiple platforms leads to inefficiency and reduced productivity. What's needed is a unified system that can streamline the workflow, simplify the verification process, and enhance its effectiveness.

Envisioning the Ideal Solution: Verisium Manager

 The cornerstone of an efficient validation cycle is integration and simplicity. The ideal solution is a singular platform that consolidates planning, coverage analysis, and regression management into one smooth, unified process. Verisium Manager emerges as this much-needed solution, encompassing all the functionalities necessary to streamline the validation process. Its comprehensive nature instills confidence in its ability to handle all aspects of the verification cycle. It can be fully customized to address and enforce any validation methodology and can facilitate smooth integration into any customer environment.

Features that stand out in Verisium Manager include: 

• Unified Workflow: It acts as a single cockpit from which all activities are orchestrated, ensuring the validation teams' work is uninterrupted and seamlessly integrated.
• Customization and Integration: Verisium Manager supports customizing test-plan structures and mapping results per project, ensuring a perfect fit for various project requirements. Its ability to smoothly integrate into the project's environment and compute platforms is unparalleled.
• Support for Continuous Updates and Migration: The tool accommodates constant updates to project data and supports the migration of legacy data, ensuring that no historical data is lost in the transition to a new system.

Addressing Project-Specific Needs

 Verisium Manager recognizes diversity in different projects and offers project-specific solutions, including:

 Enforcing Project Test-Plan Structures and Attributes: It supports and enforces each project's unique test-plan structure and mapping guidelines.

• Unified Data Views and Measurements: Verisium Manager promotes a unified view of data across all teams and enforces unified measurements, ensuring consistency and clarity in the validation process.
• Enabling Project-Specific Actions and Integrations: The tool is designed to support project-specific actions directly from its graphical user interface and allows for smooth integration with in-house databases, dashboards, and the project execution stack.

Verisium Manager is the epitome of efficiency in software/hardware validation. Its differentiating features, such as support for customization, unified data view, and comprehensive coverage and regression requirements, make it an indispensable tool for any validation team looking to elevate their workflow.

Allegro X System Capture offers a complete ecosystem for library development. This post introduces the latest DE-HDL Library Development using System Capture course in which you learn how to create different library objects. As a librarian, you often work with numerous libraries. Your tasks include creating or modifying symbols for libraries. To use Allegro X System Capture to create a library, you can follow the steps in the following flowchart: Let’s go through each step in detail. Setting the CDS_SITE Variable Before you start library development for a new project, set the CDS_SITE system environment variable. This step is required to access libraries and other configuration files. Creating a Project in Allegro X System Capture The next step is to create a project in Allegro X System Capture. Adding a Library to the Project Symbol development consists of creating symbol graphics, electrical data, and properties used by different tools in the PCB design flow. To add a library to a project, first create a library in the Libraries pane of the Project e xplorer. Creating Library Symbols The library development process supports the creation of various types of symbols. Creating a Symbol with Multiple Views You can generate multiple views of the same symbol using the Duplicate command. For example, a discrete symbol, such as a resistor, can have multiple views, as shown in the following image: Creating a Split Symbol For advanced designs, you often need to create library symbols and break them into multiple sections to support the design process. When a symbol shows all the logical pins in the physical package, it is called a single-section or flat symbol. Many large ICs have several pins and the symbols need to fit on a single schematic page. One workaround is to use vector pin names on a symbol to reduce its size, although manufacturers prefer schematics that show each pin. You can divide these high-pin count devices into smaller pieces, where each piece is a separate version of the part. Such parts are referred to as split parts or multi-section symbols. For multi-section symbols, you can create two types of split parts—symmetrical and asymmetrical. Symmetrical Split Symbols A symmetrical split symbol has only one symbol graphic, which holds two or more identical logic symbols, each with its own unique physical pin numbers. You can create a symmetrical split symbol using the Duplicate Section icon in the canvas window. Each symbol section contains the same set of pins but different pin numbers, as shown in the following image: Asymmetrical Split Symbols An asymmetrical split symbol is a symbol whose physical package contains one or more unique schematic symbols. You can create an asymmetrical split symbol by clicking the New Section icon in the canvas window. Asymmetrical symbols have a unique set of logical pins, as shown in the following image: Creating Symbols Using the Spreadsheet Interface To simplify the development of large symbols, Allegro X System Capture has a Spreadsheet Interface . You can copy from a spreadsheet into the interface. This saves time and helps minimize errors introduced by manual entry. In conclusion, the DE-HDL library development using Allegro X System Capture course involves several critical steps and supports various symbol creation techniques. This course helps librarians create and modify symbols effortlessly and deepens their understanding of library development within Allegro X System Capture. To learn more about this topic, enroll in the DE-HDL Library Development using Allegro X System Capture course on the Cadence Support portal . Click the training byte link now or visit Cadence Support and search for training bytes under Video Library. If you find the post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design: DE-HDL Library Development using Allegro X System Capture (Online). You can become Cadence Certified once you complete the course. Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise. To find out more, see the blog post Take a Cadence Masterclass and Get a Badge . You might also be interested in the training Learning Map that guides you through recommended course flows as well as tool experience and knowledge-level training modules. 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As a verification engineer, you’re surely looking for ways to automate the debugging process. Have you developed your own scripts to ease specific debugging steps that tools don’t offer? Working with scripts locally and manually is challenging—so is reusing and organizing them. What if there was a way to create your own app with the required functionality and register it with the tool? The answer to that question is “Yes!” The Verisium Debug Python App Store lets you instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. Join me, Principal Education Application Engineer Bhairava Prasad, for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps, learn about them, install or uninstall them, and even customize existing apps. Date and Time Wednesday, November 20, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within one hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Like this topic? Take this opportunity and register for the free online course related to this webinar topic: Verisium Debug Training To view our complete training offerings, visit the Cadence Training website Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. Related Courses Xcelium Simulator Training Course | Cadence Related Blogs Unveiling the Capabilities of Verisium Manager for Optimized Operations - Verification - Cadence Blogs - Cadence Community Verisium SimAI: SoC Verification with Unprecedented Coverage Maximization - Corporate News - Cadence Blogs - Cadence Community Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput - Verification - Cadence Blogs - Cadence Community Related Training Bytes Introducing Verisium Debug (Video) (cadence.com) Introduction to UVM Debug of Verisium Debug (Video) (cadence.com) Verisium Debug Customized Apps with Python API Please see course learning maps a visual representation of courses and course relationships. Regional course catalogs may be viewed here . *If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help .