Display Stream Compression (DSC) is a lossless or near-lossless image compression standard developed by the Video Electronics Standards Association (VESA) for reducing the bandwidth required to transmit high-resolution video and images. DSC compresses video streams in real-time, allowing for higher resolutions, refresh rates, and color depths while minimizing the data load on transmission interfaces such as DisplayPort, HDMI, and embedded display interfaces.

Why Is DSC Needed?

In the ever-evolving landscape of display technology, the pursuit of higher resolutions and better visual quality is relentless. As display capabilities advance, so do the challenges of managing the immense amounts of data required to drive these high-performance screens. This is where DSC steps in. DSC is designed to address the challenges of transmitting ultra-high-definition content without sacrificing quality or performance. As displays grow in resolution and capability, the amount of data they need to transmit increases exponentially. DSC addresses these issues by compressing video streams in real-time, significantly reducing the bandwidth needed while preserving image quality.
 

DSC Use in End-to-end System

DSC Key Features

• Encoding tools:
  • Modified Median-Adaptive Prediction (MMAP)
  • Block Prediction (BP)
  • Midpoint Prediction (MPP)
  • Indexed color history (ICH)
  • Entropy coding using delta size unit-variable length coding (DSU-VLC)

• The DSC bitstream and decoding process are designed to facilitate the decoding of 3 pixels/clock in practical hardware decoder implementations. Hardware encoder implementations are possible at 1 pixel/clock.
• DSC uses an intra-frame, line-based coding algorithm, which results in very low latency for encoding and decoding.

DSC encoding algorithm
 

• Compression can be done to a fractional bpp. The compressed bits per pixel ranges from 6 to 63.9375.
• For validation/compliance certification of DSC compression and decompression engines, cyclic redundancy checks (CRCs) are used to verify the correctness of the bitstream and the reconstructed image.
• DSC supports more color bit depths, including 8, 10, 12, 14, and 16 bpc.
• DSC supports RGB and YCbCr input format, supporting 4:4:4, 4:2:2, and 4:2:0 sampling.
• Maximum decompressor-supported bits/pixel values are as listed in the Maximum Allowed Bit Rate column in the table below

• DP DSC Source device shall program the bit rate within the range of Minimum Allowed Bit Rate column in the table:

Summary

Display Stream Compression (DSC) is a technology used in DisplayPort to enable higher resolutions and refresh rates while maintaining high image quality. It works by compressing the video data transmitted from the source to the display, effectively reducing the bandwidth required. DSC uses a visually lossless algorithm, meaning that the compression is designed to be imperceptible to the human eye, preserving the fidelity of the image. This technology allows for smoother, more detailed visuals at higher resolutions, such as 4K or 8K, without requiring a significant increase in data bandwidth.

More Information

• Cadence has a very mature Verification IP solution. Verification over many different configurations can be used with DisplayPort 2.1 and DisplayPort 1.4 designs, so you can choose the best version for your specific needs.
• The DisplayPort VIP provides a full-stack solution for Sink and Source devices with a comprehensive coverage model, protocol checkers, and an extensive test suite.
• More details are available on the DisplayPort Verification IP product page, Simulation VIP pages.
• If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com

Verisium SimAI App harnesses the power of machine learning technology with the Cadence Xcelium Logic Simulator - the ultimate breakthrough in accelerating verification closure. It builds models from regressions run in the Xcelium simulator, enabling the generation of new regressions with specific targets. The Verisium SimAI app also features cousin bug hunting, a unique capability that uses information from difficult-to-hit failures to expose cousin bugs. With these advanced machine learning techniques, Verisium SimAI offers the potential for a significant boost in productivity, promising an exciting future for our users.

Figure 1: Regression compression and coverage maximization with Verisium SimAI 

What can I do with Verisium SimAI?

You can exercise different use cases with Verisium SimAI as per your requirements. For some users, the goal might be regression compression and improving coverage regain. Coverage maximization and hitting new bins could be another goal. Other users may be interested in exposing hard-to-hit failures, bug hunting for difficult to find issues. Verisium SimAI allows users to take on any of these challenges to achieve the desired results.

Let's go into some more details of these use cases and scenarios where using SimAI can have a big positive impact.

1. Using SimAI for Regression Compression and Coverage Regain

Unlock up to 10X compute savings with SimAI!

Verisium SimAI can be used to compress regressions and regain coverage. This flow involves setting up your regression environment for SimAI, running your random regressions with coverage and randomization data followed by training, and finally, synthesizing and running the SimAI-generated compressed regressions. The synthesized regression may prune tests that do not help meet the goal and add more runs for the most relevant tests, as well as add run-specific constraints. This flow can also be used to target specific areas like areas involving a high code churn or high complexity.

You can check out the details of this flow with illustrative examples in the following Rapid Adoption Kits (RAK) available on the Cadence Learning and Support Portal (Cadence customer credentials needed):

• Using SimAI with vManager (For Regression Compression and Coverage Regain) (RAK) 
• Using SimAI with a Generic Runner (For Regression Compression and Coverage Regain) (RAK)

2. Using SimAI for Coverage Maximization and Targeting coverage holes

Reduce your Functional Coverage Holes by up to 40% using SimAI!

Verisium SimAI can be used for iterative coverage maximization. This is most effective when regressions are largely saturated, and SimAI will explicitly try to hit uncovered bins, which may be hard-to-hit (but not impossible) coverage holes. This is achieved using iterative learning technology where with each iteration, SimAI does some exploration and determines how well it performed. This technique can also be used for bug hunting by using holes as targets of interest.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Coverage Maximization - vManager flow (RAK) 
• Using SimAI for Coverage Maximization - Generic Runner Flow (RAK)

3. Using SimAI for Bug Hunting

Discover and fix bugs faster using SimAI!

Verisium SimAI has a new bug hunting flow which can be used to target the goal of exposing hard-to-hit failure conditions. This is achieved using an iterative framework and by targeting failures or rare bins. The goal to target failures is best exercised when the overall failure rate is typically low (below 5%). Iterative learning can be used to improve the ability to target specific areas. Use the SimAI bug hunting use case to target rare events, low hit coverage bins, and low hit failure signatures.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Bug Hunting with vManager (RAK) 
• Using SimAI for Bug Hunting – Generic runner flow (RAK) 

Unlock compute savings, reduce your functional coverage holes, and discover and fix bugs faster with the power of machine learning technology now enabled by Verisium SimAI!

Please keep visiting  https://support.cadence.com/raks to download new RAKs as they become available.

Please note that you will need the Cadence customer credentials to log on to the Cadence Online  Support  https://support.cadence.com/, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies.

Happy Learning!

DDR5 DIMM Architectures The DDR5 generation of Double Data Rate DRAM memories has experienced rapid adoption in recent years. In particular, the JEDEC-defined DDR5 Dual Inline Memory Module (DIMM) cards have become a mainstay for systems looking for high-density, high-bandwidth, off-chip random access memory[1]. Within a short time, the DIMM architecture evolved from an interconnected hierarchy of only SDRAM memory devices (UDIMM[2]) to complex subsystems of interconnected components (RDIMM/LRDIMM/MRDIMM[3]). DIMM Designs and Popular Verification Use Cases The growing complexity of the DIMMs presented a challenge for pre-silicon verification engineers who could no longer simply validate against single DDR5 SDRAM memory models. They needed to consider how their designs would perform against DIMMs connected to each channel and operating at gigahertz clock speeds. To address this verification gap, Cadence developed DDR5 DIMM Memory Models that encapsulated all of the architectural complexities presented by real-world DIMMs based on a robust, easy-to-use, easy-to-debug, and easy-to-reconfigure methodology. This memory-subsystem-in-a-single-instance model has seen explosive adoption among the traditional IP Developer and SOC Integrator customers of Cadence Memory Models. The Cadence DIMM models act as a single unit with all of the relevant DIMM components instantiated and interconnected within, and with all AC/Timing parameters among the various components fully matched out-of-the-box, based on JEDEC specifications as well as datasheets of actual devices in the market. The typical use-case for the DIMM models has been where the DUT is a DDR5 Memory Controller + PHY IP stack, and the validation plan mandated compliance with the JEDEC standards and Memory Device vendor datasheets. Unique Use Case for the DIMM Discrete Component Models Although the Cadence DIMM models have enjoyed tremendous proliferation because of their cohesive implementation and unified user API, the actual DIMM Models are built on top of powerful, flexible discrete component models, each of which was designed to stand on its own as a complete SystemVerilog UVM-based VIP. All of these discrete component models exist in the Cadence VIP Catalog as standalone VIPs, complete with their own protocol compliance checking capabilities and their own configuration mappings comprehensively modeling individual AC/Timing parameters. Because of this deliberate design decision, the Cadence DIMM Discrete Component Models can support a unique use-case scenario. Some users seek to develop IC Designs for the various DIMM components. Such users need verification environments that can model the individual components of a DIMM and allow them the option to replace one or another component with their Component Design IP. They can then validate that their component design is fully compatible with the rest of the components on the DIMM and meets the integrity of the overall DIMM compliance with JEDEC standards or Memory Vendor datasheets. The Cadence Memory VIP portfolio today includes various examples that demonstrate how customers can create DIMM “wrappers” by selecting from among the available DIMM discrete component models and “stitching” them together to build their own custom testbench around their specific Component Design IP. A Solution for Unique Component Scenarios The Cadence DDR5 DIMM Memory Models and DIMM Discrete Component Models can provide users with a flexible approach to validating their specific component designs with a fully populated pre-silicon environment. Augmented Verification Capabilities When the DIMM “wrapper” model is augmented with the Cadence DFI VIP[4] that can simulate an MC+PHY stack and offers a SystemVerilog UVM test API to the verification engineer, the overall testbench transforms into a formidable pre-silicon validation vehicle. The DFI VIP is designed as a combination of an independent DFI MC VIP and a DFI PHY VIP connected to each other via the DFI Standard Interface and capable of operating seamlessly as a single unit. It presents a UVM Sequence API to the user into the DFI MC VIP with the Memory Interface of the PHY VIP connected to the DIMM “wrapper” model. With this testbench in hand, the user can then fully take advantage of the UVM Sequence Library that comes with the DFI VIP to enable deep validation of their Component Design inside the DIMM “wrapper” model. Verification Capabilities Further Enhanced A possible further enhancement comes with the potential addition of an instance of the Cadence DIMM Memory Model in a Passive Monitor mode at the DRAM Memory Interface. The DIMM Passive Monitor consumes the same configuration describing the DIMM “wrapper” in the testbench, and thus can act as a reference model for the DIMM wrapper. If the DIMM Passive Monitor responds successfully to accesses from the DFI VIP, but the DIMM wrapper does not, then it exposes potential bugs in the DUT Components or in the settings of their AC/Timing parameters inside the DIMM wrapper. Debuggability, Interface Visibility, and Protocol Compliance One of the key benefits of the DIMM Discrete Component Models that become manifest, whether in terms of the unique use-case scenario described here, or when working with the wholly unified DDR5 DIMM Memory Models, is the increased debuggability of the protocol functionality. The intentional separation of the discrete components of a DIMM allows the user to have full visibility of the memory traffic at every datapath landmark within a DIMM structure. For example, in modeling an LRDIMM or MRDIMM, the interface between the RCD component and the SDRAM components, the interface between the RCD component and the DB components, and the interface between the SDRAM components and the DB components—all are visible and accessible to the user. The user has full access to dump the values and states of the wire interconnects at these interfaces to the waveform viewer and thus can observe and correlate the activity against any protocol violations flagged in the trace logs by any one or more of the DIMM Discrete Component Models. Access to these interfaces is freely available when using the DIMM Discrete Component Models. On the unified DDR5 DIMM Memory Models, a feature called Debug Ports enables the same level of visibility into the individual interconnects amidst the SDRAM components, RCD components, and DB components. When combined with the Waveform Debugger[5] capability that comes built-in with the VIPs and Memory Models offered by Cadence and used with the Cadence Verisium Debug[6] tool, the enhanced debuggability becomes a powerful platform. With these debug accesses enabled, the user can pull out transaction streams, chip state and bank state streams, mode register streams, and error message streams all right next to their RTL signals in the same Verisium Debug waveform viewer window to debug failures all in one place. The Verisium Debug tool also parses all of the log files to probe and extract messages into a fully integrated Smart Log in a tabbed window fully hyperlinked to the waveform viewer, all at your fingertips. A Solution for Every Scenario Cadence's DDR5 DIMM Memory Models and DIMM Discrete Component Models , partnered with the Cadence DFI VIP, can provide users with a robust and flexible approach to validating their designs thoroughly and effectively in pre-silicon verification environments ahead of tapeout commitments. The solution offers unparalleled latitude in debuggability when the Debug Ports and Waveform Debugger functions of the Memory Models are switched on and boosted with the use of the Cadence Verisium Debug tool. [1] Shyam Sharma, DDR5 DIMM Design and Verification Considerations , 13 Jan 2023. [2] Shyam Sharma, DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM) , 23 Sep 2024. [3] Kos Gitchev, DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers , 26 Aug 2024. [4] Chetan Shingala and Salehabibi Shaikh, How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device? , 29 Mar 2022. [5] Rahul Jha, Cadence Memory Models - The Gold Standard , 15 Apr 2024. [6] Manisha Pradhan, Accelerate Design Debugging Using Verisium Debug , 11 Jul 2023.

Hello,

I'm using OrCad 17.2 and in the company I'm wokring at there was a change in the database folder (from driver F to G for example) and it effects the option of synchronise using the Part Manager. and changing manually each part in the Desgin Cahce can be a pain.

Is there any way I can make a TCL script that will run and replace a part cahce with other? Better if I can call from a table to read, and write from other collum.

I would really be happy for an example.

Thanks for the help.

Hi 

I have a Xtensa compiler issue that the compilation for switch case would be optimized in some patterns and leads to unexpected result. I cross-checked the assembly code and found that such compiler optimization seems to be similar to the tree-switch-conversion feature in GCC compiler

• https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html
  -ftree-switch-conversion
      Perform conversion of simple initializations in a switch to initializations from a scalar array. This flag is enabled by default at -O2 and highe

Unfortunately I don't find any similar compiler option(like -fno-tree-switch-conversion) in Xtensa compiler(XCC) to enable/disable such feature and such feature seems like enabled in XCC by default even if I'm using -O0 for the least optimization.

I'm wondering if there's any possible solution to permanently disable such feature in XCC?

PS: The release version of XCC compiler I'm using is RD-2012.5

Thanks!

use the DBO function DboLib_RepalceCache to do the job of "Replace cache" 

in order to easy the job ,  type the code below . the code is a wrapper of the function metioned above

set lStatus [DboState]
set lSession $::DboSession_s_pDboSession
DboSession -this $lSession
set lDesignsIter [$lSession NewDesignsIter $lStatus]
set lDesign [$lDesignsIter NextDesign $lStatus]
set lNullObj NULL

set oldLibName [DboTclHelper_sMakeCString "E:\PROJECT_WORKLIB.OLB"]
set newLibName [DboTclHelper_sMakeCString "E:\MCU_PARTS_LIB.OLB"]

#DboLib_ReplaceCache wrapper
proc ReplaceCacheByName {partName} {
    global oldLibName
    global newLibName
    global lDesign
    set lPartStr [DboTclHelper_sMakeCString $partName]
    #set lNewStr [DboTclHelper_sMakeCString $newName]
    $lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1
}

then use the tcl command like below to do the real job :

ReplaceCacheByName "CL10B104KB8NNNC_C12"

Hello Fellow PCB Designers,

We have a 10 layer PCB design that originated in Pads and was converted over to Allegro 17.4, this is an old design but is manufacturable and works perfectly fine.  When I try to generate a Gerber for the Top or Bottom layers

the Gerber comes out fine.  But Most of the middle layers are Etch's and via's for power and grounds, but the Gerber's come mostly blank, there might be some details, but in the Gerber view everything is displayed correctly.

The design does have many close spacings, I have not changed anything in the constrains manager yet, turned off a lot of the DRC's, but thinking there might be something wrong with the constrains.

  I find that the CSet is set to 2_18, not sure yet what this means, also there are many of these definitions, PCS 3,4,5,ect, are the same as CSet 2_18 any suggestions would be great, we are currently looking into this, have seen

that even small change in constraint manager can cause long processing and even Allegro crashing, this is a large project.

Thanks Much, Thanks, Mike Pollock.

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

We are trying to run compilation, elab and sim with command xrun -r -u alu, where alu is one of the units to execute. we are getting the following errors.

1) xmsim: *E,DLMKDF: Unable to add default DEFINE std       /home/xxxx/Cad/xcelium/tools/inca/files/STD.
    xmsim: *E,DLMKDF: Unable to add default DEFINE synopsys  /home/xxxx/Cad/xcelium/tools/inca/files/SYNOPSYS

2) xmsim: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.

What is the purpose of hdl.var

3) xmsim: *F,NOSNAP: Snapshot 'alu' does not exist in the libraries.

I cannot see in log files, which libraries is it referring to??

Any one request you to help on how to debug these.

Hi

I have tried using "add net constraints" command to place one-cold constraints on a tristate enable bus. In the command line we need to specify the "net pathname" on which the constraints are to be enforced.

The bus here is 20-bit. How should the net pathname be specified to make this 20-bit bus signals one_hot or one_cold.

The bus was declared as follows:
ten_bus [19:0]

The command I used was

add net constraints one_hot /ren_bus[19]

What would the above command mean?
Should we not specify all the nets' pathnames on the bus?
Is it sufficient to specify the pathname of one net on the bus?
I could not get much info regarding the functionality of this command. I would be obliged if anyone can throw some light.

Thanks
Prasad.

Please include a brief summary of how to use it.

In a nutshell, tags allows you to navigate through program code distributed over multiple files effectively. e.g if you see a function call or a struct in e-code and want to "jump" to the definition (which may be in a different file) then you just hit CTRL+] in Vim! Pressing CTRL+t will take you back where you came from. Check out http://vim.wikia.com/wiki/Browsing_programs_with_tags#Using_tags if you want to learn more about how to use tags with Vim.

This utility can generate tags file for your e files. It can either walk through e import order, a directory recursively or all directories on SPECMAN_PATH recursively! The tags file will have tags for struct, unit, types, events, defines, fields, variables, etc.

For help and some examples, just run ctags4e -help.

Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more)

Melika Roshandell talks with David Malinak in a Microwaves & RF QuickChat video about the thermal challenges in today’s complex electronic designs and how the Celsius solver uniquely addresses them.(read more)

By combining finite element analysis with computational fluid dynamics, designers can perform complete thermal system analysis using a single tool.(read more)

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this blog.(read more)

I am trying to figure out the most efficient workflow for adding test points. My use case involves adding ~100 or so SMT pads at the bottom for bed-of-nails ICT test that are required to be on a test point grid. A lot of the nets are on the top or from inner layers and so have to be brought to the bottom using stubs. I'm used to Xpediiton workflow of being able to set a test point padstack, set a test point grid, and then select a net, add the test point to the bottom layer on the grid with that net attached and then route the stub with gridless routing.

In Orcad, it seems I need to route the stub, switch layer pairs to be both bottom once I bring the stub to the bottom and then change the grid to be the test point grid and then add the test point on the grid. It requires a lot of clicks, very mistake prone requiring lots of oops and very slow for 100+ test points to be brought out at the bottom. 

I'm sure there is a better way that is used by folks with a lot of Orcad experience. Any suggestions?

The world of electronics design thrives on efficient tools that bridge the gap between concept and silicon. Virtuoso Digital Implementation is a powerful ally for mixed-signal designs, which integrate both analog and digital components. This blog post will examine Virtuoso Digital Implementation's capabilities and explore how it can streamline your mixed-signal design workflow.

Virtuoso Digital Implementation in a Nutshell

Virtuoso Digital Implementation is a license package within the Cadence Virtuoso Design Platform. It offers a streamlined RTL-to-GDSII flow to implement smaller digital blocks within a mixed-signal design environment. Here's what makes Virtuoso Digital Implementation stand out:

• Focus on Small Digital Blocks: Optimized for digital blocks with an instance count of up to 50,000 (expandable to 150,000 with specific configurations), Virtuoso Digital Implementation is ideal for integrating digital logic into your analog-centric design.
• Leveraging Industry Leaders: Virtuoso Digital Implementation utilizes cut-down versions of the renowned Cadence Genus Synthesis Solution and Innovus Implementation System under the hood. This ensures you get access to proven technologies for logic optimization and place-and-route.
• Seamless Integration with the Virtuoso Environment: Virtuoso Digital Implementation's key advantage is its tight integration with the Virtuoso Layout Suite. You can launch the synthesis and place-and-route tools directly from the Virtuoso environment, eliminating the need to switch between platforms.

Benefits of Using Virtuoso Digital Implementation

 By incorporating Virtuoso Digital Implementation into your mixed-signal design flow, you can get several benefits:

• Simplified Workflow: Virtuoso Digital Implementation offers a centralized environment for both digital block implementation and layout editing within the Virtuoso environment. This reduces context switching and streamlines the design process.
• Faster Time-to-Market: Virtuoso Digital Implementation's streamlined workflow can significantly reduce design turnaround times, allowing you to get your product to market quicker.
• Improved Design Quality: Leveraging industry-leading synthesis and place-and-route engines from Cadence ensures high-quality digital block implementation within your mixed-signal design.

Who Should Consider Virtuoso Digital Implementation?

 Virtuoso Digital Implementation is a valuable tool for anyone working on mixed-signal designs with smaller digital blocks. It's particularly well-suited for:

• Analog IC designers who need to integrate digital logic into their designs.
• Circuit design teams working on mixed-signal applications like data converters, power management ICs, and RF transceivers.

Virtuoso Digital Implementation provides a compelling solution for designers working on mixed-signal projects. Its streamlined workflow, tight integration with the Virtuoso design platform, and access to proven digital design tools can significantly improve design efficiency and time-to-market. Virtuoso Digital Implementation is worth considering if you're looking to optimize your mixed-signal design flow.

I am here to help and guide you on how to learn more about Virtuoso Digital Implementation flow.

Welcome to Virtuoso Digital Implementation, an online course recently released. This course teaches implementing digital blocks using Cadence tools based on the Virtuoso Digital Implementation flow. Also, you can download a lab database after the lecture and get hands-on experience in each stage.

Want to Enroll in this Course?

We organize this Virtuoso Digital Implementation training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

• Log on to cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for Virtuoso Digital Implementation using the search bar.
• Select the course and click Enroll.

And don't forget to obtain your Digital Badge after completing the training!

Related Resources

Online Courses

• Cadence RTL-to-GDSII Flow v6.0
• Virtuoso Digital Implementation Training

Training Byte Videos

• How Do You Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus?

Happy Learning!

Russia remains fDi’s most diversified commodity economy, while second ranked Brazil has displaced Ukraine into third place. Cathy Mullan reports.

Foreign investment into Serbia is growing at a healthy pace thanks to its attractive automotive manufacturing industry and highly regarded free zones.

Mohammad Nafees Zakaria, Pakistan’s UK high commissioner, talks about his country’s potential for foreign investors.

The trend towards the vetting of foreign investment, especially projects that involve advanced technology and national data or pose potential security threats, is on the rise. David Gabathuler and Matthew T West give a trans-Atlantic perspective.

The UAE followed Singapore’s swift reaction to combat Covid-19, to preserve the health of its citizens. Now moves are in place to tackle the country’s economic wellbeing.

The dominant priority at major banks is the maximisation of short-term profits rather than serving the public interest

Jeep Wrangler sets the bar for off-roading capability Larger Ford Bronco has a more modern suspension Both SUVs have removable doors and tops When Ford relaunched the Bronco for the 2021 model year, it had one target in its sights: The Jeep Wrangler. The Wrangler has been the American benchmark for off-roading capability in the 80-plus years since...

Want a pickup truck but don’t want the hangups of a full-size truck? Ford has you covered with two compelling pickup options. The Ford Ranger midsize pickup truck has a crew cab and 5-foot bed like the F-150, and it also has a Raptor off-road model. With a 7,500-pound towing capacity, it can’t tow or haul as much as an F-150, but...

Maserati Shamal restomod project in the works Restomod will use Biturbo Coupe body and Ghibli S twin-turbocharged V-6 Production to be limited to 33 units The Maserati Shamal launched in 1990 didn't see much success, despite featuring a body penned by the legendary Marcello Gandini, and a twin-turbocharged V-8 under the hood. It was devised when...

Australian urban planning and design and economics consultancy Cistri is using its evidence-based insights to help Asian developers design and plan urban communities that enhance quality of life.

American entertainment studio Bento Box Entertainment has partnered with Australia’s Princess Pictures to form a new animation studio

Israel Aerospace Industries (IAI) has entered into a joint venture with Australia’s Bis to launch Auto-mate, a new company that will provide autonomous systems to the mining industry.

India is one of Australia’s fastest growing tourism markets. Tourism businesses can realise the potential of the Indian market by learning about travellers’ culture and service expectations.

Google Gemini may be getting its own iOS app

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Today Australia has been reincluded on China’s list of approved outgoing group travel destinations.

Auxin Solar named more than a dozen companies in its petition to Commerce Department officials.

Senators heard three hours of testimony from anti-wind sources and just one hour from proponents of renewable energy

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the third quarter of 2023 closed with 359.3 million domain name registrations across all top-level domains (TLDs), an increase of 2.7 million domain name registrations, or 0.8%, compared to the second quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 359.3 Million Domain Name Registrations in the Third Quarter of 2023 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the fourth quarter of 2023 closed with 359.8 million domain name registrations across all top-level domains (TLDs), an increase of 0.6 million domain name registrations, or 0.2%, compared to the third quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 359.8 Million Domain Name Registrations in the Fourth Quarter of 2023 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the first quarter of 2024 closed with 362.4 million domain name registrations across all top-level domains (TLDs), an increase of 2.5 million domain name registrations, or 0.7%, compared to the fourth quarter of 2023. Domain name registrations also […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.4 Million Domain Name Registrations in the First Quarter of 2024 appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the second quarter of 2024 closed with 362.4 million domain name registrations across all top-level domains (TLDs), unchanged compared to the first quarter of 2024. Domain name registrations increased by 5.8 million, or 1.6%, year over year. Check […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.4 Million Domain Name Registrations in the Second Quarter of 2024 appeared first on Verisign Blog.

Over the past several weeks, there has been significant discussion about Verisign and its management of the .com top-level domain (TLD) registry. Much of this discussion has been distorted by factual inaccuracies, a misunderstanding of core technical concepts, and misinterpretations regarding pricing, competition, and market dynamics in the domain name industry. Billions of internet users […]

The post Setting the Record Straight – Myths vs. Facts about .com appeared first on Verisign Blog.

Today, the latest issue of The Domain Name Industry Brief Quarterly Report was released by DNIB.com, showing the third quarter of 2024 closed with 362.3 million domain name registrations across all top-level domains (TLDs), a decrease of 0.1 million domain name registrations, or less than 0.05%, compared to the second quarter of 2024. Domain name […]

The post Domain Name Industry Brief Quarterly Report: DNIB.com Announces 362.3 Million Domain Name Registrations in the Third Quarter of 2024 appeared first on Verisign Blog.

This GFN Thursday, the GeForce NOW Priority membership is getting enhancements and a fresh name to go along with it. The new Performance membership offers more GeForce-powered premium gaming — at no change in the monthly membership cost. Gamers having a hard time deciding between the Performance and Ultimate memberships can take them both for Read Article

The NVIDIA app — officially releasing today — is a companion platform for content creators, GeForce gamers and AI enthusiasts using GeForce RTX GPUs.

Lifelike digital humans engage with audiences in real time. Autonomous systems streamline complex logistics. And AI-driven language tools break down communication barriers on the fly. This isn’t sci-fi. This is Tokyo’s startup scene. Supercharged by AI — and world-class academic and industrial might — the region has become a global innovation hub. And the NVIDIA Read Article

The next technology revolution is here, and Japan is poised to be a major part of it. At NVIDIA’s AI Summit Japan on Wednesday, NVIDIA founder and CEO Jensen Huang and SoftBank Chairman and CEO Masayoshi Son shared a sweeping vision for Japan’s role in the AI revolution. Speaking in Tokyo, Huang underscored that AI Read Article

Creating Connections: The Role of Community in Minnesota-Japan Relations Creating Connections: The Role of Community in Minnesota-Japan Relations