The Alumni Spotlight is a monthly feature in Bridges, highlighting College of Education alumni who are making a difference in the lives of the people around them. This edition features Rob Longwell-Grice, who draws upon personal experience to help students who are also the first in their families to pursue a college degree.

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Katarzyna Growiec, Jakub Growiec and Bogumił Kamiński: We study the impact of endogenous creation and destruction of social ties in an artificial society on aggregate outcomes such as generalized trust, willingness to cooperate, social utility and economic performance. To this end we put forward a computational multi-agent model where agents of overlapping generations interact in a dynamically evolving social network. In the model, four distinct dimensions of individuals’ social capital: degree, centrality, heterophilous and homophilous interactions, determine their generalized trust and willingness to cooperate, altogether helping them achieve certain levels of social utility (i.e., utility from social contacts) and economic performance. We find that the stationary state of the simulated social network exhibits realistic small-world topology. We also observe that societies whose social networks are relatively frequently reconfigured, display relatively higher generalized trust, willingness to cooperate, and economic performance – at the cost of lower social utility. Similar outcomes are found for societies where social tie dissolution is relatively weakly linked to family closeness.

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Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution, a next-generation RTL synthesis tool that takes physical awareness in some new directions.

Here are four important things to know about Genus technology:

• A massively parallel architecture improves turnaround time by up to 5X while maintaining quality of results
• The Genus solution synthesizes up to 10M+ instances flat without impacting power, performance and area (PPA)
• The Genus solution provides tight correlation with the Innovus Implementation System, using the same placement and routing algorithms
• Globally focused PPA optimization saves up to 20% datapath area and power

Compared to previous-generation products such as the Cadence Encounter RTL Compiler Advanced Physical Option, the Genus solution approaches physical synthesis in a different way. The Encounter solution applied physical optimization “at the tail end of synthesis,” said David Stratman, senior principal product manager at Cadence. “We were doing a final incremental push, but we could only do so much, since we had locked in a lot of the earlier steps from a logical-only synthesis perspective.”

Genus Synthesis Solution supports the physical synthesis features in the previous Encounter solution, but it also brings the full physical scope upstream to RTL logic designers. “It’s going to enable the unit-level RTL designer to gain the benefits of physical synthesis without having to understand it,” Stratman said. As an example, users can apply generic (unmapped) placement at the earliest stages of synthesis, using a lightweight version of the Innovus placement engine. The bottom line: “Genus is a full solution where every step of synthesis can be done physically.”

Getting Massively Parallel

If you bring physical data into synthesis, you need a way to improve capacity and runtimes, especially with today’s gigantic advance-node SoCs. That’s why a massively parallel architecture is the cornerstone of the Genus solution. In this way, the Genus solution is following in the footsteps of the Innovus Implementation System, which also provides a massively parallel architecture.

Both the Innovus and Genus solutions can handle blocks of 10M instances flat. Given that SoCs today may have up to 100M instances, and often up to 50-100 top-level blocks, this is an important capability. Many tools today will only handle blocks of 1M instances. As a result, design teams often have to constrain block sizes.

Genus technology offers timing-driven, multi-level design partitioning across multiple threads and machines. It enables a near-linear runtime scaling without impacting PPA. According to Stratman, the Genus solution will scale well beyond 64 CPUs for a large design, with a “sweet spot” around 8-20 CPUs for today’s typical block sizes. Runs that used to take days, he noted, can now be done in hours.

As shown below, Genus technology leverages parallelism at three levels. The Genus solution can distribute design partitions to multiple threads or CPUs, and also supports local algorithm-level multithreading on each machine with shared memory. An adaptive scheduler ensures the best use of the available CPUs.

Fig. 1 – Genus Synthesis Solution provides three levels of parallelism

With its massive parallelism, Stratman said, Genus technology can obtain production-level quality of results (QoR) in runtimes typically seen in “prototype-level” synthesis runs. The “secret sauce,” he said, is in the partitioning. Cadence has found a way to generate partitions in a way that “slices the design more intelligently, and takes advantage of the Genus database to merge partitions without losing timing, power, or area,” Stratman said.

Playing in the Sandbox

In the Genus Synthesis Solution, a process called “sandboxing” allows any subset or partition of a design to be extracted along with full timing and a physical context. Optimization algorithms will treat a sandbox as a complete design.

The “Clipper” flow clips out or extracts the context of the larger SoC blocks. “It’s kind of a skeleton floorplan but it has all the timing information,” Stratman said. These extracted contexts include all the critical physical information to make the right RTL synthesis choices at the unit level. This information is used to streamline the handoffs between unit-level RTL designers, integration engineers, and implementation engineers. It’s a way for logic designers to gain some physical knowledge without having to be a physical synthesis expert, or without having to run a full top-level synthesis.

Fig. 2 – Clipper flow provides context for unit-level blocks

Correlation with Innovus Implementation System

Although Genus technology can work with third-party IC implementation systems, it shares algorithms and engines with Innovus Implementation System, as well as a common user interface. As shown below, both the Genus and Innovus solutions use a table-based Quantus QRC parasitic extraction, effective current source model (ECSM) and composite current source (CCS) delay calculations, and a unified global routing engine. Timing and wire length claim a 5% correlation.

Fig. 3 – Genus Synthesis Solution offers tight correlation with Innovus Implementation System

Genus technology doesn’t model everything to the same level of accuracy as the Innovus solution, however. “We chose to be lighter weight and more nimble to get expected runtimes,” Stratman said. A tight correlation is possible because the Genus and Innovus solutions use a similar code base. This correlation will be tighter than that between Encounter RTL Compiler Advanced Physical Option and the Encounter Digital Implementation System today.

Genus Synthesis Solution uses a new Hybrid Global Router that provides the ability to resolve congestion and construct layer-aware, timing-driven wire topologies. This accelerates analysis and debug, and reduces iterations. Users can avoid blockages and see a full Manhattan route as opposed to “flight lines.” Layer awareness is particularly important, given the large RC variations within the metal stack at advanced process nodes.

A version of the Innovus GigaPlace engine is available within the Genus solution. Here, users can do an RTL-level generic gate placement early in the synthesis flow (“generic gate” means there is no mapping into standard cell libraries, but there’s still an area estimate). This helps designers understand PPA tradeoffs earlier.

While users can go all the way to a design-rule “legal” placement with Genus Synthesis Solution, this isn’t generally recommended. “You can do a placement and use the same algorithms as GigaPlace and get a nice correlation without all the runtimes and additional steps of doing a fully legal placement,” Stratman said.

So where does Genus technology end and Innovus technology begin? That’s up to the user. You could use the Genus solution for logical synthesis and run all physical implementation in the Innovus system. If you run physical synthesis within the Genus solution, there’s more work earlier in the flow, but you get better insights into downstream problems and reduce iterations.

“Physical synthesis should be no more than 2X [runtime] of logic synthesis,” Stratman said. “All of the runtime that moves up should be shaved off of the place-and-route stages, because now you can do lightweight incremental optimization and incremental placement. The overall flow should be runtime neutral or better.”

Be Globally Aware

Finally, Genus Synthesis Solution offers a globally focused early PPA optimization across the whole datapath, delivering up to a 20% area reduction in the datapath. Stratman noted that this capability is a follow-on to an RCP feature called “globally focused mapping” that can determine the best cells to use in a library. What’s new with the Genus solution is that this concept has been applied at the arithmetic level.

For example, there are many ways to configure a multiplier – you may want to prioritize speed, power, or size. In the past, Stratman noted, synthesis tools have not been very good at globally optimizing the architecture selection for PPA optimization. “We can [now] find the most efficient global datapath implementation for a given region,” he said.

For further information about the Cadence Genus Synthesis Solution, including a datasheet and technical product brief, see this landing page.

Richard Goering

Related Blog Posts

Designer View – RTL Synthesis Success Strategies at 28nm and Below

Front-End Design Summit: The Future of RTL Synthesis and Design for Test

Physically-Aware Synthesis Helps Design a New Computer Architecture

Hello everyone,

I am Vinay and I am currently developing some digital circuits for my chip design for my master's thesis at University at Buffalo.

I am fairly very new to Verilog and I don't seem to follow some of the things others find very easy.

Following are the things that I want to do to which I have no clue:

1. Develop certain arithmetic functionality in Verilog

2. Generate netlist for the verilog code

3. Feed the netlist file to Cadence encounter to be able to generate Digital Circuits' layout for my chip

I can use Cadence Virtuoso and Encounter for this but I don't know the exact procedure to get this done.

Could someone please describe the detailed process for doing the things mentioned above.

Thank you.

•Dassault Aviation will rely on six Dassault Systèmes industry solution experiences to integrate business processes, improve performance and reduce costs •Deployment marks next step in Dassault Aviation’s digital transformation plan through a platform approach, launched in 2018 •Dassault Systèmes’ 3DEXPERIENCE platform will power artificial intelligence-based application for intelligent enterprise services

Hashes is a cross-platform tool that generates and injects different keys with the same hash code in order to test web applications against hash collision attacks. Written in Java. Has support for Java, PHP, ASP, and V8.

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German utility E.ON has agreed to sell its 527 MW Terni hydroelectric power complex to Genoa-based ERG Power Generation S.p.A.

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Chile's Schwager Energy and China-based Shenyang Yuanda Commercial & Investment Co. signed a memorandum of understanding on Nov. 3 to build the 3-MW Los Pinos run-of-the-river hydroelectric plant in southern Chile's Lagos region, according to BN Americas.
 

Brazil is the second-largest producer of hydroelectric power in the world, after only China, and hydropower accounted for more than 70% of the country’s electricity generation in 2018. Brazil’s latest 10-year energy plan seeks to maintain this level of hydro generation while increasing the share of nonhydro renewables, particularly solar.

The idea of a “smart grid” has taken center stage — an evolution of advanced technologies that make the availability of a smarter, more efficient electrical power grid possible. These technologies aim to address the complex challenges facing grid systems today, which stem largely from its aging infrastructure and a use case model that has evolved over the years. With power systems over a century old, the field instrumentation on the grid is quickly reaching its life cycle limit, which adversely affects overall grid reliability and efficiency.

In a previous article, I had a conversation with former-CIA chief Jim Woolsey to discuss one of America’s greatest national security vulnerabilities, its power grid. The issues that Woolsey has been concerned with for over a decade has been the ease in which a terrorist group or other actor (think North Korea for example) could attack the grid and plunge the country into darkness for months, if not years. And if that seems far-fetched, just recall how a tree limb fell in Ohio in 2003 and blacked out the entire Northeast and part of Canada for several days.

The Russian Prime Minister Dmitry Medvedev has amended Russia’s federal law on the electric power industry. Ordinance No47 lays out a number of measures aiming to stimulate renewable energy sales in the national retail market.

GE announced today that it sees a future in housing its renewable generation businesses (onshore and offshore wind, hydropower) alongside its grid businesses which include substations and transformers plus solar, storage and distributed energy resource (DER) control software. GE Renewable Energy CEO Jerome Pecresse said in a press conference that the move will simplify the lives of GE’s customers by giving them one point of contact for all of their renewable energy power needs.

Renewable Energy Generation Ltd., a British low-carbon asset developer backed by BlackRock Inc., will build six waste-to-power plants with Caterpillar Inc. and Finning U.K. Ltd. in an expansion of plans published last month.

U.K. renewable power generation rose 28 percent last year as more wind farms and solar plants came online, the Department of Energy and Climate Change said.

Billionaire Rubens Ometto’s Cosan SA has the potential to triple its power generation by burning sugar-cane leftovers if the government offers power-purchase contracts for biomass producers.

Chile's Schwager Energy and China-based Shenyang Yuanda Commercial & Investment Co. signed a memorandum of understanding on Nov. 3 to build the 3-MW Los Pinos run-of-the-river hydroelectric plant in southern Chile's Lagos region, according to BN Americas.
 

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The post Listen to the voice of Generation C — they have answers for Africa’s future appeared first on The Mail & Guardian.

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