DOVER, Del.— Delaware Secretary of State Jeff Bullock on Wednesday announced the retirement of Paul Weagraff, Director of the Division of Arts, following 24 of years of service to the Department of State. Weagraff will serve through the end of July.  “Paul and I have served together through the bookends of two great challenges to our arts community: […]

October is National Italian American Heritage Month, a month dedicated to celebrating the distinguished cultural contributions of Americans with Italian lineage. According to the United States Census Bureau, as of 2019, more than 16 million Americans of Italian descent reside in the United States, making up the seventh largest ethnic group in the country. “Italian […]

More than fifty-five friends, dignitaries and guests gathered in Lewes, Delaware on Wednesday, October 20, 2021 to celebrate the unveiling of the Delaware Public Archives’ newest marker that commemorates the Block House Pond. Block House Pond, a natural spring-fed pond was named for a nearby blockhouse that was built to protect Lewes in the 1670s. […]

This year between November 2nd through 6th, the Delaware Department of State joins Indian Delawareans in celebrating Diwali, the annual festival of lights celebrated by Hindus, Jains, and Sikhs. Diwali, which is celebrated over the course of five days, symbolizes the spiritual “victory of light over darkness, good over evil, and knowledge over ignorance.” “As […]

Dover, Del.—Secretary of State Jeff Bullock announced on Friday that Jordan Schulties, Director of the Division of Small Business, and Tim Slavin, Director of the Division of Historical and Cultural Affairs, will depart from their roles to embark on new journeys at the Delaware Department of Technology and Information (DTI) and Fort Dupont Redevelopment & […]

Delaware Secretary of State Jeff Bullock issued a statement following Senator Tom Carper’s decision to not seek reelection in 2024: Tom Carper has literally bent the arch of Delaware history. Everywhere you look up and down our state, Tom Carper has had an impact. His body of work is unprecedented, and it continues to grow, […]

The Delaware Department of Agriculture is warning all residents about two deadly species of hemlock recently found in Sussex County. Environmental scientists have confirmed the presence of poison hemlock (Conicum maculatum) and spotted water hemlock (Cicuta maculata). All parts of the plants – leaves, stems, flowers, and roots – are poisonous to humans and animals.

DOVER, Del. (February 23, 2022) – Testing has confirmed a case of avian influenza on a Delaware poultry farm that showed increased mortality over the past few days. Following an investigation by the Delaware Department of Agriculture, the U.S. Department of Agriculture’s National Veterinary Services Laboratory has confirmed poultry from this farm have tested positive […]

DOVER, Del. (March 1, 2022) – The Delaware Department of Agriculture (DDA) has been warning poultry owners since January to take extra precautions to protect their birds in light of detections of highly pathogenic avian influenza (HPAI) in wild birds in the Atlantic Flyway. But after a case of HPAI was announced last week in […]

The Delaware Department of Agriculture (DDA) announced they will be distributing $199,600 in relief funds through the Seafood Processors Pandemic Response and Safety (SPRS) Block Grant Program to eligible Delaware seafood processors, dealers, and processing vessels who were financially impacted by the COVID-19 pandemic.

As businesses in the UK and Ireland rapidly adopt generative AI, strategic insights from the latest SAS study reveal the roadmap to successful integration and the hurdles to overcome. GenAI is rapidly transforming how businesses operate, innovate, and interact with customers and employees alike. However, as the technology proliferates, so [...]

Unlocking generative AI: Navigating challenges to reap unprecedented business benefits was published on SAS Voices by Iain Brown

If you hate having your SIM locked to your carrier, then we’ll show you how to SIM unlock your iPhone 16 Pro for free!

The post How to SIM unlock the iPhone 16 Pro for FREE! appeared first on Phandroid.

Smart Lock Company LockState raised $5.8M Series A in new investment to fund its aggressive sales and marketing and partner development plan. The company previously raised $740K seed round and $1M in a round led by angel investors. The lead investor in latest round was Iron Gate Capital. Other investors include Kozo Keikaku Engineering Inc, Nelnet and Service Provider Capital.

The company’s Wi-Fi-enabled RemoteLock is used by 1000s of Airbnb and other vacation rental hosts. It helps hosts remotely provide access to guests. Locking/unlocking codes can be generated via a host’s computer or smartphone.

RemoteLock’s prices start at $299 which is its algorithmic ResortLock. The most pricey lock by LockState is its ‘RemoteLock 7i Black WiFi Commercial Smart Lock’ which costs $479.

Another core product of LockState is its cloud-based remote access platform for internet-enabled locks. It implies users can remotely manage their (internet-enabled) locks via LockState’s cloud platform.

Unlike smartphones and watches, customers don’t look forward to upgrading their smart locks or buying one when new models are launched. Thus, smart lock companies offset this disadvantage by partnering with property management and short-term rental companies to get new customers.

LockState has partnered with vacation rental brands like Airbnb, HomeAway, and other listing partners to automate guest access.

Igloohome a Singapore-based smart lock company also raised an investment of $4M in April this year.

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environment. Locking is the most basic requirement for data sharing. A core takes the lock, accesses the shared data structure, and releases the lock. While one core has the lock, other cores are disallowed from accessing the same data structure. Typically, locking is implemented using an atomic read-modify-write bus transaction on a variable allocated in an uncached memory.

This blog shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform. It uses a dual-core design mapped to a KC705 platform as an example.

Exclusive Access to Accomplish Locking

The Xtensa AXI4 manager provides atomic access using the AXI4 atomic access mechanism. While Xtensa's AXI manager interface generates an exclusive transaction, the subordinate's interface is also expected to support exclusive access, i.e., AXI monitoring. Xilinx BRAM controller's AXI subordinate interface does not support exclusive access, i.e., AXI monitoring: AXI Feature Adoption in Xilinx FPGAs.

Leveraging Xtensa AXI4 Subordinate Exclusive Access

The Xtensa LX AXI subordinate interface supports exclusive access. One approach is to utilize this support and allocate locks in one of the core's local data memories. Ensure that the number of external exclusive managers is configured, typically to the number of cores (Figure 1).

Figure 1

Note that the Xtensa NX AXI subordinate interface does not support exclusive access. For an Xtensa NX design, shared memory with AXI monitoring is required.

In Figure 2, the AXI_crossbar#2 (block in green) routes core#0's manager AXI access (blue connection) to both core's local memories. Core#1's manager AXI (yellow connection) can also access both core's local memories. Locks can be allocated in either core's local data memory.

In-Bound Access on Subordinate Interface

On inbound access, the Xtensa AXI subordinate interface expects a local memory address, i.e., an external entity needs to present the same address as the core would use to access local memory in its 4GB address space. AXI address remap IP (block in pink) translates the AXI system address to each core's local address. For example, assuming locks are allocated in core#0's local memory, core#1 generates an AXI exclusive to access a lock allocated in core#0's local memory (yellow connection). AXI_crossbar#2 forwards transaction to M03_AXI port (green connection). AXI_address_remap#1 translates the AXI system address to the local memory address before presenting it to core#0's AXI subordinate interface (pink connection).

It is possible to configure cores with disjoint local data memory addresses and avoid the need for an address remap IP block. But then it will be a heterogeneous multi-core design with a multi-image build. An address remap IP is required to keep things simple, i.e., a homogeneous multi-core with a single image build. A single image uses a single memory map. Therefore, both cores must have the same view of a lock, i.e., the lock's AXI bus address must be the same for both.

Figure 2

AXI ID Width

Note Xtensa AXI manager interface ID width=4 bits. Xtensa's AXI subordinate interface ID width=12 bits. So, you must configure AXI crossbar#2 and AXI address remap AXI ID width higher than 4. AXI IDs on a manager port are not globally defined; thus, an AXI crossbar with multiple manager ports will internally prefix the manager port index to the ID and provide this concatenated ID to the subordinate device. On return of the transaction to its manager port of origin, this ID prefix will be used to locate the manager port, and the prefix will be truncated. Therefore, the subordinate port ID is wider in bits than the manager port ID. Figure 3 shows the Xilinx crossbar IP AXI ID width configuration.

Figure 3

Software Tools Support

Cadence tools provide a way to place locks at a specific location. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK. .xtos.lock(green) resides in core#0's local memory and holds user-defined and C library locks. The lock segment memory attribute is defined as shared inner (cyan) so that L32EX and S32EX instructions generate an exclusive transaction on an AXI bus. See Figure 4. The stack and per-core Xtos and C library contexts are allocated in local data memory (yellow).

…………..LSP memory map………….
BEGIN dram0
0x40000000: dataRam : dram0 : 0x8000 : writable ;
dram0_0 : C : 0x40000400 - 0x40007fff : STACK : .dram0.rodata .clib.percpu.data .rtos.percpu.data .dram0.data .clib.percpu.bss .rtos.percpu.bss .dram0.bss;
END dram0
…………………
BEGIN sysViewDataRam0
0xA0100000: system : sysViewDataRam0 : 0x8000 : writable, uncached, shared_inner;
lockRam_0 : C : 0xA0100000 - 0xA01003ff : .xtos.lock;
END sysViewDataRam0
…………..

Figure 4

Please visit the Cadence support site for more information on emulating Xtensa cores on FPGAs.

anyone know what is "cell with Zero maximum clock transition time"  ?

not zero transition, not maximum transtion, it is zero maximum clock transition time.

it means X0 cell? (drive-strength)

can you explain? 

thanks :-)

Hi all,

I have been following the tutorial "Innovus Block Implementation with Stylus Common UI", version 23.1.

While I was doing the clock tree synthesis, the tutorial calls for a command

clock_opt_design

But my tool tells me this is a beta feature which needs to be enabled.

Warning: clock_opt_design requires beta feature innovusClockOptFlow enabled.

Can I ask how do I enable this beta feature?

My version of Innovus is v21.35-s114_1, is it because of the version incompatibility?

Many thanks

Hi all,

I'm trying to model the clock of a clock doubler. The doubler consists of a delay cell and an XOR gate, which generates a pulse on both the rising and falling edge of the input clock. I've created a simple module to evaluate this. In this case, DEL1 and XOR2 are standard library cells. There is a don_touch constraint on both library cells as well as on clk_d.

module top (
input wire clk,
output reg Q);

//Doubler
wire clk_d;
wire clk_2x;
DEL1 u_delay (.I(clk),.Z(clk_d));
XOR2 u_xor (.A1(clk),.A2(clk_d),.Z(clk_2x));

//FF for connecting the clock to some leaf:
always @(posedge clk_2x) Q<=~Q;

endmodule

My SDC looks like this:

create_clock [get_ports {clk}] -name clk_i -period 100
set_clock_latency -rise 0.1 [get_pins u_xor/Z]
set_clock_latency -fall 0.4 [get_pins u_xor/Z]
create_generated_clock -name clk_2x -edges {1 1 2 2 3} -source clk [get_pins u_xor/Z]

The generated clock is correctly generated but the pulse width is zero. I would be expecting that the pulse width is the difference between fall and rise latency but is not applied:

report_clocks:

report_clocks -generated:

clk_2x is disconnected from the FF after syn_generic. What can I do to model some minimum pulse width? Will innovus later on model this correctly with the delay of DEL1?

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In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized. 

The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral.  

The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.” 

Operation of PTP: 

To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent. 

The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages.  

To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay. 

The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized. 

Advantages of PTP: 

1. It provides accurate time stamping. 
2. It is a well-known clock synchronization protocol. 
3. It provides intensified security inside the premises. 
4. It provides the possibility of setting coordinated actions and synchronized communication. 

There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS. 

Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per DIMM card. The highest speed DDR5 SDRAM devices can support data rates of up to 8800 MTps.

DDR5 SO-DIMMs and UDIMMs

One of the most recognized uses of PCDDR is with client devices like laptops and personal computers. These client devices mostly use two types of DDR5 DIMMs called SO-DIMM (Small Outline Dual Inline Memory Module) and UDIMM (Unbuffered Dual Inline Memory Module).

These types of DIMMs have no signal regeneration or buffering (which, for example, the Registering Clock Driver or the RCD does for clocks/command/control signals for a registered DIMMs). A typical 2-Rank UDIMM with x8 DDR5 SDRAM components has 8 or 10 components per rank depending on the system ECC (Error Correction Code) memory being part of the DIMM.

Why DDR5 Clock Buffer and CUDIMM?

Clocks are one of the most important signals for synchronous devices, and DDR5 SDRAMs are no exception. The host is responsible for the fanout to all the DRAM input ports, such as clocks for UDIMMs. Driving of all these DRAM clocks can put quite a bit of load on the host output drivers, thus affecting the signal quality, which can result in unexpected memory errors. This issue gets amplified when operating at the higher clock and data rates where the clock signals transition from one logic value to the next over a very short time. To solve these signal integrity issues with DRAM clocks, JEDEC has come up with a new type of DDR5 DIMM component that is called DDR5 clock buffer. Clock buffers can be used for both DDR5 SO-DIMMs and DDR5 UDIMMs. DDR5 UDIMMs that include a clock buffer component as part of the DIMM card are called DDR5 CUDIMMs (Clock Buffered UDIMMs).

DDR5 Clock Buffer Overview

DDR5 Clock Buffer is a simple logic device that takes in two sets of input clock pins and drives two sets of clock pins as output per channel. The clock buffer device can operate in three types of clock modes: -

• PLL bypass mode: In this mode, the clock buffer just passes on the input clocks to output without any kind of signal buffering. The PLL bypass mode enabled CUDIMM devices behave like traditional UDIMMs without any buffering of the clocks. This is why it’s also referred to as legacy mode. Recommended CUDIMM operating speeds in PLL bypass mode are typically limited to 3000 MHz.

• Single PLL mode: In the single PLL Mode, the clock buffer device will use a Phase Lock Loop (PLL) for the regeneration of the incoming host clock to create a better-quality clock that is sent to the DRAMs. However, since there is only one PLL that is used in this mode, both sub channel output clocks will be driven based on only one set of input clocks with the other set of input clocks remaining unused.

• Dual PLL mode: In this mode, the clock buffer will use two PLLs to independently generate each sub channel output clock based on each set of incoming host clocks. The second set of PLL can be turned on or off on the fly if needed to save power.

Beyond the clock modes, clock buffers provide additional flexibility to the system designers with register-controlled additional signal delays, optional output clock enable/disable per bit feature, drive strength and termination choices, etc. All DDR5 clock buffer device control word registers are accessible via DDR5 DIMM sideband.

Cadence VIPs offers a compressive memory subsystem solution that includes memory models for DDR5 SDRAM, DDR5 RCD, DDR5 DB, DDR5 clock buffer, all types of DDR5 DIMMs, including the DDR5 CUDIMMs, DFI Memory Controller/PHY VIPs, and a system VIP compliant to JEDEC specifications defined for each of those devices along with latest DFI Specification.

More information on Cadence DDR5 DIMM VIP is available at the Cadence VIP Memory Models website.

Hi,

So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. 
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.

Thank you all.

Hi,

I have a question about printing noise summary via maestro output expressions.

How can I print noise data using output expressions, for multiple levels of the hierarchy?

I have found this article which describe the procedure using ocnGenNoiseSummary() function: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000007MViHEAW&pageName=ArticleContent

I see also Andrew Beckett referring to the above mentioned article as a solution to a similar question: community.cadence.com/.../noise-summary-per-instance

However, this seems to work only if I'm to extract noise data from a single level of hierarchy.

If I have the output expression "ocnGenNoiseSummary(2 ?result 'hbnoise)", it will generate a "noisesummary" directory under results directory for a hierarchy level of 2.

If I am to extract data from various hierarchy levels, I should be able to generate multiple noise summary directories, such as noisesummary1, noisesummary2 where they correspond to "ocnGenNoiseSummary(1 ?result 'hbnoise)" & "ocnGenNoiseSummary(2 ?result 'hbnoise)", respectively. However this does not seem to be possible.

Can you please advice? Thanks.

My Cadence version: IC23.1-64b.ISR7.27

BR,

Denizhan Karaca

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

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Related Courses:

• Joules Power Calculator

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Continued African development could hinge on public finance reforms.

HANOI, VIETNAM — Vietnam said Chinese online retailers Shein and Temu need to register with the government before the end of November or it will block their internet domains and apps from being used in the country. Vietnam's government and local businesses have expressed concern about the impact of Chinese online platforms on local markets due to deep discounting. The trade ministry has also said it is worried about the potential for the sale of counterfeit items. Nguyen Hoang Long, Vietnam's deputy trade minister, told a government meeting at the weekend that the ministry had worked with both Shein and Temu on the licensing matter. "After the ministry's notification, if these platforms do not comply, the Ministry of Industry and Trade will coordinate with relevant agencies to implement technical measures such as blocking applications and domains," Long said in a government statement. Shein and Temu did not respond immediately to a request for comment. Fast-fashion retailer Shein has been selling into Vietnam for at least two years, while Temu, owned by Chinese e-commerce giant PDD Holdings, started allowing users in Vietnam to shop last month. Vietnam allows imported goods of up to $40 to be exempt from a value-added tax. The finance ministry said most items benefiting from this tax break are imported via e-commerce platforms and it is considering terminating the tax break. Both Temu and Shein are also facing increased scrutiny and legal challenges elsewhere. Last month, Indonesia requested Apple and Google block Temu from their app stores to protect small merchants from competing with ultra-cheap items. Vietnam's e-commerce market has grown 18% this year to be worth $22 billion, the third-largest in Southeast Asia behind Indonesia and Thailand, according to a report by Google, Temasek and Bain & Company released last week. Other e-commerce platforms that operate in Vietnam include Singapore-based Shoppe, Alibaba-backed Lazada and domestic companies Tiki and Sendo.

In a tragic incident in Rawalpindi’s Shah Khalid Colony, three siblings, 2-year-old Zohan, 6-year-old Saira, and 7-year-old Faria, lost their lives after being confined in a box. The children were left alone at home, intensifying the sorrow of the situation. According to reports from a Rescue spokesperson, the parents, who were employed in different jobs—the ... Read more

The post Tragedy Strikes as Three Siblings Found Dead Locked in Box appeared first on Pakistan Tribune.

Canada announced Wednesday it won't block access to the popular video-sharing app TikTok but is ordering the dissolution of its Canadian business after a national security review of the Chinese company behind it. Industry Minister François-Philippe Champagne said it is meant to address risks related to ByteDance Ltd.'s establishment of TikTok Technology Canada Inc. "The government is not blocking Canadians' access to the TikTok application or their ability to create content. The decision to use a social media application or platform is a personal choice," Champagne said. Champagne said it is important for Canadians to adopt good cybersecurity practices, including protecting their personal information. He said the dissolution order was made in accordance with the Investment Canada Act, which allows for the review of foreign investments that may harm Canada's national security. He said the decision was based on information and evidence collected over the course of the review and on the advice of Canada's security and intelligence community and other government partners. A TikTok spokesperson said in a statement that the shutdown of its Canadian offices will mean the loss of hundreds of local jobs. "We will challenge this order in court," the spokesperson said. "The TikTok platform will remain available for creators to find an audience, explore new interests and for businesses to thrive." TikTok is wildly popular with young people, but its Chinese ownership has raised fears that Beijing could use it to collect data on Western users or push pro-China narratives and misinformation. TikTok is owned by ByteDance, a Chinese company that moved its headquarters to Singapore in 2020. TikTok faces intensifying scrutiny from Europe and America over security and data privacy. It comes as China and the West are locked in a wider tug of war over technology ranging from spy balloons to computer chips. Canada previously banned TikTok from all government-issued mobile devices. TikTok has two offices in Canada, one in Toronto and one in Vancouver. Michael Geist, Canada research chair in Internet and E-commerce Law at the University of Ottawa, said in a blog post that "banning the company rather than the app may actually make matters worse since the risks associated with the app will remain but the ability to hold the company accountable will be weakened." Canada's move comes a day after the election in the United States of Donald Trump. In June, Trump joined TikTok, a platform he once tried to ban while in the White House. It has about 170 million users in the U.S. Trump tried to ban TikTok through an executive order that said "the spread in the United States of mobile applications developed and owned" by Chinese companies was a national security threat. The courts blocked the action after TikTok sued. Both the U.S. FBI and the Federal Communications Commission have warned that ByteDance could share user data such as browsing history, location and biometric identifiers with China's government. TikTok said it has never done that and would not, if asked. Trump said earlier this year that he still believes TikTok posed a national security risk, but was opposed to banning it. U.S. President Joe Biden signed legislation in April that would force ByteDance to sell the app to a U.S. company within a year or face a national ban. It's not clear whether that law will survive a legal challenge filed by TikTok or that ByteDance would agree to sell.

Lockman discusses the current struggle in Egypt among the Muslim Brotherhood, the revolutionaries of Tahrir Square and the military that has reclaimed power.

Speculation spiked after Prime Minister Benjamin Netanyahu replaced Gallant with Katz that the attempts to draft Haredim would be halted, given Netanyahu and the haredi coalition parties' opposition.

Judges block Albania model again and order return of 7 migrants to Italy

Climate finance will come under intense scrutiny during COP29, and its distribution aligned with scientific analysis of the impacts of climate change, but the methodology ignores the inequality in research networks of the Global South.

Armenia's data center industry offers significant opportunities for economic growth, with strategic reforms in regulation, financing, and technological innovation playing crucial roles. Addressing infrastructure challenges and fostering public-private partnerships will help position Armenia as a regional digital hub.

unlock guide in google sketchup

In most vertebrates, a pattern of chemical marks on the genome is a reliable indicator of age, but in axolotls this clock seems to stop after the first four years of life

Forget atomic clocks. Nuclear clocks, which only drop a second every 300 billion years, can test whether nature's fundamental constants are constant after all

A set of mathematical equations can help turn apparently random observations into a clock – and then measure its accuracy

Forget atomic clocks. Nuclear clocks, which only drop a second every 300 billion years, can test whether nature's fundamental constants are constant after all

The Chicxulub impact 66 million years ago filled the sky with fine silicate dust, which blocked out sunlight and lingered for 15 years

An AI-assisted robot can listen to spoken commands and assemble 3D objects such as chairs and tables out of reusable building blocks

Title: Lockdowns Tough on People With Eating Disorders: Survey
Category: Health News
Created: 8/24/2020 12:00:00 AM
Last Editorial Review: 8/25/2020 12:00:00 AM

Title: Nerve Block Plus Lidocaine Clears Psoriasis in Small Study
Category: Health News
Created: 8/15/2022 12:00:00 AM
Last Editorial Review: 8/16/2022 12:00:00 AM

Title: How Can You Unblock Your Ear?
Category: Diseases and Conditions
Created: 12/31/2020 12:00:00 AM
Last Editorial Review: 6/29/2022 12:00:00 AM

Purpose The posterior superior alveolar (PSA) block injection is one of many techniques used to provide profound anesthesia for invasive dental procedures. This technique has a high success rate but is not without complication risks. The purpose of this study was to determine if pulpal anesthesia of the maxillary second molar could be achieved using a reduced needle depth of 10mm or 5mm compared to the traditional needle depth of 16mm.Methods Sixty participants were asked to participate in three sessions. Each session started with a pre neural response test, followed by one randomized needle depth PSA injection, and ending with a post neural response test. The neural response test consisted of two parts, a cold refrigerant and a dental probe, on the buccal and interproximal surface of the maxillary second molar. After receiving a positive neural response, each participant received a posterior superior alveolar block injection using a short (21mm), 27-gauge dental needle with a randomized needle penetration depth of 16mm, 10mm, or 5mm. A post neural response test consisting of the same two parts as the pre-test was conducted on the maxillary second molar to evaluate for profound anesthesia.Results Positive neural responses were obtained from 100% of the participants (n=167) during the pre-tests. Study results demonstrated an 85% success rate at the traditional 16mm needle depth and a 93% and 92% success rates for the reduced needle depths of 10mm and 5mm, respectively. Pulpal anesthesia of the maxillary second molar had been achieved at all three needle depths with no statistically significant difference in the rate of success. Furthermore, there were no adverse events observed.Conclusion The reduced needle depth technique showed promise in achieving desired results of pulpal anesthesia with a reduced risk for complications associated with the PSA block injection. Additional studies are recommended to achieve evidence-based support for this reduced needle depth technique.

BackgroundBetween 2003 and 2018, incident prescriptions of beta-blockers for anxiety increased substantially, particularly for young adults. National Institute for Health and Care Excellence guidance for anxiety does not recommend beta-blockers, probably due to a lack of evidence to support such use. Recent reports have highlighted the potential risks of beta-blockers.AimTo understand when and why GPs prescribe beta-blockers for people with anxiety.Design and settingIn-depth interviews with 17 GPs in Bristol and the surrounding areas.MethodInterviews were held by telephone or video call. A topic guide was used to ensure consistency across interviews. Interviews were audio-recorded, transcribed verbatim, and analysed thematically.ResultsMany GPs viewed beta-blockers as ‘low risk’, particularly for young adults. Some GPs viewed beta-blockers as an alternative to benzodiazepines, acting quickly and not leading to dependence. GPs reflected that some patients appeared to want an ‘immediate fix’ to their symptoms, which GPs thought beta-blockers could potentially offer. This is salient in light of substantial waiting lists for talking therapies and delays in antidepressants taking effect. GPs described how some patients seemed more willing to try beta-blockers than antidepressants, as patients did not perceive them as ‘mental health drugs’ and therefore viewed them as potentially more acceptable and less stigmatising. Further, GPs viewed beta-blockers as ‘patient-led’, with patients managing their own dose and frequency, without GP input.ConclusionMany GPs believe that beta-blockers have a role to play in the management of anxiety. Given recent increases in the prescribing of these drugs in primary care, there is a need to assess their safety and effectiveness as a treatment for people with anxiety disorders.

Comprehensive maps of neuronal connectivity provide a foundation for understanding the structure of neural circuits. In a circuit, neurons are diverse in morphology, electrophysiology, gene expression, activity, and other neuronal properties. Thus, constructing a comprehensive connectivity map requires associating various properties of neurons, including their connectivity, at cellular resolution. A commonly used approach is to use the gene expression profiles as an anchor to which all other neuronal properties are associated. Recent advances in genomics and anatomical techniques dramatically improved the ability to determine and associate the long-range projections of neurons with their gene expression profiles. These studies revealed unprecedented details of the gene–projection relationship, but also highlighted conceptual challenges in understanding this relationship. In this article, I delve into the findings and the challenges revealed by recent studies using state-of-the-art neuroanatomical and transcriptomic techniques. Building upon these insights, I propose an approach that focuses on understanding the gene–projection relationship through basic features in gene expression profiles and projections, respectively, that associate with underlying cellular processes. I then discuss how the developmental trajectories of projections and gene expression profiles create additional challenges and necessitate interrogating the gene–projection relationship across time. Finally, I explore complementary strategies that, together, can provide a comprehensive view of the gene–projection relationship.

The mystery surrounding Deadlock, Valve’s work-in-progress MOBA shooter, has largely evaporated. Its freely extendable invite system is about as effective at controlling player headcount as a disinterested football steward, meaning pretty much anyone with a clued-in Steam friend can get in and start poking around its secrets. And yet, being a lane-pushing wizard fighter in the Dota 2 vein, it’s already a vast tangle of interplaying abilities, items, strats, and often unspoken rules, of the kind that even experienced gankists will take hundreds of hours to learn. It’s been too much for poor Brendy, at any rate.

Still, Brendy is but one man. What if we had but four men, working in tandem to crush lanes and flatten Patrons just as Gabe intended? To find out if Deadlock is indeed more comprehensible as a team sport, Graham, Ed, Ollie, and James joined forces, promptly getting fucked up yet emerging from the warlock hospital with a deeper understanding of its workings. Or, at least, if anyone would keep playing.

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JUDY WOODRUFF: And in the day’s other news: A federal judge in Hawaii struck down the Trump administration’s latest travel ban.

That temporarily blocks enforcement of the order nationwide, but the Justice Department says it will appeal. The ban extended to six mostly Muslim nations, plus North Korea and Venezuela.

Pennsylvania Congressman Tom Marino withdrew today from consideration to be President Trump’s drug czar. That followed an investigation by The Washington Post and CBS News. They found Marino was key in passing a 2016 law that limits the Drug Enforcement Administration’s ability to rein in opioid distribution.

A new verbal battle has broken out between the president and Republican Senator John McCain. It began last night in Philadelphia, when the Arizona senator and former Vietnam POW appeared to criticize Mr. Trump and his followers. He cited a list of failings.

SEN. JOHN MCCAIN, R-Ariz.: To fear the world we have organized and led for three-quarters-of-a-century, to abandon the ideals we have advanced around the globe for the sake of some half-baked, spurious nationalism cooked up by people who would rather find scapegoats than solve problems.

(CHEERING AND APPLAUSE)

JUDY WOODRUFF: The president answered by saying, “At some point, I fight back, and it won’t be pretty.”

In turn, McCain said, “I have faced tougher adversaries.”

In Afghanistan, Taliban bombings and shootings left at least 74 people dead today. The worst was Paktika province in the east, where two car bombs killed dozens, including the provincial police chief, and wounded more than 100 others. Taliban militants also staged attacks in the south and west of the country.

In Syria, militia forces backed by the U.S. say they have retaken the Islamic State group’s de facto capital. The city of Raqqa had been under ISIS control since 2014. The battle to recapture it began in June. Today, Kurdish-led fighters celebrated as they moved into the city center. The U.S. military said 90 percent of Raqqa has been taken, with pockets of militants remaining.

There’s word that U.S. airstrikes in Yemen killed dozens of Islamic State fighters on Monday. The strikes were apparently carried out by drones. The Pentagon says the targets were training camps for recruits.

In Northern Iraq, Kurdish forces withdrew from more territory today, as Iraqi government troops advanced. It came on the heels of the Kurds’ vote for independence. Federal forces and allied militia had already forced the Kurds to leave the area in and around Kirkuk and its oil fields.

Iraq’s prime minister said that paves the way for talks.

HAIDER AL-ABADI, Prime Minister, Iraq (through interpreter): I call for dialogue on the basis of partnership in one country and under the Constitution. The referendum is finished and has become a thing from the past. We hoped that they would cancel it, but we have finished it on the ground.

JUDY WOODRUFF: Meanwhile, the president of Iraqi Kurdistan, Massoud Barzani, insisted that the referendum will not be in vain.

Another 10,000 to 15,000 Rohingya Muslims fled Buddhist Myanmar for Bangladesh over the weekend. Drone video showed snaking lines of refugees making the trek to already crowded camps. Many told of villages torched by mobs and soldiers. Others said they were starved out of their homes.

Back in this country, a new fire broke out in the San Francisco Bay Area, just as crews had made major progress against other fires in Northern California. Thick smoke billowed from the new site early today, as it burned through forests in the Santa Cruz Mountains. Weary fire crews said they’re calling in more help.

ROB SHERMAN, Division Chief, Cal Fire: So, the idea is to hit it pretty hard with aircraft and then go ahead and hit it with the ground resources at the same time. We have had north winds, a lot of drying, and everything’s really, really dry. So it’s challenging.

JUDY WOODRUFF: In Southern California, yet another fire spread on Mount Wilson, about 25 miles north of downtown Los Angeles. It threatened a historic observatory and communications towers.

President Trump’s overall wealth has taken a hit, as his New York real estate loses some of its luster. Forbes ranks him 248 this year on its list of the 400 wealthiest Americans. That’s down nearly 100 points from last year. His estimated worth is $3.1 billion.

Microsoft co-founder Bill Gates again tops the list. He’s worth nearly $90 billion.

And on Wall Street, the Dow Jones industrial average traded above 23,000 for the first time. In the end, it gained 40 points to close at 22997. The Nasdaq fell a fraction, and the S&P 500 added one point.

The post News Wrap: Trump’s latest travel ban blocked by federal judge appeared first on PBS NewsHour.