fro

From business users to system architects: How generative AI will change the way you work

Generative AI (GenAI) is here to stay – there’s no question about it. A recent SAS survey of 1,600 organizations found that 54% have begun implementing It, and 86% plan to invest in it within the next financial year. As organizations integrate AI into their workflows, a critical question arises: [...]

From business users to system architects: How generative AI will change the way you work was published on SAS Voices by Stu Sztukowski




fro

NEWS FROM FEMA: FEMA and Delaware Officials Opening COVID-19 Vaccination Center in Dover 

WILMINGTON, Del. – Governor John Carney on Tuesday shared the following news from the Federal Emergency Management Agency (FEMA): The Federal Emergency Management Agency (FEMA), the Centers for Disease Control (CDC), Health and Human Services (HHS), Delaware Emergency Management Agency (DEMA), Delaware Division of Public Health (DPH), and Dover International  Speedway (DIS) have partnered to open a […]



  • Delaware Emergency Management Agency
  • Division of Public Health
  • Governor John Carney
  • Office of the Governor
  • Coronavirus
  • COVID-19 Vaccine
  • Delaware Division of Public Health
  • DEMA
  • governor
  • Governor Carney

fro

Statement from DE Law Enforcement Partnership on the Death of Tyre Nichols

   Delaware Law Enforcement Partnership   January 27, 2023   The leaders of Delaware’s Law Enforcement Partnership and its members, together with the Secretary of the Delaware Department of Safety and Homeland Security are outraged by the actions of the Memphis Police officers who participated in the heinous crimes that led to the death of […]



  • Delaware State Police
  • Department of Safety and Homeland Security
  • News

fro

Road Fatalities Decrease in 2023 from 2022 High

137 fatalities were recorded on Delaware roads in 2023, a 16 percent decrease from 2022 when 164 fatalities occurred. Fatalities were down across all modes of transportation with a 13 percent reduction in pedestrian fatalities; 29 percent reduction in bicyclist fatalities; and a 32 percent reduction in motorcyclist fatalities from last year. “Reducing fatalities on […]




fro

An update from Fenwick Island’s historic lighthouse

Visitors to the historic lighthouse in Fenwick Island may have noticed some significant upgrades over the last few years, the most recent of which include a facelift for the 165-year-old seaside structure.




fro

Governor Carney Shares Highlights from the Legislative Session 

DOVER, Del. – Governor John Carney on Sunday reflected on actions taken during this legislative session:  “We’ve done a lot this legislative session to move our state forward,” said Governor Carney. “We’ve taken action to make our communities safer, protect our environment, and we continue to invest in our students and educators. I’m proud that our budget makes […]




fro

Event at the Delaware Public Archives: Tales from the Vaults

On Saturday, October 5, 2024 at 10:30am, the Delaware Public Archives will present a new offering, “Tales from the Vaults,” that will present four unique spooky stories culled from the collections of the Delaware Public Archives. “We’re excited to share this special thematic Saturday event to the public,” said Stephen Marz, State Archivist and Delaware […]




fro

Governor Carney, with Guidance from Water Supply Coordinating Council, Declares Statewide Drought Watch

WILMINGTON, Del. – Governor John Carney on Friday issued a statewide drought watch after receiving guidance from the Delaware Water Supply Coordinating Council (WSCC). Delawareans are asked to voluntarily reduce outdoor uses of water during the drought watch. This decision follows an assessment of conditions by the WSCC on October 25. The drought watch will remain in effect until […]



  • Delaware Emergency Management Agency
  • Delaware Health and Social Services
  • Department of Agriculture
  • Department of Natural Resources and Environmental Control
  • Division of Water
  • Governor John Carney
  • News
  • Office of the Governor
  • State Fire Marshal
  • drought
  • open burning ban

fro

Mollywood MeToo: Actor Siddique's Interim Protection From Arrest Extended

The Supreme Court on Tuesday extended the interim protection from arrest granted to Malayalam film actor Siddique in an alleged rape case.




fro

Six takeaways from working on Madrid’s digital transformation efforts

During lockdowns across Europe and beyond, we all moved our lives online. We worked remotely and had meetings via Teams or Zoom. We also socialised and shopped online. For many people, this was familiar territory. For others, it opened up a whole new world—and highlighted significant problems with the ‘old [...]

The post Six takeaways from working on Madrid’s digital transformation efforts appeared first on Government Data Connection.




fro

Jailed Gangster's Wife Tries To Extort Rs 2 Crore From Hotelier, Arrested

Police on Monday arrested Manisha, wife of jailed gangster Kaushal Chaudhary, for allegedly trying to extort Rs 2 crores from a hotel owner, officials said.




fro

Ratan Tata's Journey From Mumbai Boy To Global Icon - A Timeline

Ratan Naval Tata, the business titan and global icon who led the Tata behemoth from thirty countries to over a hundred since becoming chairman in 1991, died today at Mumbai's Breach Candy Hospital. He was 86.




fro

Noel Tata Takes Over From Ratan Tata. Know The Tata Ancestry And History

Founded in 1868, Tatas have become one of largest and most diverse global conglomerates. It is a name heard in almost every home in India and tens of millions overseas.




fro

From X Factor To One Direction: The Story Of Boy Band Star Liam Payne

Liam Payne, who rose to fame as a member of the boy band One Direction has died at the age of 31. The British singer fell to his death from the third-floor balcony of Hotel CasaSur Palermo in Buenos Aires, Argentina.




fro

From Studying In Prison To Heading Hamas Oct 7 Attack: Who Was Yahya Sinwar

The Israel Defense Forces (IDF) and the Israel Security Agency have jointly confirmed that Hamas leader Yahya Sinwar was killed in the Gaza Strip by Israeli soldiers on Wednesday.




fro

Apple & Samsung Exported Rs 40,000 Crore Of Smartphones From India: Apple Can Beat Samsung Very Soon!

Apple is in fast pace catching up with Samsung in India as far as smartphone exports from the country are concerned.  Apple was not far behind at $2.2 billion at the same time Samsung’s smartphone exports in value stood at around $2.8 billion for the April-October period. Apple Scaling Up Exports In India It is […]




fro

India Beats China In Air Travel Safety: Ranking Jumps From 102 To 48 In Global Aviation Safety

India’s air safety protocols and executions have improved drastically over the years, as validated by the findings of a specialized agency of the United Nations, the International Civil Aviation Organization or ICAO. The UN watchdog has upgraded India’s ranking in terms of aviation safety to the 48th position, jumping past the rankings of countries like […]




fro

Again, Tyla Beats Asake, Tems, Ayra Starr, Burnaboy, Wins 'Best Afrobeats' at MTV EMA

[Premium Times] In September, Tyla made headlines at the MTV Video Music Awards (VMAs) for winning the "Best Afrobeats," but she stirred debate by clarifying that she identified with the Amapiano genre rather than Afrobeats




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Cosatu Is Deeply Concerned By Government's Withdrawal of the SABC Soc Ltd Bill From Parliament

[COSATU] The Congress of South African Trade Unions (COSATU) is deeply concerned by the Minister for Communications and Digital Technologies, Mr. S. Malatsi's sudden withdrawal of the South African Broadcasting Corporation (SABC) SOC Ltd Bill from Parliament where it was being engaged upon by the National Assembly's Portfolio Committee: Communications and Digital Technologies.




fro

removing cdn_loop_breaker from the genus synthesis netlist

I am trying to remove the cdn_loop_breaker cells from the netlist. 
When I tried the below 2 things, genus synthesis tool removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1.  remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker  comand without the -instances switch
2. remove_cdn_loop_breaker  
     
both of the above things are not providing the proper connections after removing the loop_breaker_cells

can anyone suggest the best possible workaround for this please?




fro

How to allow hand-made waveform plot into Viva from Assembler?

Hi! I've made some 1-point waveform "markers" that I want to overlay in my plots to aid visualization (with the added advantage, w.r.t. normal Viva markers, that they update location automatically upon refreshing simulation data).

For example, the plot below shows an spectrum along with two of these markers, which I create with the function "singlePointWave", and the Assembler output definitions also as shown below.

The problem is: as currently created and defined, Assembler is unable to plot these elements. I can send their expressions to the calculator and plotting works from there, BUT ONLY after first enabling the "Allow Any Units" in the target Viva subwindow.

Thus, I suspect Assembler is failing to plot my markers because they "lack" other information like axes units and so on. How could I add whatever is missing, so that these markers can plot automatically from Assembler?

Thanks in advance for any help!

Jorge.

P.S. I also don't know why, but nothing works without those "ymax()" in the output definitions--I suspect they are somehow converting the arguments to the right data type expected by singlePointWave(). Ideas how to fix that are also welcome! ^^

procedure( singlePointWave(xVal yVal)
    let( (xVect yVect wave)
        xVect = drCreateVec('double list(xVal));
        yVect = drCreateVec('double list(yVal));
        wave = drCreateWaveform(xVect yVect);
    );
);




fro

read from text file with two values and represent that as voltage signals on two different port a and b

i want to read from text file two values  on two ports , i wrote  that  code, and i have that error that shown in the image below . and also the data in text file is shown as screenshot

 


module read_file (a,b);

electrical a,b;
integer in_file_0,data_value, valid, count0,int_value;


analog begin
@(initial_step) begin
in_file_0 = $fopen("/home/hh1667/ee610/my_library/read_file/data2.txt","r");

valid = $fscanf (in_file_0, "%b,%b" ,int_value,count0);
end

V(a) <+ int_value;
V(b) <+ count0;

end

endmodule




fro

Stream in gds to virtuoso from directory other than where cds.lib exists

I am scripting gds streamin using 'strmin', which works fine so far.

But, as it apparently doesn't have an option to specify where the cds.lib file is, I have to run it from the directory where the cds.lib file is, or I guess I could create a dummy one to source that one.

Is there a way to tell strmin where the cds.lib file is?




fro

copy paste circuit from one schematic design to another

Hi, have two designs and would like to copy paste one area of circuit from the old design to the new design, best way/approach and guidance please..




fro

removing cdn_loop_breakers from netlist

I was trying to remove the cdn_loop_breaker cells from the netlist. 
When I tried the below 2 things, it removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1.  remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker  comand without the -instances switch
2. remove_cdn_loop_breaker  
     
both of the above things are not providing the proper connections after removing the loop_breaker_cells





fro

BoardSurfers: Some Wisdom from Designing for a High-Volume Production OEM

At what stage in the design cycle do you start to think about the PCB material costs? What about the costs to assemble the PCB? Once a design becomes successful, should you then redesign it to achieve a scalable product? Placing components and routi...(read more)




fro

How to transfer etch/conductor delays from Allegro Package Designer (APD) to pin delays in Allegro PCB Editor

The packaging group has finished their design in Allegro Package Designer (APD) and I want to use the etch/conductor delay information from the mcm file in the board design in Allegro PCB Designer. Is there a method to do this?

This can be done by exporting the etch/conductor data from APD and importing it as PIN_DELAY information into Allegro PCB Editor.

If you are generating a length report for use in Allegro Pin Delay, you should consider changing the APD units to Mils and uncheck the Time Delay Report.

In Allegro Package Designer:

  1. Select File > Export > Board Level Component.
  2. Select HDL for the Output format and select OK.

       3. Choose a padstack for use when generating the component and select OK.

This will create a file, package_pin_delay.rpt, in the component subdirectory of the current working directory. This file will contain the etch/conductor delay information that can be imported into Allegro.

In Allegro PCB Editor:

  1. Make sure that the device you want to import delays to is placed in your board design and is visible.
  2. Select File > Import > Pin delay.
  3. Browse to the component directory and select package_pin_delay.rpt. The browser defaults to look for *.csv files so you will need to change the Files of type to *.* to select the file.
  4. You may be prompted with an error message stating that the component cannot be found and you should select one. If so, select the appropriate component.
  5. Select Import.
  6. Once the import is completed, select Close.

Note: It is important that all non-trace shapes have a VOLTAGE property so they will not be processed by the the 2D field solver. You should run Reports > Net Delay Report in APD prior to generating the board-level component. This will display the net name of each net as it is processed. If you miss a VOLTAGE property on a net, the net name will show in the report processing window, and you will know which net needs the property.




fro

Lessons from the UMass Lowell Women’s Leadership Conference

This post was contributed by Liliko Uchida, application engineer at Cadence. Being a “Woman in STEM” is a phrase that has long been used to describe the holistic experience shared by thousands of women globally, yet it still makes us feel isolated. Partially due to the statistics of gender population in the STEM workforce and the remainder due to our own internal obstacles, being a woman in STEM continues to be a challenge. While many of us know the should-do’s and should-be’s of taking on this unique role objectively, we struggle to implement them. After all, our perseverance as engineers, mathematicians, businesswomen, programmers, and scientists is largely affected by subjectivity. The UMass Lowell Women’s Leadership Conference 2024 aimed to tackle this problem by uniting hundreds of women with shared experiences under one roof. Not only did the conference provide us with the knowledge necessary to persevere, but it also gave us the tools that will allow us to thrive and act upon the facts we already know. It is my hope that through this blog post, I can share some of my main takeaways from this special day. Be Confident This is one of the most palpable pieces of advice we always hear. Yet so many of us struggle to build this confidence because we don’t know how. Featured speaker Nicole Kalil defined confidence as “complete trust in oneself”.”One way to build this self-trust is by getting to know yourself on a deeper level. By creating a true inner connection, we begin to see ourselves as a whole instead of hyper-focusing on our shortcomings frequently illusioned by imposter syndrome. In one of the sessions, we were asked to introduce ourselves to our neighbors, not by what we do for work, but by who we are as a person. Even if this opportunity does not arise every day, this practice can be done simply by listing characteristics of yourself that define who you are. Who do you care for? How do you show them? What are your life goals oriented towards? How do you observe others’ behavior around you, and what does that say about how you make them feel? Getting to know you beneath the surface and allowing yourself to be seen for who you are is critical in building internal confidence. With practice, this self-reassurance will grow independent of external factors. Take Risks “Sometimes, you have to put your foot in the elevator” - Barb Vlacich, Keynote Speaker When opportunities arise, the only thing you can do to have a chance is to try. Without putting your foot in the elevator, the doors will close, becoming a missed opportunity. Similarly, several of the conference’s speakers also emphasized that the answer to every unasked question will always be a no. Even if you are not ready to full-send a negotiation, ask for a raise, or respectfully disagree with a co-worker’s opinion, start by getting comfortable asking uncomfortable questions. Just one discomfort a day will help in building an immunity to the anxiety that comes with taking risks, typically driven by our self-doubt. Another interesting point that stood out from the conference was the statistics of self-assessed qualifications between men and women. During the negotiation panel, it was revealed that men typically feel they only need 60% of the qualifications under a job description to apply, whereas women often feel they need close to 100%. These numbers alone demonstrate how the pure mental habits of men continue to funnel them into STEM and not women. The next time you seek a new opportunity, assess yourself based on the 60% and use it as a checklist threshold. If more women are able to pursue STEM careers using these numbers, the more likely we will begin to populate these roles. Build Your Genuine Network “ The essence of communication lies in the mutual exchange of ideas and emotions. And when the listener isn’t invested, it undermines the entire purpose of the conversation. Why are you having it anyway?” This is a quote from episode 186 of Julie Brown’s podcast This Sh!t Works called “The 5 Steps to Being an Active Listener”. Julie Brown is a Networking Coach, author, and podcast host who guided an energetic and candid conversation about networking and building a personal brand for women. Networking is often misunderstood as putting your name and qualifications out on the table for as many people to pick up your cards. While making these things known is important, they are not what nurtures effective connections. The key to cultivating your genuine network is to activate a sincere interest in the people you meet. Become the proactive receiver of the confidence exercise discussed above. When you meet someone new, what can you take away from them as a person, not an employee? By making people feel heard, even through the little conversations, you can begin to develop more meaningful connections that resonate. And, with practice, the sometimes inherent need to overcompensate by defining yourself with your resume will slowly fade. It was a wonderful opportunity to attend the UML Women’s Leadership Conference with four other inspiring Cadence women. Not only was the conference a motivating learning experience, but it was also a wonderful opportunity for us to bond together as women and feel supported by each other. The most eye-opening part of the day was seeing just how many women alike were sitting under the same roof. The conclusion of the event led me to feel proud to be an engineer, proud to be at Cadence, and most importantly, proud to be a woman. Learn more about life at Cadence .




fro

We Must Reclaim Nationalism From the BJP

This is the 18th installment of The Rationalist, my column for the Times of India.

The man who gave us our national anthem, Rabindranath Tagore, once wrote that nationalism was “a great menace.” He went on to say, “It is the particular thing which for years has been at the bottom of India’s troubles.”

Not just India’s, but the world’s: In his book The Open Society and its Enemies, published in 1945 as Adolf Hitler was defeated, Karl Popper ripped into nationalism, with all its “appeals to our tribal instincts, to passion and to prejudice, and to our nostalgic desire to be relieved from the strain of individual responsibility which it attempts to replace by a collective or group responsibility.”

Nationalism is resurgent today, stomping across the globe hand-in-hand with populism. In India, too, it is tearing us apart. But must nationalism always be a bad thing? A provocative new book by the Israeli thinker Yael Tamir argues otherwise.

In her book Why Nationalism, Tamir makes the following arguments. One, nation-states are here to stay. Two, the state needs the nation to be viable. Three, people need nationalism for the sense of community and belonging it gives them. Four, therefore, we need to build a better nationalism, which brings people together instead of driving them apart.

The first point needs no elaboration. We are a globalised world, but we are also trapped by geography and circumstance. “Only 3.3 percent of the world’s population,” Tamir points out, “lives outside their country of birth.” Nutopia, the borderless state dreamed up by John Lennon and Yoko Ono, is not happening anytime soon.

If the only thing that citizens of a state have in common is geographical circumstance, it is not enough. If the state is a necessary construct, a nation is its necessary justification. “Political institutions crave to form long-term political bonding,” writes Tamir, “and for that matter they must create a community that is neither momentary nor meaningless.” Nationalism, she says, “endows the state with intimate feelings linking the past, the present, and the future.”

More pertinently, Tamir argues, people need nationalism. I am a humanist with a belief in individual rights, but Tamir says that this is not enough. “The term ‘human’ is a far too thin mode of delineation,” she writes. “Individuals need to rely on ‘thick identities’ to make their lives meaningful.” This involves a shared past, a common culture and distinctive values.

Tamir also points out that there is a “strong correlation between social class and political preferences.” The privileged elites can afford to be globalists, but those less well off are inevitably drawn to other narratives that enrich their lives. “Rather than seeing nationalism as the last refuge of the scoundrel,” writes Tamir, “we should start thinking of nationalism as the last hope of the needy.”

Tamir’s book bases its arguments on the West, but the argument holds in India as well. In a country with so much poverty, is it any wonder that nationalism is on the rise? The cosmopolitan, globe-trotting elites don’t have daily realities to escape, but how are those less fortunate to find meaning in their lives?

I have one question, though. Why is our nationalism so exclusionary when our nation is so inclusive?

In the nationalism that our ruling party promotes, there are some communities who belong here, and others who don’t. (And even among those who ‘belong’, they exploit divisions.) In their us-vs-them vision of the world, some religions are foreign, some values are foreign, even some culinary traditions are foreign – and therefore frowned upon. But the India I know and love is just the opposite of that.

We embrace influences from all over. Our language, our food, our clothes, our music, our cinema have absorbed so many diverse influences that to pretend they come from a single legit source is absurd. (Even the elegant churidar-kurtas our prime minister wears have an Islamic origin.) As an example, take the recent film Gully Boy: its style of music, the clothes its protagonists wear, even the attitudes in the film would have seemed alien to us a few decades ago. And yet, could there be a truer portrait of young India?

This inclusiveness, this joyous khichdi that we are, is what makes our nation a model for the rest of the world. No nation embraces all other nations as ours does. My India celebrates differences, and I do as well. I wear my kurta with jeans, I listen to ghazals, I eat dhansak and kababs, and I dream in the Indian language called English. This is my nationalism.

Those who try to divide us, therefore, are the true anti-nationals. We must reclaim nationalism from them.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.




fro

Lessons from an Ankhon Dekhi Prime Minister

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.




fro

How to transfer custom title block from Orcad Capture to PCB Editor

Hi,

So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. 
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.

Thank you all.




fro

Launch footprint editor from Capture or PCB Editor?

I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint?




fro

Migrating from files Orcad Layout 16.2

I have managed to convert our old schematic and PCD file to from Layout 16.2 to 17.4

I have exported the footprints and moved them to the correct lib directory. 

I get no DRC errors and I can build a new netlist file. The problem is I can't get the PCB editor to update using the new netlist and get the following error:

I cannot figure out how to fix the Name is too long error. 

(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : 70055R2.brd                                   )
(    Software Version : 17.4S023                                      )
(    Date/Time        : Tue Dec 14 18:54:25 2021                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  Yes
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               IfSame
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         'C:/AFS/70055 PCB Test 2'
Design Directory:            'C:/AFS/70055 PCB Test 2'
Old design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'
New design name:             'C:/AFS/70055 PCB Test 2/70055R2.brd'

CmdLine: netrev -$ -i C:/AFS/70055 PCB Test 2 -x -u -t -y 2 -h -z -q netrev_constraint_report.xml C:/AFS/70055 PCB Test 2/#Taaaaae57776.tmp

------ Preparing to read pst files ------

Starting to read C:/AFS/70055 PCB Test 2/pstchip.dat 
   Finished reading C:/AFS/70055 PCB Test 2/pstchip.dat (00:00:00.02)
Starting to read C:/AFS/70055 PCB Test 2/pstxprt.dat 
   Finished reading C:/AFS/70055 PCB Test 2/pstxprt.dat (00:00:00.00)
Starting to read C:/AFS/70055 PCB Test 2/pstxnet.dat 
   Finished reading C:/AFS/70055 PCB Test 2/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------


#1   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#2   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_S' has library errors. Unable to transfer to Allegro.

#3   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.

#4   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW' has library errors. Unable to transfer to Allegro.

#5   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW' has library errors. Unable to transfer to Allegro.

#6   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_DPDT': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_DP' has library errors. Unable to transfer to Allegro.

#7   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB15_DSUBVPTM15_CONNECTOR DB15': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB15_DSUBVPTM15_CONNE' has library errors. Unable to transfer to Allegro.

#8   ERROR(SPMHNI-176): Device library error detected.

ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB9_DSUBVPTM9_CONNECTOR DB9': 'Name is too long.'.

ERROR(SPMHNI-170): Device 'CONNECTOR DB9_DSUBVPTM9_CONNECT' has library errors. Unable to transfer to Allegro.

#9   ERROR(SPMHNI-175): Netrev error detected.

ERROR(SPMHDB-195): Error processing 'M6': Text line is outside of the extents..

------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_17.4/share/local/pcb/modules 

PSMPATH =  . 
           symbols 
           .. 
           ../symbols 
           C:/Cadence/SPB_17.4/share/local/pcb/symbols 
           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 
           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 
           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 

PADPATH =  . 
           symbols 
           .. 
           ../symbols 
           C:/Cadence/SPB_17.4/share/local/pcb/padstacks 
           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 
           C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols 
           C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols 


------ Summary Statistics ------


#10  Run stopped because errors were detected

netrev run on Dec 14 18:54:25 2021
   DESIGN NAME : '70055R2'
   PACKAGING ON Nov  2 2021 14:32:04

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 10 errors detected
 No oversight detected
 No warning detected

cpu time      0:00:27
elapsed time  0:00:00




fro

Change code in veriloga view from external program

For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.

My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?




fro

error when generating snp files from a variable

Hello everyone, 
I have a testbench for generating s2p files from a SP simulation that was working until few months ago. Today I have reopened (w/o making changes that I am aware of) and I get the error as shown below:

first I show the testbench settings:

notice how the s2p generation is disabled: the field "file" is left blank

in the corner I defined some parameters, "filename" is the word that is suppose to generate the name for the s2p. 

where the two variables are defined as follows

And now the output log:

spectre.out file gives the following error:


When clicking on the error message at "9", the input.scs file opens up and the line 9 gets highlighted in green



now, so far I understood that the problem seem to be related tom the "pathcds" variable, but I really don't understand what the error message here means, since I don't see any error in the input.scs file

by the way - if for instance I define the variable "filename" as shown below, then I get no errors:


thanks
Tommaso




fro

Is it possible to automatically exclude registers or wires that are not used from toggle coverage?

Hello,

I have a question about toggle coverage.

In my case, there are many unused registers or wires that are affecting the toggle coverage score negatively.

Is it possible to automatically exclude registers or wires that are not used from toggle coverage?

My RTL code is as follows, Is it possible to automatically disable tb.top1.b and tb.top1.c without using an exclude file?

module top1;

  reg a;

  reg b;

  reg [31:0] c;

  initial

  begin

  #1 a=1'b0;

  #1 a=1'b1;

  #1 a=1'b0;

  end

endmodule

module tb;

  top1 top1();

endmodule




fro

Using vManager to identify line coverage from a specific test

I have been using the rank feature to identify tests that are redundant in our environment, but then I realized I'd also like to be able to see exactly what coverage goes into increasing the delta_cov value for a given test. If I had a test in my rank report that contributed 0.5% of the delta_cov, how could I got about seeing exactly where that 0.5% was coming from? It seems like that might be part of the correlate function, but I couldn't mange to find a way to see what specific coverage was being contributed for a given test.




fro

Plot on Smith Chart from HB Simulation

Dear All,

To design an outphasing combiner, I need to extract the input impedances when the circuit is driven by two sources concurrently with a varying phase-shift and plot them on a Smith Chart. However, I can't find a way to display the simulated S-parameters on a Smith Chart.

The testbench, shown below, consists of two sources set to 50 Ohm with variable phase (PORT0: theta, PORT1: -theta) swept from -90° to 90°. The NPORTs are couplers used to isolate the forward and reflected power at each source, i.e. the S-parameters are:

  • S13 = S31 = 1; through path
  • S21 = S41 = 1; forward and reflected power
  • All other are zero

The testbench is simulated with an "hb" analysis instead of "sp", as the two sources have to be excited simultaneously with varying phase-shift to see their load-modulation effect. The sweep is setup in the "Choosing Analysis" window. The powers of the forward (pXa) and reflected (pXb) waves are found through the "Direct Plot" window, e.g. pvr('hb "/p1a" 0 50.0 '(1)) as the power for p1a, and named P1A_Watt. The S-parameters are then calculated as the reflected power w.r.t. the forward power P1B_Watt/P1A_Watt. This approach is based on a Hot S-parameter testbench from ADS.

At this point I would like to display these S-parameters on a Smith Chart. However, this seemed more challenging than expected. One straightforward method would seem to create an empty Smith Chart window in the Display Window and dragging the S-parameters from the rectangular plot on it, but this just deletes them from the Display Window. Hence my question:

How can I display these S-parameters on a Smith Chart?




fro

Update Package_Height_Max from Orcad Capture

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?




fro

Technical Webinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

  • Key concepts of specifying chip behavior and performance
  • How to translate ideas into a digital blueprint and transform that into a design
  • How to ensure your design is free of errors

This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.

When Is the Webinar?

Date and Time

Wednesday, September 18, 2024
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing 

REGISTER

To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System.

Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.

If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

To view our complete training offerings, visit the Cadence Training website.

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Want to Learn More?

This link gives you more information about the related training course and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Also, take this opportunity to register for the free Online Trainings related to this webinar topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Xcelium Integrated Coverage

Related Training Bytes

How to Run the Synthesis Without DFT?

How to Run the Synthesis Flow with DFT? (Video)

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!




fro

Here Is the Recording of the RTL-to-GDSII Flow FrontEnd Webinar!

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

  • Key concepts of specifying chip behavior and performance
  • How to translate ideas into a digital blueprint and transform that into a design
  • How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Learning Maps

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Related Training Bytes

What is RTL Coding In VLSI Design?

What is Digital Verification?

What Is Synthesis in VLSI Design?

What Is Logic Equivalence Checking in VLSI Design?

What Is DFT in VLSI Design?

What is Digital Implementation?

What is Power Planning?

What are DRC and LVS in Physical Verification?

What are On-Chip Variations?

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!




fro

View from the Middle East & Africa: small steps can have a big impact on tourism

Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders.




fro

View from Middle East and Africa: SDGs need rich to support the poor

The UN Sustainable Development Goals aim to end global poverty, but poorer countries are struggling to hit them. More help from richer countries is crucial, writes Mazdak Rafaty.




fro

View from Asia: imagining the worst

What if the coronavirus lasts until the end of the year? Lawrence Yeo has a bleak forecast.




fro

Nokia Bell Labs looks to make maximum impact from minimum sites

Marcus Weldon, chief technology officer of Nokia and president of its research arm Nokia Bell Labs, talks about what guided the decision to set up a new global R&D centre and the company’s strategy for driving innovation




fro

View from Asia: why Asia needs to nurture its tourism offering

Asia outstrips the world for tourist arrivals and is still experiencing growth. Constant maintenance and upgrade are essential to maintain this lead.




fro

View from Asia: the crippling effect of coronavirus

China's coronavirus outbreak is having a seismic effect in Asia and beyond, writes Lawrence Yeo.




fro

View from the Americas: the evolving political economy of FDI

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 




fro

View from the Americas: time for action on SDGs

Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf.




fro

Which FDI sectors could benefit from the coronavirus crisis?

Wavteq's Henry Loewendahl discusses which sectors retain potential for foreign investment amid the current global crisis