In conversation with Martin Griffiths: How can a divided world address conflict? 1 October 2024 — 10:00AM TO 11:00AM Anonymous (not verified) 16 September 2024 Chatham House and Online

The former United Nations Under-Secretary-General describes how a weakening multilateralism system and dysfunctional political diplomacy can be revitalized by a humanitarian approach.

Addressing Russia’s use of forced displacement in Ukraine 7 November 2024 — 12:30PM TO 2:00PM Anonymous (not verified) 17 October 2024 Chatham House and Online

Experts consider the role international law could play in responding to Russia’s forcible movement of people during its war against Ukraine.

In the two and a half years since its full-scale invasion of Ukraine, evidence has emerged of Russia’s use of forced deportation and forcible transfer. Russia has also employed arbitrary detention as a tool of war and occupation.

Much attention has been on the International Criminal Court’s arrest warrants against Russian President Vladimir Putin and his children’s commissioner Maria Alekseyevna Lvova-Belova. These warrants were issued in relation to the alleged war crimes concerning the unlawful deportation of children from Ukraine to Russia and the unlawful transfer of thousands of children from occupied areas of Ukraine.

Meanwhile, Ukrainian citizens are being arrested and sent to Russia to serve prison sentences. They are often detained without charge and conviction.

This panel discussion explores:

• What evidence is emerging of Russia using unlawful deportation and transfer of children, and the arbitrary detention of civilians?
• What is the role and significance of international law on these issues?
• What challenges might these practices create for later peace negotiations, as well as the securing of justice?
• What is the process of releasing illegally detained Ukrainians, and Ukrainian children in particular, and reuniting them with their families? How do Russian volunteers inside Russia cooperate with Ukrainian NGOs to facilitate family reunification?

The event includes a screening of part of the documentary After the Rain: Putin’s Stolen Children. 

The institute occupies a position of respect and trust, and is committed to fostering inclusive dialogue at all events. Event attendees are expected to uphold this by adhering to our code of conduct.

The UK needs to address growth and debt problems if it is to match resources to ambitions on international priorities Expert comment LJefferson 5 November 2024

The budget marks the lowest amount in decades the country has spent on development, and it is struggling to fund other international priorities too.

The UK’s Chancellor Rachel Reeves unveiled her much-anticipated budget last week, the first of the new Labour government. Labour is in a difficult place. There are numerous calls on the public purse and public services are not performing well. Meanwhile, public debt remains close to 100 per cent of GDP, and there has been a long run of sluggish growth.
 
Reeves argues with some justification that the previous government left her a challenging inheritance – gaps in this year’s spending plans, and persistent debt questions left unresolved. More importantly, there are longer-term concerns about the sustainability of UK public spending – the country’s Office for Budget Responsibility has warned public debt could triple by the 2070s due to an ageing population, the climate crisis, and security risks. The focus has understandably been on kitchen table questions about tax rises and funding public services.
 
But this picture also has longstanding implications for international policy – on whether the UK can afford to invest in its foreign policy. The Chancellor did announce an increase of £2.9bn for defence. But the question of whether the UK can get on a sustainable path to spending 2.5 per cent of GDP on defence is still being worked through in the ongoing Strategic Review, and remains challenging despite increasingly urgent warnings from parliamentary committees about the UK’s defence readiness.

The budget also marks one of the lowest amounts in recent years the UK will spend on development overseas, despite setting an ambition to reset relations with the Global South and recover the UK’s role as a leader in international development.
  
The UK needs to either match resources to ambition, spend much more efficiently, or, in the case of the aid budget, it could seek to focus on priorities that are less dependent on spending. But even this will still require consistent resources, alongside significant diplomatic attention, intellectual leadership, and focus.

Longer-term, the UK may need to consider larger questions: addressing broader problems with its lack of growth and productivity will be critical to fund an expansive international role.

With this budget, UK aid spent overseas is at a historic low

In 2020 the UK government cut its goal for spending on international development to 0.5 per cent of Gross National Income (GNI), ending a longstanding policy of spending 0.7 per cent. Labour have echoed this, promising to only return to previous levels when fiscal circumstances allow.
 
But this masks a bigger issue. Since 2022, significant amounts of the UK’s aid budget have been spent on accommodation for asylum seekers in the UK. This is within the rules governing aid, but reduces the amount spent on reducing poverty overseas. In 2023 this spending was 28 per cent of the £15.4bn aid budget. In 2016, it was 3.2 per cent. 

Previous Chancellor Jeremy Hunt quietly allowed a top-up of aid spending over the last two fiscal years to offset how much is being spent at home on asylum seeker accommodation. That provided an additional £2.5 billion for 2022–23 and 2023–24.

But Rachel Reeves declined to provide extra funding this time, meaning the amount being spent overseas is likely the lowest its been since 2007 – an effective cut – under a Labour government.

The Minister for Development, Anneliese Dodds, speaking at Chatham House last month, said the government is working on clearing the backlog of asylum claims, which should free up more to spend overseas.

But beyond this there has been little clarity on plans to address the issue. And costs for asylum seeker accommodation have increased significantly – the UK appears to spend much more than comparator countries per head, according to the Center for Global Development, raising questions about how this spending is managed.

Development is not just about money – but money is important

The UK debate about development has often focused on the 0.7 per cent figure, which can distract from larger questions about what development policy is intended to achieve. As many experts have argued, development aid is about more than spending, and the wider, complex process by which the UK contributes to broad-based growth and stability for poorer countries is not about hitting a specific number.
 
There are things the UK can do that aren’t about spending more directly. This might include focusing on priorities like reforming multilateral development banks so they provide more low-cost public finance, and more flexible and agile loans to poorer countries – a priority echoed by Dodds. It might also incorporate focusing more broadly on helping developing countries attract more investment to bolster growth. 

There is also the issue of developing country debt, much of which is held by the private sector. Dodds previously said, when she was shadow chancellor, she might consider changing the law to address this issue. However,  she declined to recommit to this when questioned at Chatham House. 

None of this can be done unilaterally – on debt, for example, the UK has spearheaded some creative policies. Its UK Export Finance body developed climate-resilient debt clauses – agreements that countries can pause debt repayments in the event of a climate shock – but the UK holds limited amounts of developing country debt. Impact will only come by galvanizing and coordinating others to adopt similar approaches.

Addressing illegal gold mining: International policy priorities 18 November 2024 — 11:30AM TO 1:00PM Anonymous (not verified) 6 November 2024 Chatham House and Online

Held in partnership with the World Gold Council, this panel of experts examines the global Artisanal and Small-Scale Gold Mining (ASGM) landscape and propose policy priorities essential for fostering sector formalization.

In this panel discussion, held in partnership with the World Gold Council, experts will examine the global Artisanal and Small-Scale Gold Mining (ASGM) landscape and propose policy priorities essential for fostering sector formalization.

An estimated twenty million people worldwide are involved in the Artisanal and Small-Scale Gold Mining (ASGM) sector, which now accounts for around 20 percent of global gold output. However, 85 percent of this production occurs outside formal legal frameworks. While many in ASGM operate within informal economies or seek pathways to formalization, a significant portion is also vulnerable to criminal exploitation, involving organized crime and armed groups.

In Ethiopia, the sector’s informality is tied to the nation’s volatile security dynamics, with illicit gold mining proliferating as non-state actors compete for control in conflict-prone regions such as Tigray. Additionally, gold is increasingly trafficked through transnational illicit networks in the Sahel and Sudan fuelling instability. South America is also impacted, for example in Peru where the government’s response to illegal ASGM initially saw success in 2019 but has faced sustainability challenges, and environmental impact.

ASGM growth is driven by the rising value of gold, youth unemployment, weak law enforcement, climate impacts, and conflict. While formalization offers significant economic potential, robust international cooperation and industry commitment is required to address the human toll, environmental impact and support sustainable practices.

In this panel discussion, experts will focus on addressing the expansion of illicit control and exploitation within ASGM, highlighting the pathways for governments and large-scale mining companies to drive meaningful change.

This event is hosted in partnership with the World Gold Council. There will be a reception with light refreshments hosted at Chatham House following the event.

This event will be livestreamed via the Africa Programme Facebook page.

The institute occupies a position of respect and trust, and is committed to fostering inclusive dialogue at all events. Event attendees are expected to uphold this by adhering to our code of conduct.

How can the investor community address the ‘S’ in ESG? – the role of social purpose values 16 November 2021 — 1:30PM TO 2:30PM Anonymous (not verified) 18 October 2021 Online

This webinar highlights the crucial relationship between an open civic space and a profitable business environment.

2020 was a tipping point for investors to think and act more responsibly, galvanized by catalysts like the killing of George Floyd and the pandemic. There is increasing investor support for social and environmental causes. Younger investors are placing increasing emphasis on values and social issues in their investment decisions.

The ‘S’ in the Environment Social and Governance (ESG) agenda is clearly gaining traction, but how far does it extend to civil and political liberties i.e. the right of citizens, NGOs and journalists to speak freely, assemble and associate which are increasingly shrinking around the world?

While there is increasing focus on human rights issues such as modern slavery and supply chains, civil society space issues often fall between the cracks when investors consider ESG.

This webinar also explores opportunities and challenges that arise for the investor community in terms of factoring civic space issues into their political risk and ESG analysis.

• To what extent are civic space issues being factored into ESG social purpose values, especially by younger investors?
• What is the best methodology for assessing these issues in order to ensure a common and coherent set of global standards in this area?
• And how can investors mitigate the risks of their activities to civic space in practice?

We have observed overexpression of PACS-1, a cytosolic sorting protein in primary cervical tumors. Absence of exonic mutations and overexpression at the RNA level suggested a transcriptional and/or posttranscriptional regulation. University of California Santa Cruz genome browser analysis of PACS-1 micro RNAs (miR), revealed two 8-base target sequences at the 3' terminus for hsa-miR-34a and hsa-miR-449a. Quantitative RT-PCR and Northern blotting studies showed reduced or loss of expression of the two microRNAs in cervical cancer cell lines and primary tumors, indicating dysregulation of these two microRNAs in cervical cancer. Loss of PACS-1 with siRNA or exogenous expression of hsa-miR-34a or hsa-miR-449a in HeLa and SiHa cervical cancer cell lines resulted in DNA damage response, S-phase cell cycle arrest, and reduction in cell growth. Furthermore, the siRNA studies showed that loss of PACS-1 expression was accompanied by increased nuclear γH2AX expression, Lys382-p53 acetylation, and genomic instability. PACS-1 re-expression through LNA-hsa-anti-miR-34a or -449a or through PACS-1 cDNA transfection led to the reversal of DNA damage response and restoration of cell growth. Release of cells post 24-h serum starvation showed PACS-1 nuclear localization at G1-S phase of the cell cycle. Our results therefore indicate that the loss of hsa-miR-34a and hsa-miR-449a expression in cervical cancer leads to overexpression of PACS-1 and suppression of DNA damage response, resulting in the development of chemo-resistant tumors.

WASHINGTON, Oct. 30, 2024 — The U.S. Department of the Treasury (Treasury) today issued a final rule (Final Rule) to implement Executive Order 14105 of August 9, 2023, “Addressing United […]

The post US Treasury Issues Final Rule Addressing Investments in Certain National Security Technologies and Products appeared first on HPCwire.

The nation's depleted supply of IV solutions is recovering after a North Carolina facility recently resumed production after Hurricane Helene temporarily put it out of business.

The fate of fictional Montana Gov. John Dutton -- played by Kevin Costner -- has finally been disclosed in the Season 5B premiere of "Yellowstone" that aired on Paramount Sunday night.

World Food Day is coming up this Monday, October 16. This year’s theme, Change the future of migration. Invest in food security and rural development, highlights FAO’s work in [...]

Click here to access the presentation by QU Dongyu.

SOLIDWORKS Helps Companies Automate Documentation, Analysis, and Data Management for Compliance

Apple's 2024 Mac mini stashes the power button underneath, a bold move that executives say aligns with user habits, even if it's left some fans scratching their heads.

Minister of Communications and Digital Technologies Solly Malatsi has said his department will look into scrapping luxury tax on smartphones.

The Education Department outlines when and how schools must respond to reports of sexual assault and harassment under the Trump administration's interpretation of Title IX, the federal law that prohibits sex discrimination.

A former computer engineer turned motivational speaker will share his dynamic insights on “Bridging the Digital Divide: Unlocking Access and Opportunity in Education” during a Nov. 6 presentation of the Technology & Society Colloquia Series at Pennsylvania College of Technology.

A Penn State Extension land-use webinar on Nov. 20 will guide local officials on the ins and outs of implementing “active transportation plans.”
 

Alumnus Marvin Johnson Jr. will share personal and professional lessons from his distinguished career leading large-scale global pharmaceutical initiatives with new Penn State Abington graduates.

Heather M. Costa, director of technology resilience at the Mayo Clinic, will address the Penn State Chapter of the Order of the Sword & Shield National Honor Society on Nov. 4. The College of Information Sciences and Technology established the chapter in 2023 and will induct its second cohort at this year’s ceremony.

The overarching goal of HOSS is to support individuals and families in maintaining their housing and achieving housing stability. HOSS does this by providing education on and connection to short- and long-term services as needed.

Governor Markell signed House Bill 175 which will place tighter controls on workers compensation medical costs, while improving the state’s workplace safety program and more effectively encouraging injured individuals to return to work.

Delaware will become first state to prohibit employers from requesting salary history DOVER, Del. – Governor John Carney on Wednesday signed a new law that will prevent employers from requesting the salary history of job applicants and will help close the pay gap between men and women. Sponsored by House Majority Leader Valerie Longhurst, the […]

DOVER, DE (March 15, 2022) – The Division of Public Health’s (DPH) Office of Health Crisis Response (OHCR), has initiated a Restaurant Accolade Program to train and educate restaurant industry staff on how to reverse an opioid overdose and support coworkers with substance use disorder (SUD). The program was developed to assist restaurants, hospitality groups, and […]

NEW CASTLE – The Delaware Division of Substance Abuse and Mental Health (DSAMH) announces the launch of the Health Equity Advancement Project, consisting of two funding opportunities that seek to develop strategies for addressing rising opioid overdose deaths among Black and African American communities in Delaware. DSAMH will award eight mini grants as well as […]

The Smart Food Program, a first in the nation project, will save food waste and reach families in need by using an AI-driven app to match surplus food to SNAP demands    WILMINGTON, Del. — Delaware will be the first state to pilot an innovative app to help those hardest hit by economic challenges stretch […]

WILMINGTON, Del. – Governor Carney was joined by Senator Darius Brown, other members of the General Assembly, and advocates on Thursday, August 29, to sign Senate Substitute 1 for Senate Bill 254, which creates the Delaware Grocery Initiative and addresses food insecurity in urban and rural food deserts. The bill signing was held at the Kingswood Food Bank Mobile […]

Read the in depth Review of Sapphire PULSE AMD Radeon RX 5600 XT 6G GDDR6 PC Components. Know detailed info about Sapphire PULSE AMD Radeon RX 5600 XT 6G GDDR6 configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of CORSAIR DOMINATOR PLATINUM RGB First Edition DDR5 DRAM Memory Kit PC Components. Know detailed info about CORSAIR DOMINATOR PLATINUM RGB First Edition DDR5 DRAM Memory Kit configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

The generative AI market is experiencing rapid growth, driven by the increasing parameter size of Large Language Models (LLMs). This growth is pushing the boundaries of performance requirements for training hardware within data centers. For an in-depth look at this, consider the insights provided in "HBM3E: All About Bandwidth". Once trained, these models are deployed across a diverse range of applications. They are transforming sectors such as finance, meteorology, image and voice recognition, healthcare, augmented reality, high-speed trading, and industrial, to name just a few.

The critical process that utilizes these trained models is called AI inference. Inference is the capability of processing real-time data through a trained model to swiftly and effectively generate predictions that yield actionable outcomes. While the AI market has primarily focused on the requirements of training infrastructure, there is an anticipated shift towards prioritizing inference as these models are deployed.

The computational power and memory bandwidth required for inference are significantly lower than those needed for training. Inference engines typically need between 300-700GB/s of memory bandwidth, compared to 1-3TB/s for training. Additionally, the cost of inference needs to be lower, as these systems will be widely deployed not only in data centers but also at the network's edge (e.g., 5G) and in end-user equipment like security cameras, cell phones, and automobiles.

When designing an AI inference engine, there are several memory options to consider, including DDR, LPDDR, GDDR, and HBM. The choice depends on the specific application, bandwidth, and cost requirements. DDR and LPDDR offer good memory density, HBM provides the highest bandwidth but requires 2.5D packaging, and GDDR offers high bandwidth using standard packaging and PCB technology.

The GDDR7 standard, announced by JEDEC in March of this year, features a data rate of up to 192GB/s per device, a chip density of 32Gb, and the latest data integrity features. The high data rate is achieved by using PAM3 (Pulse Amplitude Modulation) with 3 levels (+1, 0, -1) to transmit 3 bits over 2 cycles, whereas the current GDDR6 generation uses NRZ (non-return-to-zero) to transmit 2 bits over 2 cycles.

GDDR7 offers many advantages for AI Inference having the best balance of bandwidth and cost. For example, an AI Inference system requiring 500GB/s memory bandwidth will need only 4 GDDR7 DRAM running at 32Gbp/s (32 data bits x 32Gbp/s per pin = 1024Gb/s per DRAM). The same system would use 13 LPDDR5X PHYs running at 9.6Gbp/s, which is currently the highest data rate available (32 data bits x 9.6Gb/s = 307Gb/s per DRAM).

Cadence stands at the forefront of AI inference hardware support, being the first IP company to roll out GDDR7 PHYs capable of impressive speeds up to 36Gb/s across various process nodes. This milestone builds on Cadence's established leadership in GDDR6 PHY IP, which has been available since 2019. The company caters to a diverse client base spanning AI inference, graphics, automotive, and networking equipment.

While GDDR7 continues to utilize standard PCB board technology, the increased signal speeds seen in GDDR6 (20Gbp/s) and now GDDR7 (36Gb/s) calls for careful attention with the physical design to ensure optimized system performance. In addition to providing the PHY, Cadence also offers comprehensive PCB and package reference design, which are essential in helping customers achieve optimal signal and power integrity (SI/PI) for their systems.

Cadence is dedicated to ensuring customer success beyond just providing hardware. They provide expert support in SI/PI, collaborating closely with customers throughout the design process. This approach ensures that customers can benefit from Cadence's expertise in navigating the complexities of high-speed design and achieving optimal performance in their AI inference systems.

As the AI market continues to advance, Cadence remains at the forefront by offering a comprehensive memory IP portfolio tailored for every segment of this dynamic market. From DDR5 and HBM3E, which cater to the intensive demands of training in servers and high-performance computing (HPC), to LPDDR5X designed for low-end inference at the network edge and in consumer devices, Cadence's offerings cover a wide range of applications.

Looking to the future, Cadence is dedicated to innovating at the forefront of memory system performance, ensuring that the evolving needs of AI training and inference are met with the highest standards of excellence. Whether it's pushing the boundaries with GDDR7 or exploring new technologies, Cadence is dedicated to driving the AI revolution forward, one breakthrough at a time.

Learn more about Cadence GDDR7 PHY

Learn more about Cadence Simulation VIP for GDDR7.

The demand for higher-performance computing is greater than ever. Cutting-edge applications in artificial intelligence (AI), big data analytics, and databases require high-speed memory systems to handle the ever-increasing volumes and complexities of data. Advancements in cloud computing and machine virtualization are stretching the limits of current capabilities. AI applications hosted in the cloud rely on fast access and reduced latency in memory systems, which is amplified by an increasing number of CPU and GPU cores.

Introducing the DDR5 Multiplexed Rank DIMM (MRDIMM), the next-generation memory module technology designed to meet the needs of high-performance computing (HPC) and AI in cloud applications. By leveraging existing DDR5 DRAM memory devices, MRDIMM modules not only double the DRAM data rate but also maintain the RAS capabilities of the industry-proven RDIMM modules, setting a new precedent for memory module performance.

Let’s compare RDIMM and MRDIMM modules using the same DRAM parts. Today, high-speed production DDR5 RDIMM modules run at 5600Mbps. Those modules use DDR5 DRAM parts, which also run at 5600Mbps. An MRDIMM module using the same DDR5 5600Mbps DRAM parts will run at a blazing 11.2Gbps.

One key metric for best-in-class performance, low bit error rate (BER), and ease of adoption is the eye diagram. The eye diagram illustrates at-speed system margin and accurately represents DDR system quality when captured with a pseudo-random binary sequence (PRBS)-like pattern. The diagram below illustrates Cadence’s 3nm silicon write eye diagram for DDR5 MRDIMM IP running at 12.8Gbps.

Cadence 3nm DDR5 MRDIMM 12.8Gbps test chip write eye diagram, design kit is available today

The eye diagram is captured using a PRBS-like pattern, incorporating a package and system board representative of a typical MRDIMM channel. Using PRBS-like patterns is crucial for capturing accurate eye diagrams. Repetitive clock-like data patterns create deceptively “open eyes” that do not reflect the real system performance. Effects like intersymbol interference, simultaneous switching, reflections, and crosstalk are not accurately reflected in the eye diagrams for parallel interfaces like DDR using non-random data streams. Relying on improperly captured eye diagrams inevitably leads to a significantly worse real system BER than conveyed by that eye diagram.

Doubling the DDR5 RDIMM data rate is challenging. Achieving high performance while optimizing for area and power requires multiple design techniques. Feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and T-coils are required to reach 12.8Gbps MRDIMM data rates in multi-channel systems. Building a production-worthy 12.8Gbps DDR5 MRDIMM IP requires engineering expertise that comes from many generations of memory interface design and production experience. Cadence has developed this expertise through multiple DDR5/4, LPDDR5X/5, and GDDR6 designs in different technology nodes and foundries. For instance, Cadence’s GDDR6 IP is available in three foundries and ten process nodes, with mass production at speeds exceeding 22Gbps.

For your next project, consider DDR5 12.8Gbps MRDIMM, a technology that not only doubles the bandwidth of DDR5 RDIMM but also promises rapid proliferation into next-generation AI, data center, HPC, and enterprise applications. With its cutting-edge capabilities, the Cadence DDR5 12.8Gbps MRDIMM IP is ready to power the future of computing.

Explore Impacts of Finite Interconnect Impedance on PDN Characterization

Over the past few decades, many details have been worked out in the power distribution network (PDN) in the frequency and time domains. We have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior. We also have frequency- and time-domain test methods to measure the steady-state and transient behavior of the built-up systems.

All of these pieces in our current toolbox have their own assumptions, limitations, and artifacts, and they constantly raise the challenging question that designers need to answer: How to select the design process, simulation, measurement tools, and processes so that we get reasonable answers within a reasonable time frame with a reasonable budget.

Read this award-winning DesignCon 2024 paper titled “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.” Led by Samtec’s Istvan Novak and written with a team of nine authors from Cadence, Amazon, and Samtec, the paper discusses a series of continually evolving challenges with PDN requirements for cutting-edge designs.

Read the full paper now: “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.”

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per DIMM card. The highest speed DDR5 SDRAM devices can support data rates of up to 8800 MTps.

DDR5 SO-DIMMs and UDIMMs

One of the most recognized uses of PCDDR is with client devices like laptops and personal computers. These client devices mostly use two types of DDR5 DIMMs called SO-DIMM (Small Outline Dual Inline Memory Module) and UDIMM (Unbuffered Dual Inline Memory Module).

These types of DIMMs have no signal regeneration or buffering (which, for example, the Registering Clock Driver or the RCD does for clocks/command/control signals for a registered DIMMs). A typical 2-Rank UDIMM with x8 DDR5 SDRAM components has 8 or 10 components per rank depending on the system ECC (Error Correction Code) memory being part of the DIMM.

Why DDR5 Clock Buffer and CUDIMM?

Clocks are one of the most important signals for synchronous devices, and DDR5 SDRAMs are no exception. The host is responsible for the fanout to all the DRAM input ports, such as clocks for UDIMMs. Driving of all these DRAM clocks can put quite a bit of load on the host output drivers, thus affecting the signal quality, which can result in unexpected memory errors. This issue gets amplified when operating at the higher clock and data rates where the clock signals transition from one logic value to the next over a very short time. To solve these signal integrity issues with DRAM clocks, JEDEC has come up with a new type of DDR5 DIMM component that is called DDR5 clock buffer. Clock buffers can be used for both DDR5 SO-DIMMs and DDR5 UDIMMs. DDR5 UDIMMs that include a clock buffer component as part of the DIMM card are called DDR5 CUDIMMs (Clock Buffered UDIMMs).

DDR5 Clock Buffer Overview

DDR5 Clock Buffer is a simple logic device that takes in two sets of input clock pins and drives two sets of clock pins as output per channel. The clock buffer device can operate in three types of clock modes: -

• PLL bypass mode: In this mode, the clock buffer just passes on the input clocks to output without any kind of signal buffering. The PLL bypass mode enabled CUDIMM devices behave like traditional UDIMMs without any buffering of the clocks. This is why it’s also referred to as legacy mode. Recommended CUDIMM operating speeds in PLL bypass mode are typically limited to 3000 MHz.

• Single PLL mode: In the single PLL Mode, the clock buffer device will use a Phase Lock Loop (PLL) for the regeneration of the incoming host clock to create a better-quality clock that is sent to the DRAMs. However, since there is only one PLL that is used in this mode, both sub channel output clocks will be driven based on only one set of input clocks with the other set of input clocks remaining unused.

• Dual PLL mode: In this mode, the clock buffer will use two PLLs to independently generate each sub channel output clock based on each set of incoming host clocks. The second set of PLL can be turned on or off on the fly if needed to save power.

Beyond the clock modes, clock buffers provide additional flexibility to the system designers with register-controlled additional signal delays, optional output clock enable/disable per bit feature, drive strength and termination choices, etc. All DDR5 clock buffer device control word registers are accessible via DDR5 DIMM sideband.

Cadence VIPs offers a compressive memory subsystem solution that includes memory models for DDR5 SDRAM, DDR5 RCD, DDR5 DB, DDR5 clock buffer, all types of DDR5 DIMMs, including the DDR5 CUDIMMs, DFI Memory Controller/PHY VIPs, and a system VIP compliant to JEDEC specifications defined for each of those devices along with latest DFI Specification.

More information on Cadence DDR5 DIMM VIP is available at the Cadence VIP Memory Models website.

DDR5 DIMM Architectures The DDR5 generation of Double Data Rate DRAM memories has experienced rapid adoption in recent years. In particular, the JEDEC-defined DDR5 Dual Inline Memory Module (DIMM) cards have become a mainstay for systems looking for high-density, high-bandwidth, off-chip random access memory[1]. Within a short time, the DIMM architecture evolved from an interconnected hierarchy of only SDRAM memory devices (UDIMM[2]) to complex subsystems of interconnected components (RDIMM/LRDIMM/MRDIMM[3]). DIMM Designs and Popular Verification Use Cases The growing complexity of the DIMMs presented a challenge for pre-silicon verification engineers who could no longer simply validate against single DDR5 SDRAM memory models. They needed to consider how their designs would perform against DIMMs connected to each channel and operating at gigahertz clock speeds. To address this verification gap, Cadence developed DDR5 DIMM Memory Models that encapsulated all of the architectural complexities presented by real-world DIMMs based on a robust, easy-to-use, easy-to-debug, and easy-to-reconfigure methodology. This memory-subsystem-in-a-single-instance model has seen explosive adoption among the traditional IP Developer and SOC Integrator customers of Cadence Memory Models. The Cadence DIMM models act as a single unit with all of the relevant DIMM components instantiated and interconnected within, and with all AC/Timing parameters among the various components fully matched out-of-the-box, based on JEDEC specifications as well as datasheets of actual devices in the market. The typical use-case for the DIMM models has been where the DUT is a DDR5 Memory Controller + PHY IP stack, and the validation plan mandated compliance with the JEDEC standards and Memory Device vendor datasheets. Unique Use Case for the DIMM Discrete Component Models Although the Cadence DIMM models have enjoyed tremendous proliferation because of their cohesive implementation and unified user API, the actual DIMM Models are built on top of powerful, flexible discrete component models, each of which was designed to stand on its own as a complete SystemVerilog UVM-based VIP. All of these discrete component models exist in the Cadence VIP Catalog as standalone VIPs, complete with their own protocol compliance checking capabilities and their own configuration mappings comprehensively modeling individual AC/Timing parameters. Because of this deliberate design decision, the Cadence DIMM Discrete Component Models can support a unique use-case scenario. Some users seek to develop IC Designs for the various DIMM components. Such users need verification environments that can model the individual components of a DIMM and allow them the option to replace one or another component with their Component Design IP. They can then validate that their component design is fully compatible with the rest of the components on the DIMM and meets the integrity of the overall DIMM compliance with JEDEC standards or Memory Vendor datasheets. The Cadence Memory VIP portfolio today includes various examples that demonstrate how customers can create DIMM “wrappers” by selecting from among the available DIMM discrete component models and “stitching” them together to build their own custom testbench around their specific Component Design IP. A Solution for Unique Component Scenarios The Cadence DDR5 DIMM Memory Models and DIMM Discrete Component Models can provide users with a flexible approach to validating their specific component designs with a fully populated pre-silicon environment. Augmented Verification Capabilities When the DIMM “wrapper” model is augmented with the Cadence DFI VIP[4] that can simulate an MC+PHY stack and offers a SystemVerilog UVM test API to the verification engineer, the overall testbench transforms into a formidable pre-silicon validation vehicle. The DFI VIP is designed as a combination of an independent DFI MC VIP and a DFI PHY VIP connected to each other via the DFI Standard Interface and capable of operating seamlessly as a single unit. It presents a UVM Sequence API to the user into the DFI MC VIP with the Memory Interface of the PHY VIP connected to the DIMM “wrapper” model. With this testbench in hand, the user can then fully take advantage of the UVM Sequence Library that comes with the DFI VIP to enable deep validation of their Component Design inside the DIMM “wrapper” model. Verification Capabilities Further Enhanced A possible further enhancement comes with the potential addition of an instance of the Cadence DIMM Memory Model in a Passive Monitor mode at the DRAM Memory Interface. The DIMM Passive Monitor consumes the same configuration describing the DIMM “wrapper” in the testbench, and thus can act as a reference model for the DIMM wrapper. If the DIMM Passive Monitor responds successfully to accesses from the DFI VIP, but the DIMM wrapper does not, then it exposes potential bugs in the DUT Components or in the settings of their AC/Timing parameters inside the DIMM wrapper. Debuggability, Interface Visibility, and Protocol Compliance One of the key benefits of the DIMM Discrete Component Models that become manifest, whether in terms of the unique use-case scenario described here, or when working with the wholly unified DDR5 DIMM Memory Models, is the increased debuggability of the protocol functionality. The intentional separation of the discrete components of a DIMM allows the user to have full visibility of the memory traffic at every datapath landmark within a DIMM structure. For example, in modeling an LRDIMM or MRDIMM, the interface between the RCD component and the SDRAM components, the interface between the RCD component and the DB components, and the interface between the SDRAM components and the DB components—all are visible and accessible to the user. The user has full access to dump the values and states of the wire interconnects at these interfaces to the waveform viewer and thus can observe and correlate the activity against any protocol violations flagged in the trace logs by any one or more of the DIMM Discrete Component Models. Access to these interfaces is freely available when using the DIMM Discrete Component Models. On the unified DDR5 DIMM Memory Models, a feature called Debug Ports enables the same level of visibility into the individual interconnects amidst the SDRAM components, RCD components, and DB components. When combined with the Waveform Debugger[5] capability that comes built-in with the VIPs and Memory Models offered by Cadence and used with the Cadence Verisium Debug[6] tool, the enhanced debuggability becomes a powerful platform. With these debug accesses enabled, the user can pull out transaction streams, chip state and bank state streams, mode register streams, and error message streams all right next to their RTL signals in the same Verisium Debug waveform viewer window to debug failures all in one place. The Verisium Debug tool also parses all of the log files to probe and extract messages into a fully integrated Smart Log in a tabbed window fully hyperlinked to the waveform viewer, all at your fingertips. A Solution for Every Scenario Cadence's DDR5 DIMM Memory Models and DIMM Discrete Component Models , partnered with the Cadence DFI VIP, can provide users with a robust and flexible approach to validating their designs thoroughly and effectively in pre-silicon verification environments ahead of tapeout commitments. The solution offers unparalleled latitude in debuggability when the Debug Ports and Waveform Debugger functions of the Memory Models are switched on and boosted with the use of the Cadence Verisium Debug tool. [1] Shyam Sharma, DDR5 DIMM Design and Verification Considerations , 13 Jan 2023. [2] Shyam Sharma, DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM) , 23 Sep 2024. [3] Kos Gitchev, DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers , 26 Aug 2024. [4] Chetan Shingala and Salehabibi Shaikh, How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device? , 29 Mar 2022. [5] Rahul Jha, Cadence Memory Models - The Gold Standard , 15 Apr 2024. [6] Manisha Pradhan, Accelerate Design Debugging Using Verisium Debug , 11 Jul 2023.

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