Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the...

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In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution....

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We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro® Package Designer Plus layout tools allowing you to work...

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If I talk about my life, it was much simpler when I used to live with my parents. They took good care of whatever I wanted - in fact, they still do. But now, I am living alone, and sometimes I buy...

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Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

All PCB designers know the importance of proper power delivery for successful board design. Integrated circuits need the power to turn on, and ICs with marginal power delivery will not operate reliably. Since power planes can...(read more)

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)

So, what if you can figure out all that can go wrong when your product is being assembled early on? Not guess but know and correct at an early stage – not wait for the fabricator or manufacturer to send you a long report of what needs to change. That’s why Design for Assembly (DFA) rules(read more)

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Hi supporters,

I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20):

----

ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
ncsim: *E,DLOALB: Design library 'tcbnxxx' not defined while reading module tcbnxxx.MAOxxx:bv (VST).
ncsim: *F,NOSIMU: Errors initializing simulation 'alu_tb' 

----

xxx: standard library name.

My netlist design uses a cell "MAOxxx". I already included the library behavior model to compile using ncverilog, there is no error while compiling. But when I run with ncsim to execute the test, I got above error.

I tried to run with other vendors such as VCS or MTI, they worked.

Please help to understand the error.

Thanks.

Hi

     I want develope basic circuit of DC motor which consist of resistor, inductor and back emf in capture and check its simulation in pspice, for reference I have attached image and link.

https://www.precisionmicrodrives.com/content/ab-025-using-spice-to-model-dc-motors/ .

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...(read more)

  A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...(read more)

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...(read more)

Variants seem to be defined as present or not present.

Is there a variant that can assign different parts to the same reference designator? i.e.  R17 can be either 0 ohm 0805 jumper or 12k ohms 0805 resistor.

The simplest way I can think of is to use two parts with the same footprint and overlay them.

Is there a more functional way of doing this?  So that the variant would put the correct part in the BOM and the parts would of course have the same identical footprint.

Hello All,

I'm currently using OrCAD PCB Designer Professional w/ PSpice (version 16.6-2015).  In the 'Design Object Find Filter' side bar, all options are grayed out and unselectable.  I did attempt to 'Reset UI to Cadence Default' without any luck.  A colleague has no issues with the identical file on his computer.  Any guidance would be much appreciated.  Thanks!

George

Hi,

I have a new customer that uses Allegro Design entry HDL for the schematic and have a few questions.

1. How do you get pin/gate swaps into the symbols in the schematic ?

2. How do you transfer them to the pcb editor ?

3. How do you back annotate the swaps from the pcb editor to the schematic ?

4. How do you stop the export/Import physical from updating the constraints in the pcb file ? 

Try looking at www.solidwoodkitchen.co.uk. They have some amazing designs and prices.

Kitchen Design Manchester

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning! (read more)

Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These and other low power techniques are applied on both analog and digital parts of the design. Digital designers capture power intent in standard formats like Common Power Format (CPF), IEEE1801 (aka Unified Power Format or UPF) or Liberty and apply it top-down throughout design, verification and implementation flows. Analog parts are often designed bottom-up in schematic without upfront defined power intent. Verifying that low power intent is implemented correctly in mixed-signal design is very challenging. If not discovered early, errors like wrongly connected power nets, missing level shifters or isolations cells can cause costly rework or even silicon re-spin. 

Mixed-signal designers rely on simulation for functional verification. Although still necessary for electrical and performance verification, running simulation on so many power modes is not an effective verification method to discover low power errors. It would be nice to augment simulation with formal low power verification but a specification of power intent for analog/mixed-signal blocs is missing. So how do we obtain it? Can we “extract” it from already built analog circuit? Fortunately, yes we can, and we will describe an automated way to do so!

Virtuoso Power Manager is new tool released in the Virtuoso IC6.1.8 platform which is capable of managing power intent in an Analog/MS design which is captured in Virtuoso Schematic Editor. In setup phase, the user identifies power and ground nets and registers special devices like level shifters and isolation cells. The user has the option to import power intent into IEEE1801 format, applicable for top level or any of the blocks in design. Virtuoso Power Manager uses this information to traverse the schematic and extract complete power intent for the entire design. In the final stage, Virtuoso Power Manager exports the power intent in IEEE1801 format as an input to the formal verification tool (Cadence Conformal-LP) for static verification of power intent.

Cadence and Infineon have been collaborating on the requirements and validation of the Virtuoso Power Manager tool and Low Power verification solution on real designs. A summary of collaboration results were presented at the DVCon conference in Munich, in October of 2018.  Please look for the paper in the conference proceedings for more details. Alternately, can view our Cadence webinar on Verifying Low-Power Intent in Mixed-Signal Design Using Formal Method for more information.

Do you want to create designs that are correct by construction? Read along this blog to understand how you can achieve this by using Width Spacing Patterns (WSPs) in your designs. WSPs, are track lines that provide guidance for quickly creating wires. Defining WSPs that capture the width-dependent spacing rules, and snapping the pathSegs of a wire to them, ensures that the wires meet width-dependent spacing rules.(read more)

•Customers can seamlessly extend their design to manufacturing ecosystem to the cloud with the integrated 3DEXPERIENCE.WORKS portfolio, enabling new levels of functionality, collaboration, agility and operational efficiency •Latest release of 3D design and engineering portfolio features hundreds of enhancements, new capabilities and workflows to accelerate and improve product development •Over six million SOLIDWORKS users can innovate products faster with better performance and streamlined...

This whitepaper goes into detail on design and implementation details for performing voice encryption on telephone networks. Written in Spanish.

Care Technology provides technological solutions to the needs of customers through innovations like energy-efficient LED lighting and transportable heat sources that operate without power racks or induction heaters. We spoke to co-founder Belinda Wong about the production of their sustainable offerings and the benefits of green technology.

Naval shipbuilder Navantia Australia, a subsidiary of Spain-based Navantia S.A., has opened a new design and engineering centre in Melbourne.

The U.S. House of Representatives has passed bipartisan hydroelectric power regulatory improvement provisions as part of the North American Energy Security and Infrastructure Act of 2015, potentially helping to expedite the project approval process.

Bolivia’s President Evo Morales has approved a supreme decree to carry out final design studies for the 3,251-MW El Chepete and 425-MW El Bala hydro projects in La Paz department.

Presentation by Dave McGregor of DuPont

Presentation by Glenn Oliver of DuPont Electronic Technologies.

The US has elevated its ambassador to Belgium, former businessman Ronald J. Gidwitz, to the post of caretaker ambassador to the EU, it said Tuesday, adding he will "advance a strong US-EU partnership", help Europe in its economic recovery after the pandemic, and promote "our shared interests and values across the globe." The last US ambassador to the EU, businessman Gordon Sondland, left in disgrace over a Ukraine blackmail scandal.

NVIDIA Chief Scientist Bill Dally this week released an open-source design for a low-cost, easy-to-assemble mechanical ventilator. The ventilator, designed in just a few weeks by Dally — whose storied technology career includes key contributions to semiconductors and supercomputers — can be built quickly from just $400 of off-the-shelf parts, Dally says. Traditional ventilators, by Read article >

The post NVIDIA Chief Scientist Releases Low-Cost, Open-Source Ventilator Design appeared first on The Official NVIDIA Blog.

NVIDIA Chief Scientist Bill Dally this week released an open-source design for a low-cost, easy-to-assemble mechanical ventilator. The ventilator, designed in just a few weeks by Dally — whose storied technology career includes key contributions to semiconductors and supercomputers — can be built quickly from just $400 of off-the-shelf parts, Dally says. Traditional ventilators, by Read article >

The post NVIDIA Chief Scientist Releases Low-Cost, Open-Source Ventilator Design appeared first on The Official NVIDIA Blog.

In response to Government guidance on maintaining educational provision for the children of key workers, the FCA and PRA have published guidance regarding individuals in th...

Re-examining the design of rural road projects will make them more effective in improving the lives of the people living nearby.

Carefully designed social programs offer the best chance to avoid corruption, inefficiency and other governance problems. 

Resolver Replacement Reference Design

STAMFORD, CT -- HARMAN International Industries, Inc. (NYSE:HAR), the premium global audio and infotainment group, announced today that 19 of its audio products have been selected as winners in the prestigious Red Dot Award: Product Design 2014 competition.

You heard it here first: in 2018, HARMAN received a record-breaking 53 product design and technology awards, bringing our six-year-total to more than 300 awards for 190 different products.   This unprecedented number is a direct reflection of our...

Today’s companies see the importance of design as more consumers demand elegance alongside flawless functionality and exceptional user experience. As a company that has created countless ingenious product designs in different markets all over the ...

CES 2020, LAS VEGAS – JANUARY 6, 2020 – Today, JBL is introducing its first headphone series inspired by touring musicians, the JBL CLUB. Equipped with Legendary JBL Pro Sound, Personi-Fi™ and native voice assistants, the JBL CLUB series – CLUB ONE, CLUB...

Huemen, HARMAN’s in-house design agency, brings home 25 iF World Design Awards

Music and driving are a powerful combination, and JBL automotive sound is designed to connect consumers to their vehicles at an emotional level. From Italy-based creative agency Garage Italia to leading auto manufacturers who leverage JBL’s audio ...

We’re thrilled to announce that HARMAN’s QLED Auto solution has been recognized in the User Experience category in Fast Company’s 2019 Innovation by Design Awards.