Before I ask this, I am aware that I can output an s-parameter file from an SP analysis.

I'm wondering if there is a simple way of creating an s-parameter model of a component.

As an example, if I have an S-parameter model that has 200 ports and 150 of those ports are to be connected to passive components and the remaining 50 ports are to be connected to active components, I can simplify the model by connecting the 150 passive components, running an SP analysis, and generating a 50 port S-parameter file.

The problem is that this is cumbersome. You've got to wire up 50 PORT components and then after generating the s50p file, create a new cellview with an nport component and connect the 50 ports with 50 new pins.

Wiring up all of those port components takes quite a lot of time to do, especially as the "choosing analyses" form adds arrays in reverse (e.g. if you click on an array of PORT components called X<0:2> it will add X<2>, X<1>, X<0> instead of in ascending order) so you have to add all of them to the analyses form manually.

Is any way of taking a schematic and running some magic "generate S-Parameter cellview from schematic cellview"  function that automates the whole process?

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test equipment. Among the semiconductor designs they create for these products is a test processor chip with over 100 million logic transistors, but also with lots of analog functions.They set out to find a way to speed up their full-chip simulations to a point where they could run the system software. To do that, they needed about a 50X speed-up. Well, they did it!

Figure 1: Advantest SoC Test Products

To skip the commentary, read Advantest's paper here. 

Problem Statement

Software is becoming a bigger part of just about every hardware product in every market today, and that includes the semiconductor test market. To achieve high product quality in the shortest amount of time, the hardware and software components need to be verified together as early in the design cycle as possible. However, the throughput of a typical software RTL simulation is not sufficient to run significant amounts of software on a design with hundreds of millions of transistors.  

Executing software on RTL models of the hardware means long runs  (“deep cycles”) that are a great fit for an emulator, but the mixed-signal content posed a new type of challenge for the Advantest team.  Emulators are designed to run digital logic. Analog is really outside of the expected use model. The Advantest team examined the pros and cons of various co-simulation and acceleration flows intended for mixed signal and did not feel that they could possibly get the performance they needed to have practical runtimes with software testbenches. They became determined to find a way to apply their Palladium XP platform to the problem.

Armed with the knowledge of the essential relationship between the analog operations and the logic and software operations, the team was able to craft models of the analog blocks using reduction techniques that accurately depicted the essence of the analog function required for hardware-software verification without the expense of a continuous time simulation engine.

The requirements boiled down to the following:

• Generation of digital signals with highly accurate and flexible timing

• Complete chip needs to run on Palladium XP platform

• Create high-resolution timing (100fs) with reasonable emulation performance, i.e. at least 50X faster than simulation on the fastest workstations

Solution Idea

The solution approach chosen was to simplify the functional model of the analog elements of the design down to generation of digital signal edges with high timing accuracy. The solution employed a fixed-frequency central clock that was used as a reference.Timing-critical analog signals used to produce accurately placed digital outputs were encoded into multi-bit representations that modeled the transition and timing behavior. A cell library was created that took the encoded signals and converted them to desired “regular signals”. 

Automation was added to the process by changing the netlisting to widen the analog signals according to user-specified schematic annotations. All of this was done in a fashion that is compatible with debugging in Cadence’s Simvision tool.  Details on all of these facets to follow.

The Timing Description Unit (TDU) Format

The innovative thinking that enabled the use of Palladium XP was the idea of combining a reference clock and quantized signal encoding to create offsets from the reference. The implementation of these ideas was done in a general manner so that different bit widths could easily be used to control the quantization accuracy.

Figure 2: Quantization method using signal encoding

Timed Cell Modeling

You might be thinking – timing and emulation, together..!?  Yes, and here’s a method to do it….

The engineering work in realizing the TDU idea involved the creation of a library of cells that could be used to compose the functions that convert the encoded signal into the “real signals” (timing-accurate digital output signals). Beyond some basic logic cells (e.g., INV, AND, OR, MUX, DFF, TFF, LATCH), some special cells such as window-latch, phase-detect, vernier-delay-line, and clock-generator were created. The converter functions were all composed from these basic cells. This approach ensured an easy path from design into emulation.

The solution was made parameterizable to handle varying needs for accuracy.  Single bit inputs need to be translated into transitions at offset zero or a high or low coding depending on the previous state.  Single bit outputs deliver the final state of the high-resolution output either at time zero, the next falling, or the next rising edge of the grid clock, selectable by parameter. Output transitions can optionally be filtered to conform to a configurable minimum pulse width.

Timed Cell Structure

There are four critical elements to the design of the conversion function blocks (time cells):

                Input conditioning – convert to zero-offset, optional glitch preservation, and multi-cycle path

                Transition sorting – sort transitions according to timing offset and specified precedence

                Function – for each input transition, create appropriate output transition

                Output filtering – Capability to optionally remove multiple transitions, zero-width, pulses, etc.

Timed Cell Caveat

All of the cells are combinational and deliver a result in the same cycle of an input transition. This holds for storage elements as well. For example a DFF will have a feedback to hold its state. Because feedback creates combinational loops, the loops need a designation to be broken (using a brk input conditioning function in this case – more on this later). This creates an additional requirement for flip-flop clock signals to be restricted to two edges per reference clock cycle.

Note that without minimum width filtering, the number of output transitions of logic gates is the sum of all input transitions (potentially lots of switching activity). Also note that the delay cell has the effect of doubling the number of output transitions per input transition.

Figure 3: Edge doubling will increase switching during execution

SimVision Debug Support

The debug process was set up to revolve around VCD file processing and directed and viewed within the SimVision debug tool. In order to understand what is going on from a functional standpoint, the raw simulation output processes the encoded signals so that they appear as high-precision timing signals in the waveform viewer. The flow is shown in the figure below.

Figure 4: Waveform post-processing flow

The result is the flow is a functional debug view that includes association across representations of the design and testbench, including those high-precision timing signals.

Figure 5: Simvision debug window setup

Overview of the Design Under Verification (DUV)

Verification has to prove that analog design works correctly together with the digital part. The critical elements to verify include:

• Programmable delay lines move data edges with sub-ps resolution

• PLL generates clocks with wide range of programmable frequency

• High-speed data stream at output of analog is correct

These goals can be achieved only if parts of the analog design are represented with fine resolution timing.

Figure 6: Mixed-signal design partitioning for verification

How to Get to a Verilog Model of the Analog Design

There was an existing Verilog cell library with basic building blocks that included:

- Gates, flip-flops, muxes, latches

- Behavioral models of programmable delay elements, PLL, loop filter, phase detector

With a traditional simulation approach, a cell-based netlist of the analog schematic is created. This netlist is integrated with the Verilog description of the digital design and can be simulated with a normal workstation. To use Palladium simulation, the (non-synthesizable) portions of the analog design that require fine resolution timing have to be replaced by digital timing representation. This modeling task is completed by using a combination of the existing Verilog cell library and the newly developed timed cells.

Loop Breaking

One of the chief characteristics of the timed cells is that they contain only combinational cells that propagate logic from inputs to outputs. Any feedback from a cell’s transitive fanout back to an input creates a combinational loop that must be broken to reach a steady state. Although the Palladium XP loop breaking algorithm works correctly, the timed cells provided a unique challenge that led to unpredictable results.  Thus, a process was developed to ensure predictable loop breaking behavior. The user input to the process was to provide a property at the loop origin that the netlister recognized and translated to the appropriate loop breaking directives.

Augmented Netlisting

Ease of use and flow automation were two primary considerations in creating a solution that could be deployed more broadly. That made creating a one-step netlisting process a high-value item. The signal point annotation and automatic hierarchy expansion of the “digital timing” parameter helped achieve that goal. The netlister was enriched to identify the key schematic annotations at any point in the hierarchy, including bit and bus signals.

Consistency checking and annotation reporting created a log useful in debugging and evolving the solution.

Wrapper Cell Modeling and Verification

The netlister generates a list of schematic instances at the designated “netlister stop level” for each instance the requires a Verilog model with fine resolution timing. For the design in this paper there were 160 such instances.

The library of timed cells was created; these cells were actually “wrapper” cells comprised of the primitives for timed cell modeling described above. A new verification flow was created that used the behavior of the primitive cells as a reference for the expected behavior of the composed cells. The testing of the composed cells included had the timing width parameter set to 1 to enable direct comparison to the primitive cells. The Cadence Incisive Enterprise Simullator tool was successfully employed to perform assertion-based verification of the composed cells versus the existing primitive cells.

Mapping and Long Paths

Initial experiments showed that inclusion of the fine resolution timed cells into the digital emulation environment would about double the required capacity per run. As previously pointed out, the timed cells having only combinational forward paths creates a loop issue. This fact also had the result of creating some such paths that were more than 5,000 steps of logic. A timed cell optimization process helped to solve this problem. The basic idea was to break the path up by adding flip-flops in strategic locations to reduce combinational path length. The reason that this is important is that the maximum achievable emulation speed is related to combinational path length.

Results

Once the flow was in place, and some realistic test cases were run through it, some further performance tuning opportunities were discovered to additionally reduce runtimes (e.g., Palladium XP tbrun mode was used to gain speed). The reference used for overall speed gains on this solution was versus a purely software-based solution on the highest performance workstation available.

The findings of the performance comparison were startlingly good:

• On Palladium XP, the simulation speed is 50X faster than on Advantest’s fastest workstation

• Software simulation running 25 days can now be run in 12 hours -> realistic runtime enables long-running tests that were not feasible before

• Now have 500 tests that execute once in more than 48 hours

• They can be run much more frequently using randomization and this will increase test coverage dramatically

Steve Carlson

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor, analog behavioral and real-number model (RNM) and RTL levels, and combination of these.

In recent years, RNM and simulation is being adopted for functional verification by many, due to advantages it offers including simpler modeling requirements and much faster simulation speed (compared to a traditional analog behavioral models like Verilog-A or VHDL-AMS). Verilog-AMS with its wreal continue to be popular choice. Standardization of real number extensions in SystemVerilog (SV) made SV-RNM an even more attractive choice for MS SoC verification.

Verilog-AMS/wreal is scalar real type. SV-RNM offers a powerful ability to define complex data types, providing a user-defined structure (record) to describe the net value. In a typical design, most analog nodes can be modeled using a single value for passing a voltage (or current) from one module to another. The ability to pass multiple values over a net can be very powerful when, for example, the impedance load impact on an analog signal needs to be modeled. Here is an example of a user-defined net (UDN) structure that holds voltage, current, and resistance values:

When there are multiple drives on a single net, the simulator will need a resolution function to determine the final net value. When the net is just defined as a single real value, common resolution functions such as min, max, average, and sum are built into the simulator.  But definition of more complex structures for the net also requires the user to provide appropriate resolution functions for them. Here is an example of a net with three drivers modeled using the above defined structural elements (a voltage source with series resistance, a resistive load, and a current source):

To properly solve for the resulting output voltage, the resolution function for this net needs to perform Norton conversion of the elements, sum their currents and conductances, and then calculate the resolved output voltage as the sum of currents divided by sum of conductances.

With some basic understanding of circuit theory, engineers can use SV-RNM UDN capability to model electrical behavior of many different circuits. While it is primarily defined to describe source/load impedance interactions, its use can be extended to include systems including capacitors, switching circuits, RC interconnect, charge pumps, power regulators, and others. Although this approach extends the scope of functional verification, it is not a replacement for transistor-level simulation when accuracy, performance verification, or silicon correlation are required:  It simply provides an efficient solution for discretely modeling small analog networks (one to several nodes).  Mixed-signal simulation with an analog solver is still the best solution when large nonlinear networks must be evaluated.

Cadence provides a tutorial on EEnet usage as well as the package (EEnet.pkg) with UDN definitions and resolution functions and modeling examples. To learn more, please login to your Cadence account to access the tutorial.

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic simulation is an activity where following that advice has enormous payoffs. In this blog I’ll talk about some of my experiences with how Virtuoso RF Solution’s shape simplification feature has helped my customers get significant performance improvements with minimal impacts on accuracy. (read more)

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A vulnerability associated with Use of Hard-coded Credentials (CWE-798) exists in Simulation Process Intelligence (3DOrchestrate Services) on premises licensed program. The security risk is evaluated as High (CVSS v.3.0 Base Score 8.0) and affects all 3DEXPERIENCE releases (from 3DEXPERIENCE R2014x to 3DEXPERIENCE R2020x).

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People in Germany are more pessimistic than the rest of Europe regarding their country’s progress on its energy transition, or engergiewende.

People in Germany are more pessimistic than the rest of Europe regarding their country’s progress on its energy transition, or engergiewende.

Presentation by Jason Fullerton of ACI Technologies, Inc.

People in Germany are more pessimistic than the rest of Europe regarding their country’s progress on its energy transition, or engergiewende.

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The post 5 Simple Tips to Finding Your Perfect .com Domain Name (Plus 2 Bonus Ones!) appeared first on Verisign Blog.

Simplifying finance vehicles for renewable energy will lure more investors and lower the costs of capital.

The Wekundu wa Msimbazi winger has been out for a considerable period as he was injured during international duty for the Taifa Stars ......

Why is the visual depiction of this country in centre-left international online news publications so unrecognisable?

The post What is this place?: The visual simulacrum of South Africa in the Covid-19 lockdown appeared first on The Mail & Guardian.

In nationwide demonstrations over the last few days, Israeli women are demanding help with the spike violence against women during the COVID-19 crisis.

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Microchip Simplifies Functional Safety Requirements with MPLAB TÜV SÜD-certified Tools

Due to the global COVID-19 pandemic, engineers and scientists are finding themselves suddenly working from home or other remote locations. We’d like to help you continue to use MATLAB and Simulink productively. We hope this brief collection of resources will help you access MATLAB, collaborate and connect with others, and... read more >>

A sophisticated computer simulation of the universe, approximately 1 billion light years across, is modelling tens of thousands of galaxies

Google's Sycamore quantum computer, which recently demonstrated its dominance over ordinary computers, is now breaking records in quantum chemistry

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Payne Capital Management's Courtney Dominguez says the high level of investor pessimism indicates the markets may have bottomed. She says savings could make their way into stocks.

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ABSTRACT

Bacteria harbor viruses called bacteriophages that, like all viruses, co-opt the host cellular machinery to replicate. Although this relationship is at first glance parasitic, there are social interactions among and between bacteriophages and their bacterial hosts. These social interactions can take on many forms, including cooperation, altruism, and cheating. Such behaviors among individuals in groups of bacteria have been well described. However, the social nature of some interactions between phages or phages and bacteria is only now becoming clear. We are just beginning to understand how bacteriophages affect the sociobiology of bacteria, and we know even less about social interactions within bacteriophage populations. In this review, we discuss recent developments in our understanding of bacteriophage sociobiology, including how selective pressures influence the outcomes of social interactions between populations of bacteria and bacteriophages. We also explore how tripartite social interactions between bacteria, bacteriophages, and an animal host affect host-microbe interactions. Finally, we argue that understanding the sociobiology of bacteriophages will have implications for the therapeutic use of bacteriophages to treat bacterial infections.

ABSTRACT

Dimethylsulfoniopropionate (DMSP) is abundant in marine environments and an important source of reduced carbon and sulfur for marine bacteria. While both Ruegeria pomeroyi and Ruegeria lacuscaerulensis possessed genes encoding the DMSP demethylation and cleavage pathways, their responses to DMSP differed. A glucose-fed, chemostat culture of R. pomeroyi consumed 99% of the DMSP even when fed a high concentration of 5 mM. At the same time, cultures released 19% and 7.1% of the DMSP as dimethylsulfide (DMS) and methanethiol, respectively. Under the same conditions, R. lacuscaerulensis consumed only 28% of the DMSP and formed one-third of the amount of gases. To examine the pathways of sulfur and methyl C assimilation, glucose-fed chemostats of both species were fed 100 μM mixtures of unlabeled and doubly labeled [dimethyl-¹³C, ³⁴S]DMSP. Both species derived nearly all of their sulfur from DMSP despite high sulfate availability. In addition, only 33% and 50% of the methionine was biosynthesized from the direct capture of methanethiol in R. pomeroyi and R. lacuscaerulensis, respectively. The remaining methionine was biosynthesized by the random assembly of free sulfide and methyl-tetrahydrofolate derived from DMSP. Thus, although the two species possessed similar genes encoding DMSP metabolism, their growth responses were very different.

IMPORTANCE Dimethylsulfoniopropionate (DMSP) is abundant in marine environments and an important source of reduced carbon and sulfur for marine bacteria. DMSP is the precursor for the majority of atmospheric dimethylsulfide (DMS), a climatically active gas that connects the marine and terrestrial sulfur cycles. Although research into the assimilation of DMSP has been conducted for over 20 years, the fate of DMSP in microbial biomass is not well understood. In particular, the biosynthesis of methionine from DMSP has been a focal point, and it has been widely believed that most methionine was synthesized via the direct capture of methanethiol. Using an isotopic labeling strategy, we have demonstrated that the direct capture of methanethiol is not the primary pathway used for methionine biosynthesis in two Ruegeria species, a genus comprised primarily of globally abundant marine bacteria. Furthermore, although the catabolism of DMSP by these species varied greatly, the anabolic pathways were highly conserved.

ABSTRACT

Many HIV prevention strategies are currently under consideration where it is highly informative to know the study participants’ times of infection. These can be estimated using viral sequence data sampled early in infection. However, there are several scenarios that, if not addressed, can skew timing estimates. These include multiple transmitted/founder (TF) viruses, APOBEC (apolipoprotein B mRNA editing enzyme, catalytic polypeptide-like)-mediated mutational enrichment, and recombination. Here, we suggest a pipeline to identify these problems and resolve the biases that they introduce. We then compare two modeling strategies to obtain timing estimates from sequence data. The first, Poisson Fitter (PF), is based on a Poisson model of random accumulation of mutations relative to the TF virus (or viruses) that established the infection. The second uses a coalescence-based phylogenetic strategy as implemented in BEAST. The comparison is based on timing predictions using plasma viral RNA (cDNA) sequence data from 28 simian-human immunodeficiency virus (SHIV)-infected animals for which the exact day of infection is known. In this particular setting, based on nucleotide sequences from samples obtained in early infection, the Poisson method yielded more accurate, more precise, and unbiased estimates for the time of infection than did the explored implementations of BEAST.

IMPORTANCE The inference of the time of infection is a critical parameter in testing the efficacy of clinical interventions in protecting against HIV-1 infection. For example, in clinical trials evaluating the efficacy of passively delivered antibodies (Abs) for preventing infections, accurate time of infection data are essential for discerning levels of the Abs required to confer protection, given the natural Ab decay rate in the human body. In such trials, genetic sequences from early in the infection are regularly sampled from study participants, generally prior to immune selection, when the viral population is still expanding and genetic diversity is low. In this particular setting of early viral growth, the Poisson method is superior to the alternative approach based on coalescent methods. This approach can also be applied in human vaccine trials, where accurate estimates of infection times help ascertain if vaccine-elicited immune protection wanes over time.

ABSTRACT

Simian immunodeficiency virus (SIV)-infected nonhuman primates can serve as a relevant model for AIDS neuropathogenesis. Current SIV-induced encephalitis (SIVE)/neurological complications of AIDS (neuroAIDS) models are generally associated with rapid progression to neuroAIDS, which does not reflect the tempo of neuroAIDS progression in humans. Recently, we isolated a neuropathogenic clone, SIVsm804E-CL757 (CL757), obtained from an SIV-infected rhesus macaque (RM). CL757 causes a more protracted progression to disease, inducing SIVE in 50% of inoculated animals, with high cerebral spinal fluid viral loads, multinucleated giant cells (MNGCs), and perivascular lymphocytic cuffing in the central nervous system (CNS). This latter finding is reminiscent of human immunodeficiency virus (HIV) encephalitis in humans but not generally observed in rapid progressor animals with neuroAIDS. Here, we studied which subsets of cells within the CNS were targeted by CL757 in animals with neurological symptoms of SIVE. Immunohistochemistry of brain sections demonstrated infiltration of CD4⁺ T cells (CD4) and macrophages (Ms) to the site of MNGCs. Moreover, an increase in mononuclear cells isolated from the brain tissues of RMs with SIVE correlated with increased cerebrospinal fluid (CSF) viral load. Subset analysis showed a specific increase in brain CD4⁺ memory T cells (Br-mCD4), brain-Ms (Br-Ms), and brain B cells (Br-B cells). Both Br-mCD4s and Br-Ms harbored replication-competent viral DNA, as demonstrated by virus isolation by coculture. However, only in animals exhibiting SIVE/neuroAIDS was virus isolated from Br-Ms. These findings support the use of CL757 to study the pathogenesis of AIDS viruses in the central nervous system and indicate a previously unanticipated role of CD4s cells as a potential reservoir in the brain.

IMPORTANCE While the use of combination antiretroviral therapy effectively suppresses systemic viral replication in the body, neurocognitive disorders as a result of HIV infection of the central nervous system (CNS) remain a clinical problem. Therefore, the use of nonhuman primate models is necessary to study mechanisms of neuropathogenesis. The neurotropic, molecular clone SIVsm804E-CL757 (CL757) results in neuroAIDS in 50% of infected rhesus macaques approximately 1 year postinfection. Using CL757-infected macaques, we investigate disease progression by examining subsets of cells within the CNS that were targeted by CL757 and could potentially serve as viral reservoirs. By isolating mononuclear cells from the brains of SIV-infected rhesus macaques with and without encephalitis, we show that immune cells invade the neuroparenchyma and increase in number in the CNS in animals with SIV-induced encephalitis (SIVE). Of these cells, both brain macrophages and brain memory CD4⁺ T cells harbor replication-competent SIV DNA; however, only brain CD4⁺ T cells harbored SIV DNA in animals without SIVE. These findings support use of CL757 as an important model to investigate disease progression in the CNS and as a model to study virus reservoirs in the CNS.

ABSTRACT

The profiling of gene expression by RNA sequencing (RNA-seq) has enabled powerful studies of global transcriptional patterns in all organisms, including bacteria. Because the vast majority of RNA in bacteria is rRNA, it is standard practice to deplete the rRNA from a total RNA sample such that the reads in an RNA-seq experiment derive predominantly from mRNA. One of the most commonly used commercial kits for rRNA depletion, the Ribo-Zero kit from Illumina, was recently discontinued abruptly and for an extended period of time. Here, we report the development of a simple, cost-effective, and robust method for depleting rRNA that can be easily implemented by any lab or facility. We first developed an algorithm for designing biotinylated oligonucleotides that will hybridize tightly and specifically to the 23S, 16S, and 5S rRNAs from any species of interest. Precipitation of these oligonucleotides bound to rRNA by magnetic streptavidin-coated beads then depletes rRNA from a complex, total RNA sample such that ~75 to 80% of reads in a typical RNA-seq experiment derive from mRNA. Importantly, we demonstrate a high correlation of RNA abundance or fold change measurements in RNA-seq experiments between our method and the Ribo-Zero kit. Complete details on the methodology are provided, including open-source software for designing oligonucleotides optimized for any bacterial species or community of interest.

IMPORTANCE The ability to examine global patterns of gene expression in microbes through RNA sequencing has fundamentally transformed microbiology. However, RNA-seq depends critically on the removal of rRNA from total RNA samples. Otherwise, rRNA would comprise upward of 90% of the reads in a typical RNA-seq experiment, limiting the reads coming from mRNA or requiring high total read depth. A commonly used kit for rRNA subtraction from Illumina was recently unavailable for an extended period of time, disrupting routine rRNA depletion. Here, we report the development of a "do-it-yourself" kit for rapid, cost-effective, and robust depletion of rRNA from total RNA. We present an algorithm for designing biotinylated oligonucleotides that will hybridize to the rRNAs from a target set of species. We then demonstrate that the designed oligonucleotides enable sufficient rRNA depletion to produce RNA-seq data with 75 to 80% of reads coming from mRNA. The methodology presented should enable RNA-seq studies on any species or metagenomic sample of interest.

Background

Chronic lung disease of prematurity (CLD), also called bronchopulmonary dysplasia, is a major consequence of preterm birth, but the role of the microbiome in its development remains unclear. Therefore, we assessed the progression of the bacterial community in ventilated preterm infants over time in the upper and lower airways, and assessed the gut–lung axis by comparing bacterial communities in the upper and lower airways with stool findings. Finally, we assessed whether the bacterial communities were associated with lung inflammation to suggest dysbiosis.

Simian-human immunodeficiency virus (SHIV) infection of rhesus monkeys is an important preclinical model for human immunodeficiency virus type 1 (HIV-1) vaccines, therapeutics, and cure strategies. SHIVs have been optimized by incorporating HIV-1 Env residue 375 mutations that mimic the bulky or hydrophobic residues typically found in simian immunodeficiency virus (SIV) Env to improve rhesus CD4 binding. We applied this strategy to three SHIV challenge stocks (SHIV-SF162p3, SHIV-AE16, and SHIV-325c) and observed three distinct outcomes. We constructed six Env375 variants (M, H, W, Y, F, and S) for each SHIV, and we performed a pool competition study in rhesus monkeys to define the optimal variant for each SHIV prior to generating large-scale challenge stocks. We identified SHIV-SF162p3S/wild type, SHIV-AE16W, and SHIV-325cH as the optimal variants. SHIV-SF162p3S could not be improved, as it already contained the optimal Env375 residue. SHIV-AE16W exhibited a similar replicative capacity to the parental SHIV-AE16 stock. In contrast, SHIV-325cH demonstrated a 2.6-log higher peak and 1.6-log higher setpoint viral loads than the parental SHIV-325c stock. These data demonstrate the diversity of potential outcomes following Env375 modification in SHIVs. Moreover, the clade C SHIV-325cH challenge stock may prove useful for evaluating prophylactic or therapeutic interventions against clade C HIV-1.

IMPORTANCE We sought to enhance the infectivity of three SHIV stocks by optimization of a key residue in human immunodeficiency virus type 1 (HIV-1) Env (Env375). We developed the following three new simian-human immunodeficiency virus (SHIV) stocks: SHIV-SF162p3S/wild type, SHIV-AE16W, and SHIV-325cH. SHIV-SF162p3S could not be optimized, SHIV-AE16W proved comparable to the parental virus, and SHIV-325cH demonstrated markedly enhanced replicative capacity compared with the parental virus.

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