IFTTT (If This Than That), a web-based software that automates and connects over 600 online services/software raised a $24M Series C led by Salesforce. Other investors include IBM and the Chamberlain Group and Fenox Venture Capital.

The latest round brings IFTTT’s funding to $63M and it will use the funding proceeds to provide integration for enterprise and IoT services and hiring. In IFTTT’s platform, applets are code/script users need to deploy to integrate two or more services (such Google Drive’s integration with Twitter/Facebook).

Investment in IFTTT reveals that Salesforce is consolidating its presence in enterprise IoT space. It also acquired Mulesoft, an integration platform that rivals Microsoft’s BizTalk.

IBM’s investment in IFTTT is also noteworthy as the former is pushing its IBM Watson IoT platform. The following statement also shows its keen interest in IFTTT.

Other recent investments in IoT companies include $30M Series B of Armis and Myriota's $15M for its IoT satellite-based connectivity platform.

For latest IoT funding and product news, please visit our IoT news section.

Owlet, a connected-baby care company raised a $24 million Series B investment from Trilogy Equity Partners, with participation from existing investors, including Eclipse Ventures, Broadway Angels, and Enfield Ventures, and the addition Pelion Venture Partners.

Owlet’s core product is a baby sock that contains a smart sensor. The sensor monitors pulse oximetry, a technology used in hospitals to measure an infant's heart rate and blood oxygen levels. The vital signs are communicated to parents’ smartphone via Bluetooth connection. The product retails for $299 and parents can also choose from monthly payment plans.

Other IoT-health startups using sensors to monitor vital signs include Aifloo, a company selling wrist-bands for elders and Air by Propeller, a smart health company that provides an API to predict local asthma conditions.

A complete product package of Owlet monitor includes three fabric socks, smart sock sensor, a base station (which rings an alarm if a baby’s vital signs are abnormal), and charging cords.

Before the company raised the latest round, it closed a $15 million Series B round in late 2016. The recent investment brought Owlet’s total equity funding to $46M. Owlet plans to use the growth capital to launch more baby care products.

Smart baby monitor company Nanit raised a $14M Series B round led by Jerusalem Venture Partners (JVP). Other investors that participated include existing investors Upfront Ventures, RRE Ventures, Vulcan Capital and Vaal Investment Partners. The latest investment brings total equity funding of Nanit to $30M.

Nanit announced it will use the funding proceeds to expand its team of computer vision and machine learning engineers and grow its sales in Europe and Canada.

Nanit’s baby monitor helps new parents oversee nursery conditions as it has built-in temperature and humidity sensors. The camera lets parents remotely monitor baby’s crib whereas sound and motion are detected via smart sensors.

The monitor’s insights can be accessed via an accompanying mobile app. Nanit charges $10 per month for its premium package.

The key use cases of Nanit’s baby monitoring technology include sleep insights, behavioral analysis, expert guidance, and nightly video summaries. The company currently sells its smart monitors via its website.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[allAfrica]

[allAfrica]

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

I am not able to open 64bit version of simvision using the following :

simvision -64 -wav "path to wav"

This throws the error "  /lib64/libc.so.6: version `GLIBC_2.14' not found"

I am only able to open it without the -64 option.

As a result I am not able to use the source browser feature since the simulation was run in 64 bit mode.

Need suggestion on how to resolve this. Thanks.

Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity. 

UFS is a simple and high-performance mass storage device with a serial interface. It is primarily used in mobile systems between host processing and mass storage memory devices. Another important reason for the usage of UFS in mobile systems like smartphones and tablets is minimum power consumption. 

To achieve the highest performance and most power-efficient data transport, JEDEC UFS works in collaboration with industry-leading specifications from the MIPI® Alliance to form its Interconnect Layer. MIPI UniPro is used as a transport layer, and MIPI MPHY is used as a physical layer with the serial DpDn interface. 

UFS 4.0 specification is the latest specification from JEDEC, which leverages UniPro 2.0 and MPHY 5.0 specification standards to achieve the following major improvements:

• Enables up to 4200 Mbps read/write traffic with MPHY 5.0, allowing 23.29 Gbps data rate. 
• High Speed Link Startup, along with Out of Order Data Transfer and BARRIER Command, were introduced to improve system latencies. 
• Data security is enhanced with Advanced RPMB. Advance RPMB also uses the EHS field of the header, which reduces the number of commands required compared to normal RPMB, increasing the bandwidth. 
• Enhanced Device Error History was introduced to ease system integration. 
• File Based Optimization (FBO) was introduced for performance enhancement. 

Along with many major enhancements, UFS 4.0 also maintains backward compatibility with UFS 3.0 and UFS 3.1. 

JEDEC has just announced the UFS 4.0 specification release, quoting Cadence support as a constant contributor in the JEDEC UFS Task Group, actively participating in these specifications development.  

With the availability of the Cadence Verification IP for JEDEC UFS 4.0, MIPI MPHY 5.0 and MIPI UniPro 2.0, early adopters can start working with the provisional specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure.  

More information on Cadence VIP is available at the Cadence VIP Website. 

Yeshavanth B N 

NAND Flash memory is now a widely accepted non-volatile memory in many application areas for data storage such as digital cameras, USB drive, SSD and smartphones. One form of NAND flash memory, Toggle NAND, was introduced to transmit high-speed data asynchronously thus consuming less power and increasing the density of the NAND flash device. 

The initial Toggle NAND versions had memory arranged in terms of SLC (Single Level Cell) or MLC (Multi Level Cell) mode that was considered as a 2D scalar stack and their frequency of operation was also less. The ever-growing demand of high memory capacity and high throughput required further research in the areas like the shrinking size of cell, performance to fill-in these gaps.

Some of these new requirements were incorporated, leading to newer versions of Toggle NAND, namely 3.0 and 4.0, with a re-arrangement of the internal memory developing a 3D layer of memory. With such structures, higher capacity of the memory was possible, but performance was the primary challenge as the latency of the write/read of memory quadrupled with the same frequency.

The key to improving the performance and run the device at very high speed in low power mode was to enhance the frequency of operation for faster read/writes to the memory and reduce the voltage levels.

But with every technology advancement comes some other problems, the next being the data sampling at that high frequency that can cause setup/hold time issues. To overcome these concerns, different types of trainings on the signal interface were made mandatory that shall assist in proper sampling of the data. Few other features for improving the integrity of the signals were added.

The current set of commands were applicable to access the SLC and MLC memory modes but with the 3D layering, these commands were lacking access to the entire set of TLC (Triple Level Cell) and QLC (Quad Level Cell) memory modes. Thus, more commands were required to make sure that the 3D layering was fully written/read.

Main features of Toggle NAND 4.0 :

• High Density of Memory
• High Frequency of operation, greater than 800 MHz
• Data Trainings

Cadence Verification IP for Flash Toggle NAND 4.0 is available to support the newer version of Flash Toggle NAND 4.0, allowing to simulate the memory device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 
 
Gaurav 

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt  products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3-compatible rates of 10.3125 Gbps (for Gen 2) and 20.625 Gbps (for Gen 3). It becomes very important to verify the Thunderbolt  backward compatibility with the designs. Though the support of USB4 Interoperability with Thunderbolt  3 (TBT3) is optional in USB4 host or USB4 peripheral device and required USB4 Hub and USB4 Based Dock but it is very essential to work in the existing ecosystem. 

Few Main features of USB4 Interoperability with Thunderbolt  3 (TBT3) Systems

• Support for Bi-Directional Pins & Retimers: TBT3 Active Cables can contain two bidirectional Re-timers which have the capability to send AT Responses on its RX channel. Router connected directly to such Retimer needs to support A Router that is connected directly to a bidirectional Re-timer shall support reception of Transactions on both TX and RX channels. 

• Bounce Mechanism: This feature is used by Router to access the Register Space of a Cable Re-timer that can only be accessed by its Link Partner.
• Asymmetric Negotiation: The Router which connects with Cable Retimers needs to follow Asymmetric TxFFE in Phase 5 of Lane Initialization. 
• USB4 Link Transitions: In TBT3 mode, the configuration of two independent Single Lane Links can be used non-transient state or Single Lane Link just using the Lane1 Adapter.

Cadence has a mature USB4 Verification IP solution that can help in the verification of USB4 designs with TBT3. Cadence has taken an active part in the Cairo group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members. If you plan to have a USB4-compatible design, you can reduce the risk of adopting new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team, for more details.

Explore Impacts of Finite Interconnect Impedance on PDN Characterization

Over the past few decades, many details have been worked out in the power distribution network (PDN) in the frequency and time domains. We have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior. We also have frequency- and time-domain test methods to measure the steady-state and transient behavior of the built-up systems.

All of these pieces in our current toolbox have their own assumptions, limitations, and artifacts, and they constantly raise the challenging question that designers need to answer: How to select the design process, simulation, measurement tools, and processes so that we get reasonable answers within a reasonable time frame with a reasonable budget.

Read this award-winning DesignCon 2024 paper titled “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.” Led by Samtec’s Istvan Novak and written with a team of nine authors from Cadence, Amazon, and Samtec, the paper discusses a series of continually evolving challenges with PDN requirements for cutting-edge designs.

Read the full paper now: “Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization.”

The OrCAD X and Allegro X 24.1 release is now available at Cadence Downloads. This blog post provides links to access the release and describes some major changes and new features.   OrCAD X /Allegro X 24.1 (SPB241) Here is a representative li...(read more)

The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those who want to use formal analysis for design or verification. 

To optimally benefit from this course, you must already have sufficient knowledge of the System Verilog assertions to be capable of writing properties for formal verification. Hence, this training provides a module on formal analysis to help cover this essential background. 

In this course, you will learn how to code efficient SVA Properties for formal analysis, understand formal complexity and how to overcome it, and learn the basics of formal coverage.

After completing this course, you will be able to:

• Define reusable, functionally correct SVA properties that are efficient for formal tools. These shall use abstract auxiliary code to simplify descriptions, make code maintenance easier, reduce debug time, and reduce tool-proof runtime.
• Set up, run, and analyze results from formal analysis.
• Identify designs upon which formal is likely to be successful while understanding formal complexity issues and how to identify and overcome them.
• Use a systematic property development process to approach a completely new verification problem.
• Understand the basics of formal coverage.

 The most recently updated release includes new modules on:

• "Basic complexity handling" which discusses the complexity in formal and how to identify and handle them.
• "Complexity reduction methods” which discusses the complexity reduction methods and which is suitable for which type of complexity problem.
• “Coverage in formal” which discusses the basics of coverage in formal verification and how coverage can be used in formal.   

Take this course to learn the basics of formal verification. 

What's Next? 

You can check out the complete training: Jasper Formal Fundamentals. There is a free online version of the training available 24/7 for all customers with a Cadence Learning and Support Portal account. If you are interested in an instructor-led version of the training, please contact Cadence Training. And don't forget to obtain your digital badge after completing the training!

You can also check Jasper University page for more materials on formal analysis and Jasper apps. 

Related Trainings 

Jasper Formal Expert Training Course | Cadence

Verilog Language and Application Training Course | Cadence

SystemVerilog for Design and Verification Training Course | Cadence

SystemVerilog Assertions Training Course | Cadence

Related Training Bytes 

Jasper Formal Property Verification (FPV) App: Basic Usage Demo (Video)

Jasper Formal Methodology playlist

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The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1 release is now available for download at Cadence Downloads . For the list of CCRs fixed in this release, see the README.txt file in the installation hierarchy. SIGRITY/SYSANLS 2024.1 Here is a list of some of the key updates in the SIGRITY/SYSANLS 2024.1 release: For more details about these and all the other new and enhanced features introduced in this release , refer to the following document: Sigrity Release Overview and Common Tools What's New . Supported Platforms and Operating Systems Platform and Architecture X86_64 (lnx86) Windows (64 bit) Development OS RHEL 8.4 Windows Server 2022 Supported OS RHEL 8.4 and above RHEL 9 SLES 15 (SP3 and above) Windows 10 Windows 11 Windows Server 2019 Windows Server 2022 Systems Analysis 2024.1 Clarity 3D Solver Clarity 3D Layout Structure Optimization Workflow : A new workflow, Clarity 3D Layout Structure Optimization Workflow, has been added to Clarity 3D Layout. This workflow integrates Allegro PCB Designer with Clarity 3D Layout for high-speed structure optimization. Component Geometry Model Editor : The new Clarity 3D Layout editor lets you set up ports, solder bumps/balls/extrusions, and two-terminal and multi-terminal circuits using a single GUI. Coaxial Open Port Option Added to Port Setup Wizard : The Coaxial Open Port option lets you create ports for each target net pin and reference net pin in Clarity 3D Layout. The nearby reference net pins are then used as a reference for each target net pin, reducing the number of ports needed. In addition, the ports of unused reference net pins are shorted to the ground. Parametric Import Option Added : Two new options, Parametric Import and Default Import , have been added to the Tools – Launch Clarity3DWorkbench menu. The Parametric Import option lets you import the design along with its parameters into Clarity 3D Workbench. The Default Import option lets you ignore the parameters when importing the design into Clarity 3D Workbench. Component Library Added to Generate 3D Components : Clarity 3D Workbench now includes a new component library that lets you use predefined 3D component templates or add existing 3D components to create 3D designs and simulation models. AI-Powered Content Search Capability : Clarity 3D Workbench and Clarity 3D Transient Solver now support an AI-powered capability for searching the content and displaying relevant information. Expression Parser to Handle Undefined Parameters : Clarity 3D Workbench and Clarity 3D Transient Solver support writing expressions or equations containing undefined parameters in the Property window to describe a simulation variable. The improved expression parser automatically detects any undefined parameter in an expression and prompts users to specify their values. This capability lets you define a model or a simulation variable as a function instead of specifying static values. For detailed information, refer to Clarity 3D Layout User Guide and Clarity 3D Workbench User Guide on the Cadence Support portal. Clarity 3D Transient Solver Mesh Processing Improved to Simulate Large Use Cases : Clarity 3D Transient Solver leverages a new meshing algorithm that enhances overall mesh processing, specifically for large designs and use cases. The new algorithm dramatically improves the mesh quality, minimum mesh size, number of mesh key points, total mesh number, and memory usage. Advanced Material Processing Engine : The material processing capability has been enhanced to handle thin outer metal, which previously resulted in open and short issues in some designs. In addition, the material processing engine offers improved mode extraction for particular use cases, including waveguide and coaxial designs. Characteristic Impedance Calculation Improved : The solver engine now uses a new analytical calculation method to calculate the characteristic impedance of coaxial designs with improved accuracy. For detailed information, refer to Clarity 3D Transient Solver User Guide on the Cadence Support portal. Celsius Studio Celsius Interchange Model Introduced : Celsius Studio now supports Celsius Interchange Model generation, which is a 3D model derived from detailed physical designs for multi-physics and multi-scale analysis. This Celsius Interchange Model file ( .cim ) serves as a design information carrier across Celsius Studio tools, enabling a variety of simulation and analysis tasks . Celsius 3DIC Thermal Workflow Improvements : The Thermal Simulation workflows in Celsius 3DIC have been significantly enhanced. Key improvements include: Advanced Power Setup with Transient Power Function and Multi Mode options Enhanced GUI for the Mesh Control and Simulation Control tabs Improved meshing capabilities Celsius Interchange Model ( .cim ) generation Material library support for block and connections Import of Heat Transfer Coefficients (HTCs) from a CFD file Bump creation through the Bump Array Wizard Layer Stackup CSV file generation Celsius 3DIC Warpage and Stress Workflow Enhancements : The Warpage and Stress workflow in Celsius 3DIC has undergone significant improvements, such as: Improved multi-stage warpage simulation flow for 3DIC packaging process Enhanced GUI for the Mesh Control , Simulation Control , and Stress Boundary Conditions tabs Support for large deformations and temperature profiles Bump creation through the Bump Array Wizard New constraint types Enhanced meshing capabilities Geometric Nonlinearity Support in Warpage and Stress Analysis : Large deformation analysis is now supported in warpage and stress studies. This study uses the Total Lagrangian approach to model geometric nonlinearities in simulation, which allows accurate prediction of final deformations. Thermal Network Extraction and Simulation : In the solid extraction flow in Celsius 3D Workbench, you can now import area-based power map files to create terminals. For designs with multiple blocks, this capability allows automatic terminal creation, eliminating the need to manually create and set up 2D sheets individually. Additionally, thermal throttling feature is now supported in Celsius Thermal Network. This makes it ideal for preliminary analyses or when a quick estimation is required. It runs significantly faster than 3D models, allowing for quicker iterations and more efficient decision-making. For detailed information, refer to the Celsius 3DIC User Guide , Celsius Layout User Guide and Celsius 3D Workbench User Guide on the Cadence Support portal. Sigrity 2024.1 Layout Workbench Improved Graphical User Interface : A new option, Use Improved User Interface , has been added in the Themes page of the Options dialog box in the Layout Workbench GUI. In the new GUI, the toolbar icons and menu options have been enhanced and rearranged. For detailed information, refer to Layout Workbench User Guide on the Cadence Support portal. Broadband SPICE Python Script Integration with Command Line for Simulation Tasks : Broadband SPICE lets you run Python scripts directly from the command line for performing simulation and analysis. The new -py and *.py options make it easier to integrate Python scripts with the command-line operations. This update streamlines the process of automating and customizing simulations from the command line, which makes your simulation tasks faster and easier. For detailed information, refer to Broadband SPICE User Guide on the Cadence Support portal. Celsius PowerDC Block Power Assignment (BPA) File Format Support : PowerDC now supports the BPA file format. Similar to the Pin Location (PLOC) file, the BPA file is a current assignment file that defines the total current of a power grid cell, which is then equally distributed across the power pins within the cell. This provides better control over the power distribution. Ability to Run Multiple IR Drop Cases Sequentially : You can now select multiple result sinks from the Current-Limited IR Drop flow and run IR Drop analysis for them sequentially. PowerDC automatically runs the simulations in sequence after you select multiple result sinks. This saves time by automating the process. Enhanced Support for Mixed Conversion Devices : PowerDC now supports mixing different conversion devices, such as switching regulators and linear regulators within a single DC-DC/LDO instance. This enhancement offers added flexibility by letting you configure each instance in your design according to your specific needs. For detailed information, refer to PowerDC User Guide on the Cadence Support portal. PowerSI Monte Carlo Method Added : A new option, Monte Carlo Method, has been added in the Optimality dialog box. This option lets you create multiple random samples to depict variations in the input parameters and assess the output. Channel Check Optimization Added : The S-Parameter Assessment workflow in PowerSI now supports Channel Check Optimization . It uses the AI-driven Multidisciplinary Analysis and Optimization (MDAO) technology that lets you optimize your design quickly and efficiently with no accuracy loss. For detailed information, refer to PowerSI User Guide on the Cadence Support portal. SPEEDEM Multi-threaded Matrix Solver Support Added : The Enable Multi-threaded Matrix Solver check box has been added that lets you accelerate the simulation speed for high-performance computing. This check box provides two options, Automatic and Always, to include the -lhpc4 or -lhpc5 parameter, respectively, in the SPEEDEM Simulator (SPDSIM) before running the simulation. For detailed information, refer to the SPEEDEM User Guide on the Cadence Support portal. XtractIM Options to Skip or Calculate Special DC-R Simulation Results : The Skip DC_R of Each Path and Only DC_R of Each Path options have been added to the Setup menu. Skip DC_R of Each Path : This option lets you skip the calculation of the DC-R result during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are still calculated. Only DC_R of Each Path : This option lets you calculate the DC-R result only during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are not calculated. Color Assignment for Pin Matching : The MCP Auto Connection window includes the Display Color Editor , which lets you assign a color for pin matching. It helps you easily identify the matching pins in the left and right sections of the MCP Auto Connection window . Ability to Save Simulations Individually : The Save each simulation individually check box has been added to the Tools - Options - Edit Options - Simulation (Basic) - General form. Select this check box and run the simulation to generate a simulation results folder containing files and logs with a timestamp for each simulation. Reuse of SPD File Settings : The XtractIM setup check box lets you import an existing package setup to reuse the configurations and settings from one .spd file to another. For detailed information, refer to XtractIM User Guide on the Cadence Support portal. Documentation Enhancements Cloud-Based Help System Upgraded The cloud-based help system, Doc Assistant, has been upgraded to version 24.10, which contains several new features and enhancements over the previous 2.03 version. Sigrity Release Team Please send your questions and feedback to sigrity_rmt@cadence.com .

This November, the engineering and simulation community is set to converge in China for an event that promises to be nothing short of revolutionary. The 2024 BETA CAE Systems China Open Meeting, taking place in the vibrant cities of Beijing and Shanghai on November 5 and 7 , respectively, is a must-attend for anyone looking to stay at the forefront of technological innovation in simulation solutions. Prepare to be inspired by Ben Gu , the visionary Corporate VP of Research and Development at Cadence. He will lead both meetings in Beijing and Shanghai with his keynote on " A New Millennium in Multiphysics System Analysis ." This thought-provoking keynote is expected to provide attendees with a glimpse into the future of engineering simulation and analysis. What sets the BETA CAE Systems Open Meetings apart is not just the high caliber of speakers but also the hands-on training sessions designed to enhance your technical expertise with the BETA CAE software suite. Whether you are an inexperienced individual seeking to acquire fundamental knowledge or an accomplished professional endeavoring to hone your expertise, these training sessions following the open meetings are meticulously tailored to meet your needs. Join Us at the BETA CAE Systems Open Meeting in Beijing The BETA CAE Systems Open Meeting in Beijing will feature a keynote speech by Peng Qiao , Senior Engineer at Great Wall Motors Co., Ltd, on Multidisciplinary Optimization Techniques for Automotive Control Arms . ( View detailed agenda for Beijing. ) When: November 5, 2024 Where: Grand Metropark Hotel Beijing If this sounds interesting, register today for the BETA CAE Systems Beijing Open Meeting by clicking the button below. Don't Miss Out on the BETA CAE Systems Open Meeting in Shanghai After the BETA CAE Systems Open Meeting in Beijing, the next meeting in China will be in Shanghai. During this event, Liu Deping, CAE Engineer from Zhejiang Geely Automobile Research Institute Co., Ltd, will deliver a keynote speech on the Application of ANSA in the Simulation Development Cycle . ( View detailed agenda for Shanghai. ) When: November 7, 2024 Where: InterContinental Shanghai Jing'an Following the open meeting on November 7 will be an exclusive training day on November 8. This session will provide attendees with practical experience using the BETA CAE software to improve their technical skills and provide hands-on knowledge of the software. If you find this intriguing, register now for the BETA CAE Systems Shanghai Open Meeting by clicking the button below. Why Attend? Gain firsthand insights into the latest developments in simulation technology Learn from real-world applications and success stories from various industries Connect and exchange ideas with experts in a collaborative environment Mark your calendars for this unparalleled opportunity to explore the forefront of simulation technology. Whether you're aiming to broaden your knowledge, enhance your technical skills, or connect with industry leaders, the BETA CAE Systems Open Meetings are your gateway to the future of engineering. Join us and be part of shaping the next wave of innovation in the simulation world.

The demand for higher compute performance, energy efficiency, and faster time-to-market drove the conversations at this year's Open Compute Project (OCP) Global Summit in San Jose, California. It was the scene of showcasing groundbreaking innovations, expert-led sessions, and networking opportunities to drive the future of data center technology. For those who didn't get to attend or stop by our booth, here's a recap of Cadence's comprehensive solutions that enable next-generation compute technology, AI data center design, analysis, and optimization. Optimized Data Center Design and Operations As the data center community increasingly faces demands for enhanced efficiency, thermal management, sustainability, and performance optimization, data center operators, IT managers, and executives are looking for solutions to these challenges. At the Cadence booth, attendees explored the Cadence Reality Digital Twin Platform and Celsius EC Solver. These technologies are pivotal in achieving high-performance standards for AI data centers, providing advanced digital twin modeling capabilities that redefine next-generation data center design and operation. The Celsius EC Solver demonstration showed how it solves challenging thermal and electronics cooling management problems with precision and speed. CadenceCONNECT: Take the Heat Out of Your AI Data Center Cadence hosted a networking reception on October 16 titled "Take the Heat Out of Your AI Data Center." In today's AI era, managing the heat generated by high-density computing environments is more critical than ever. This reception offered insights into current and emerging data center technologies, digital twin cooling strategies that deliver energy-saving operations, and a chance to engage with industry leaders, Cadence experts, and peers to explore the latest cooling, AI, and GPU acceleration advancements. Here's a recap: Researcher, author, and entrepreneur Dr. Jon Koomey highlighted the inefficiency of data centers in his talk "The Rise of Zombie Data Centers," noting that 20-30% of their capacity is stranded and unused. He advocated for organizational changes and technological solutions like digital twins to reduce wasted energy and improve computational effectiveness as AI deployments increase. In "A New Millennium in Multiphysics System Analysis," Cadence Corporate VP Ben Gu explained the company's significant strides in multiphysics system analysis, evolving from chip simulation to a broader application of computational software for simulating various physical systems, including entire data centers. He noted that the latest Cadence venture, a digital twin platform for data center optimization, opened the opportunity to use simulation technology to optimize the efficiency of data centers. Senior Software Engineering Group Director Albert Zeng highlighted the Cadence Reality DC suite's ability to transform data center operations through simulation, emphasizing its multi-phase engine for optimal thermal performance and the integration of AI capabilities for enhanced design and management. A panel discussion titled "Turning AI Factory Blueprints into Reality at the Speed of Light" featured industry experts from NVIDIA, Norman Wright Precision Environmental and Power, NV5, Switch Data Centers, and Cadence, who explored the evolving requirements and multidimensional challenges of AI factories, emphasizing the need for collaboration across the supply chain to achieve high-performing and sustainable data centers. Watch the highlights. Transforming Designs from Chips to Data Centers The OCP Global Summit 2024 has reaffirmed its status as a pivotal event for data center professionals seeking to stay at the forefront of technological advancements. Cadence's contributions, from groundbreaking digital twin technologies to innovative cooling strategies, have shed light on the path forward for efficient, sustainable data centers. For data center professionals, IT managers, and engineers, the insights gained at this summit are invaluable in navigating the challenges and opportunities presented by the burgeoning AI era. Partnering with Arm Arm Total Design Cadence is a member of the Arm Total Design program. At an invitation-only special Arm event, Cadence's VP of Research and Development, Lokesh Korlipara, delivered a presentation focusing on data center challenges and design solutions with Arm Neoverse Compute Subsystem (CSS). The session highlighted: Efficient integration of Arm Neoverse CSS into system on chips (SoCs) with pre-integrated connectivity IP Performance analysis and verification of the Neoverse CSS integration into the SoC through Cadence's System VIP verification suite and automated testbench creation, enhancing both quality and productivity Jumpstarting designs through Cadence's collaboration with Arm for 3D-IC system planning, chiplets, and interposers Design Services readiness and global scale to support and/or deliver the most demanding Arm Neoverse CSS-based SoC design projects Cadence Supports Arm CSS in Arm Booth During the event, Cadence conducted a demo in the Arm booth that showcased the Cadence System VIP verification suite. The demo highlighted automated testbench creation and performance analysis for integrating the Arm CSS into SoCs while enhancing verification quality and productivity. Summary Cadence offers data center solutions for designing everything from the compute and networking chips to the board, racks, data centers, and campuses. Stay connected with Cadence and other industry leaders to continue exploring the innovations set to redefine the future of data centers. Learn More Cadence Joins Arm Total Design Cadence Arm-Based Solutions Cadence Reality Digital Twin Platform

Hello~

As the following circuit shows, VCC+5V_USB is the 4^th power source, connecting the output of power management of diode.There are 3 5V input in the input port of LTC4417.

It’s normal when VCC+5V_USB prodive power with other circuit. However, if I cup VCC+5V_FIRST,VCC+5V_SECOND,VCC+5V_THIRD, 5V voltage will occurred in the VCC+5V_FIRST,VCC+5V_SECOND,VCC+5V_THIRD.

The LTC4417 PDF

Is this phenomance normal ?

Please kindly give me some advice ! Thanks.

Hi ,

  FIrst of all , I hope I have posted my query in the right place . I am expecting software support/suggestions for the below issue.

   I am working on LTE which use USB interface and the Host Controller is USB 2.0 . The BSP is from NXP which supports Cadence USB 3.0 Host controller and with USB 3.0 supported cadence driver.NXP had used the   USB 3.0 host controller for USB type C based device.

  Cadence USB 3.0 based device driver seems to be backward compatible for USB 2.0 host controller .Since basic LTE functionalities seems to be working fine I continued to use the same driver in Linux 4.14.62 

  But I am facing a kernel warning of unhandled interrupt and the crash log points to cdns_irq function as shown below  The crash/kerenel warning is very random and not occuring all the time.

.691533] irq 36: nobody cared (try booting with the "irqpoll" option)

[ 1.698242] CPU: 0 PID: 87 Comm: kworker/0:1 Not tainted 4.9.88 #24

[ 1.704509] Hardware name: Freescale i.MX8QXP MEK (DT)

[ 1.709659] Workqueue: pm pm_runtime_work

[ 1.713675] Call trace:

[ 1.716123] [<ffff0000080897d0>] dump_backtrace+0x0/0x1b0

[ 1.721523] [<ffff000008089994>] show_stack+0x14/0x20

[ 1.726582] [<ffff0000083daff0>] dump_stack+0x94/0xb4

[ 1.731638] [<ffff00000810f064>] __report_bad_irq+0x34/0xf0

[ 1.737212] [<ffff00000810f4ec>] note_interrupt+0x2e4/0x330

[ 1.742790] [<ffff00000810c594>] handle_irq_event_percpu+0x44/0x58

[ 1.748974] [<ffff00000810c5f0>] handle_irq_event+0x48/0x78

[ 1.754553] [<ffff0000081100a8>] handle_fasteoi_irq+0xc0/0x1b0

[ 1.760390] [<ffff00000810b584>] generic_handle_irq+0x24/0x38

[ 1.766141] [<ffff00000810bbe4>] __handle_domain_irq+0x5c/0xb8

[ 1.771979] [<ffff000008081798>] gic_handle_irq+0x70/0x15c

1.807416] 7a40: 00000000000002ba ffff80002645bf00 00000000fa83b2da 0000000001fe116e

[ 1.815252] 7a60: ffff000088bf7c47 ffffffffffffffff 00000000000003f8 ffff0000085c47b8

[ 1.823088] 7a80: 0000000000000010 ffff800026484600 0000000000000001 ffff8000266e9718

[ 1.830925] 7aa0: ffff00000b8b0008 ffff800026784280 ffff00000b8b000c ffff00000b8d8018

[ 1.838760] 7ac0: 0000000000000001 ffff000008b76000 0000000000000000 ffff800026497b20

[ 1.846596] 7ae0: ffff00000810bd24 ffff800026497b20 ffff000008851d18 0000000000000145

[ 1.854433] 7b00: ffff000008b8d6c0 ffff0000081102d8 ffffffffffffffff ffff00000810dda8

[ 1.862268] [<ffff000008082eec>] el1_irq+0xac/0x120

[ 1.867155] [<ffff000008851d18>] _raw_spin_unlock_irqrestore+0x18/0x48

[ 1.873684] [<ffff00000810bd24>] __irq_put_desc_unlock+0x1c/0x48

[ 1.879695] [<ffff00000810de10>] enable_irq+0x48/0x70

[ 1.884756] [<ffff0000085ba8f8>] cdns3_enter_suspend+0x1f0/0x440

[ 1.890764] [<ffff0000085baca0>] cdns3_runtime_suspend+0x48/0x88

[ 1.896776] [<ffff0000084cf398>] pm_generic_runtime_suspend+0x28/0x40

[ 1.903223] [<ffff0000084dc3e8>] genpd_runtime_suspend+0x88/0x1d8

[ 1.909320] [<ffff0000084d0e08>] __rpm_callback+0x70/0x98

[ 1.914724] [<ffff0000084d0e50>] rpm_callback+0x20/0x88

[ 1.919954] [<ffff0000084d1b2c>] rpm_suspend+0xf4/0x4c8

[ 1.925184] [<ffff0000084d20fc>] rpm_idle+0x124/0x168

[ 1.930240] [<ffff0000084d26c0>] pm_runtime_work+0xa0/0xb8

[ 1.935732] [<ffff0000080dc1dc>] process_one_work+0x1dc/0x380

[ 1.941481] [<ffff0000080dc3c8>] worker_thread+0x48/0x4d0

[ 1.946885] [<ffff0000080e2408>] kthread+0xf8/0x100
[ 1.957080] handlers:

[ 1.959350] [<ffff0000085ba668>] cdns3_irq

[ 1.963449] Disabling IRQ #36

 Kindly provide a solution to solve this issue.

Thanks & Regards,

Anjali

The SPECTRE 24.1 release is now available for download at Cadence Downloads. For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy.(read more)

1， Some components in the installation package cannot choose to install; even if they do not choose them, they will still be installed; just less shortcut icons, the documents are still released to the installation directory.

2， "Catia Application Frame" repeat the problem?
       “x:CadenceSPB_17.4 oolsin“
       ”x:CadenceSPB_17.4 oolsspatial“
       "Catia Application Frame" shouldn't you use the latest version?

3，Follow-up update patch cleaning the useless files and extra empty folder action !!!

The SPB17.4 installation package is currently the worst installation package I have seen for large-scale software packaging.

As the title suggests I am unable to perform design sync between OrCAD Capture and Allegro. When I add a layout and try to sync to it I am given ERROR(ORCAP-2426): Cannot run Design Sync because of errors. See session log for error details.

Session Log

[ORPCBFLOW] : Invoking ECO dialog.
INFO(ORNET-1176): Netlisting the design
INFO(ORNET-1178): Design Name:
C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN
Netlist Directory:
c:usersddoyledocumentscadenceoards emote power devicelayoutallegro
Configuration File:
C:CadenceSPB_17.4 ools/capture/allegro.cfg
pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
Spawning... pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
{ Using PSTWRITER 17.4.0 d001Dec-14-2021 at 09:00:49 }

INFO(ORCAP-36080): Scanning netlist files ...

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstchip.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstchip.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstxprt.dat

Loading... c:usersddoyledocumentscadenceoards emote power devicelayoutallegropstxnet.dat
packaging the design view...
Exiting... pstswp.exe - pst - d "C:USERSDDOYLEDOCUMENTSCADENCEBOARDSREMOTE POWER DEVICECAPTUREREMOTE_POWER_DEVICE.DSN"- n "c:usersddoyledocumentscadenceoards emote power devicelayoutallegro" - c "C:CadenceSPB_17.4 ools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
INFO(ORNET-1179): *** Done ***

This issue started to occur after I changed parts that exist on previously created PCBs. I changed the following leading up to this:

1. Added height in Allegro to many of my components using the Setup->Area->Package Height tool.

2. Changed the reference designator category in OrCAD Capture to TP for several components on board.

Any advice here would be most welcome. Thanks!

Hello. I am using Cadence 17.4 tools. When I open a package symbol (.dra) or board file (.brd) in Allegro that was created in an older version of the tool I get a message like this one (as expected):

"The design created using release 17.2 will be updated for compatibility with the current software..."

If I create a symbol or board file from scratch in the 17.4 tool then open it later, I get the same message. (always referring to version 17.2 which is the previous version I was using here).

So far this has not caused me any problems, but I would like to understand why it is doing this in case I have something setup incorrectly.

I only have version 17.4 installed. I am not exporting to a downrev version when I save (i.e. not using File->Export->Downrev design…) and in User Preferences->Drawing I don’t have anything selected for database_compatibility_mode. What else might I check?

FYI here is the tool version information that I see after selecting Help->About Symbol:

OrCAD PCB Designer Standard 17.4-2019 S012 [10/26/2020] Windows SPB 64-bit Edition

Thanks -Jason

Hello All,

I'm a novice to this forum and probably this subject has been already discussed here.

My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.

However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.

Does anybody have opinion on this issue?

Many thanks,

Pavel

hello,

We have a number of workstations with version 17.2 that work on a floating license server

We want to know if it can be upgraded to version 17.4

If so, should the floating license server be upgraded as well?

In addition, how can you know where the license was purchased from?

Thanks!

Hi,

I found that under the Dark Theme of PCB Environment Editor 17.4,

the window background is not all dark, resulting in unclear text display。

As shown in the figure below：

I decided it was time to update my spectre install (currently a version of Spectre211).  Since 241 was a larger number than 211 I thought it would be a good idea (LOL)

Anyway, the simulator failed to run, and since I didn't have the time to debug why, I reverted to 211.

What's the difference in the two?

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

Sample clues

14 across: FDR’s baby (3,4)

1 down: A glitch in the Matrix? (4,2)

4 down: Slanted character (6)

5 down: New Year’s venue in New York (5,6)

16 down: Atmosphere of melancholy (5)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
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Sample clues

6 across: Alejandro González Iñárritu’s breakthrough film (6,6)

19 across: Soft leather shoe (8)

7 down: Randroids, for example (12)

12 down: First American World Chess Champion (7)

17 down: Circle of influence (5)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Hai Community,

What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24.

Can I get the grid matrix difference between these two tools?

Regards,

Rohit Rohan

Has anyone experienced the same situation?

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