Read the in depth Review of TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router Networking. Know detailed info about TP-Link Archer AXE95 AXE7800 Tri-Band Wi-Fi 6E Router configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

I am gratified to see the continuing adoption of Forecast Value Added by organizations worldwide. FVA is an easy to understand and easy to apply approach for identifying bad practices in your forecasting process. And I'm particularly gratified to see coverage of FVA in two new books, which the authors [...]

The post Vandeput's Data Science for Supply Chain Forecasting (book excerpt) appeared first on The Business Forecasting Deal.

In SAS, the INPUT and PUT functions are powerful functions that enable you to convert data from character type to numeric type and vice versa. They work by applying SAS formats or informats to data. You cannot fully understand the INPUT and PUT functions without understanding formats and informats in [...]

The post Understand the PUT and INPUT functions in SAS appeared first on The DO Loop.

The INPUT function and PUT function in SAS are used to apply informats and formats (respectively) to data. For both functions, you must know in advance which informat or format you want to apply. For brevity, let's consider only applying a format. To use the PUT function, you must know [...]

The post Run-time variations of the INPUT and PUT functions in SAS appeared first on The DO Loop.

In SAS, range attribute maps enable you to specify the range of values that determine the colors used for graphical elements. There are various examples that use the GTL to define a range attribute map, but fewer examples that show how to use a range attribute map with PROC SGPLOT. [...]

The post Automate the creation of a range attribute map in SAS appeared first on The DO Loop.

Ready to turn big data into big business insights? Look to the cloud.

The post Why it's hard to say "big data" without saying "cloud" appeared first on The Data Roundtable.

The evolution of service is simplicity and clarity. Build for the digital future of service today.

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A man has been arrested here in connection with the murder of a 50-year-old beautician in Rajasthan's Jodhpur whose body was chopped and buried in a pit by the accused, an official has said.

One person was killed and two others were injured when three men on a motorcycle opened fire on three friends returning home on a scooter last night in the Kabir Nagar area of North East Delhi.

The explosion occurred in Telangana Spice Kitchen on Road Number One Jubilee Hills. According to police, the explosion damaged the boundary wall of the hotel.

BJP MP from South Delhi Ramvir Singh Bidhuri on Tuesday inaugurated a newly constructed stretch of a 12-lane national highway connecting Mithapur Chowk to the Mumbai-Baroda highway in the Badarpur area.

On February 4, 2019, gloom settled over the iconic Brigade Parade grounds in the heart of Kolkata. Kanhaiya Kumar, then a firebrand Left leader known for his rousing speeches, had cancelled his visit to a rally just before the Lok Sabha election

Abdul Ghafoor Noorani, eminent constitutional expert, lawyer and author, died today at the age of 93. A noted scholar on Jammu and Kashmir, his absence is being felt in the Union Territory, where many are mourning him.

The CPIM lost one of its pillars today as Sitaram Yechury, the party's three-time general secretary, strategist, think tank, author and editor of its mouthpiece People's Democracy, died at the age of 72.

Ratan Tata, born on December 28, 1937, is the Chairman of Ratan Tata Trust, two of the largest private-sector-promoted philanthropic trusts in India.

Kamala Devi Harris was born on October 20, 1964, in Oakland, California, to immigrant parents.

1. 9 Surprising Facts About Voyager 2’s Uranus Flyby  Moneycontrol
2. Potential For Life Found On Uranus' Moons, Scientists Reveal  NDTV
3. The anomalous state of Uranus’s magnetosphere during the Voyager 2 flyby  Nature.com
4. Voyager-2 visited Uranus in 1986. Something more happened when it arrived  India Today
5. Uranus and its moons may have ideal conditions for life—but Voyager 2 missed it due to one bad day  The Economic Times

1. South Africa vs India Match Prediction - Who will win today’s 3rd T20I match between SA vs IND?  CricTracker
2. SA look to break spin stranglehold while India worry about depth  ESPNcricinfo
3. South Africa vs India 3rd T20 Playing 11, live match time (IST), streaming  Business Standard
4. Time running out for Abhishek, Avesh as Ramandeep-Vyshak waiting in wings: India vs South Africa 3rd T20I Probable XIs  Hindustan Times
5. India, SA eye series lead in Centurion before decisive T20I in Johannesburg  Cricbuzz

1. Ricky Ponting hits back at Gautam Gambhir, calls him 'prickly character'  The Times of India
2. Ricky Ponting Fires Back At Gautam Gambhir After India Coach's Press Conference Remarks  NDTV Sports
3. A fired-up Virat Kohli is Australia's worry after Ricky Ponting's 'bad move'  The Times of India
4. Gambhir a prickly character, never took dig at Kohli: Ponting  The Hindu
5. Border-Gavaskar Trophy: Why Gautam Gambhir comes across as abrasive at times  The Indian Express

1. Garena Free Fire MAX redeem codes for November 13, 2024: Win bundles, new outfits, and more rewards...  Moneycontrol
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3. Garena Free Fire MAX redeem codes for November 13: Win free in-game rewards daily  The Times of India
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5. Garena Free Fire MAX November 13 redeem codes: All about Booyah Top-Up event  HT Tech

1. Inflation in nearly half of major states outgrows India's Oct CPI; price pressure steepest in Chhattisgarh  Moneycontrol
2. Retail inflation surges to a 14-month high of 6.2% in October  The Times of India
3. If we exclude vegetable prices, CPI inflation remains in RBI's range: UBI research  The Economic Times
4. Rising food prices are likely to push back beginning of rate cutting cycle  The Indian Express
5. India confident of reaching USD 100 billion trade volume with Russia ahead of 2030 timeline: S Jaishankar  Telegraph India

1. Delhi: India's capital chokes as air pollution turns 'severe'  BBC.com
2. Several flights diverted due to low visibility conditions at Delhi airport  The Times of India
3. Delhi's toxic air: Why you should not take your cough lightly  India Today
4. Delhi air pollution: Visibility near-zero amid thick smog; CPCB says AQI 'very poor', IQAir shows 'hazardous' | Details  Hindustan Times
5. Delhi's IGI airport sees flight diversions as season's first dense fog hits national capital  Moneycontrol

If you’re in the market for a new Android tablet, check out these early Black Friday deals for the Samsung Galaxy Tab S10 series.

The post Check out these Samsung Galaxy Tab S10 early Black Friday deals and SAVE BIG! appeared first on Phandroid.

The iPad Mini 7 is an impressive tablet, but there are some compromises that might be a deterrent for potential buyers.

The post iPad Mini (2024) Review: Imperfect, but Impressive appeared first on Phandroid.

Valve says that customers are limited to one purchase per account.

The post You can Soon Get the Steam Deck OLED in White, but You’d Better Hurry appeared first on Phandroid.

In this clip, Steve Jobs pauses for 18 seconds to contemplate a question deeply before answering.

The offer is valid across the US. Some of its international locations - the chain operates in 40 countries - also have World Kindness Day promotions planned.

Amber Solutions, an IoT product company that sells smart outlets, switches and circuit breakers closed Series A Preferred Stock round of financing that equals $3.3M in gross proceeds. Amber will use the funds to support the commercial development of Amber's core technologies.

One of Amber’s product is solid-state circuit interrupter (GFCI) that basically stops harmful levels of electricity from passing through a person. It operates as a safety device alerting the homeowner of electrocution incidents in real time.

Amber Solutions’ core markets are builders that prepare smart home/smart building ready infrastructure, certified electrical contractors or remodelers, and electrical manufacturers.

Other latest funding news include Owlet’s $24M Series B, Axonize’s $6M Series A round and addition of Deutsche Telekom as its strategic investor, and $30M Series B raised by Palo Alto-based Armis.

[The Conversation Africa] South Africa's finance minister, Enoch Godongwana, announced in his October mid-term budget policy statement that cabinet had approved funding for an early retirement programme to reduce the public sector wage bill. R11 billion (about US$627 million) will be allocated over the next two years to pay for the exit costs of 30,000 civil servants while retaining critical skills and promoting the entry of younger talent.

[State Department] U.S. Ambassador-at-Large to Monitor and Combat Trafficking in Persons Cindy Dyer will travel to Madagascar November 13-16 and South Africa November 17-21.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[allAfrica]

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

[allAfrica]

[The Conversation Africa] Despite the flaws in the latest novel by South African writer Nthikeng Mohlele, there is something alluring about Revolutionaries' House. It is Mohlele's most political novel, and the parallels drawn between love and politics - and their pitfalls - are intriguing.

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems. For example, even GPT-3 at 175 billion parameters is stressing the bandwidth, capacity, training time, and power of the most advanced GPUs on the market.

To this end, Cadence has shown our HBM3E memory subsystem running at 12.4Gbps at nominal voltages, demonstrating the PHY’s robustness and performance margin. The production version of our latest HBM3E PHY supports DRAM speeds of up to 10.4Gbps or 1.33TB/s per DRAM device. This speed represents a >1.6X bandwidth increase over the previous generation, making it ideal for LLM training.

Cadence has been the HBM performance leader since 2021, when we announced our first 8.4Gbps HBM3E PHY supporting >1TB/s of memory bandwidth per HBM DRAM. Customers building advanced AI processors have used this speed while building margin into their systems. Recall that HBM3E is a 3D stacked DRAM with 1024-bit wide data (16 64-bit channels). While this wide data bus enables high data transfer, routing these signals requires interposer technology (2.5D) capable of routing close to 2000 signals (data and control), including silicon, RDL, and silicon bridges.

The interposer design is critical for the system to operate at these data rates. Cadence provides 2.5D reference designs, including the interposer and package, as part of our standard IP package. As demonstrated in our test silicon, these designs give customers confidence they will meet their memory bandwidth requirements. The reference design is also a good starting point, helping to reduce development time and risk. Our expert SI/PI and system engineers work closely with customers to analyze their channels to ensure the best system performance.

Even as HBM3E delivers the highest memory bandwidth today, the industry keeps pushing forward. JEDEC recently announced that HBM4, the next version of the HBM DRAM standard, is nearing completion. JEDEC calls HBM4 an “evolutionary step beyond the currently published HBM3 standard.” They also claim HBM4 “enhancements are vital for applications that require efficient handling of large datasets and complex calculations.” HBM4 will support AI training applications, high-performance computing (HPC), and high-end graphics cards.

Cadence will continue to push the HBM performance boundaries to ensure designers of these data-intensive systems can take advantage of the highest memory bandwidth available.

Learn more about Cadence HBM PHY IP products.

The generative AI market is experiencing rapid growth, driven by the increasing parameter size of Large Language Models (LLMs). This growth is pushing the boundaries of performance requirements for training hardware within data centers. For an in-depth look at this, consider the insights provided in "HBM3E: All About Bandwidth". Once trained, these models are deployed across a diverse range of applications. They are transforming sectors such as finance, meteorology, image and voice recognition, healthcare, augmented reality, high-speed trading, and industrial, to name just a few.

The critical process that utilizes these trained models is called AI inference. Inference is the capability of processing real-time data through a trained model to swiftly and effectively generate predictions that yield actionable outcomes. While the AI market has primarily focused on the requirements of training infrastructure, there is an anticipated shift towards prioritizing inference as these models are deployed.

The computational power and memory bandwidth required for inference are significantly lower than those needed for training. Inference engines typically need between 300-700GB/s of memory bandwidth, compared to 1-3TB/s for training. Additionally, the cost of inference needs to be lower, as these systems will be widely deployed not only in data centers but also at the network's edge (e.g., 5G) and in end-user equipment like security cameras, cell phones, and automobiles.

When designing an AI inference engine, there are several memory options to consider, including DDR, LPDDR, GDDR, and HBM. The choice depends on the specific application, bandwidth, and cost requirements. DDR and LPDDR offer good memory density, HBM provides the highest bandwidth but requires 2.5D packaging, and GDDR offers high bandwidth using standard packaging and PCB technology.

The GDDR7 standard, announced by JEDEC in March of this year, features a data rate of up to 192GB/s per device, a chip density of 32Gb, and the latest data integrity features. The high data rate is achieved by using PAM3 (Pulse Amplitude Modulation) with 3 levels (+1, 0, -1) to transmit 3 bits over 2 cycles, whereas the current GDDR6 generation uses NRZ (non-return-to-zero) to transmit 2 bits over 2 cycles.

GDDR7 offers many advantages for AI Inference having the best balance of bandwidth and cost. For example, an AI Inference system requiring 500GB/s memory bandwidth will need only 4 GDDR7 DRAM running at 32Gbp/s (32 data bits x 32Gbp/s per pin = 1024Gb/s per DRAM). The same system would use 13 LPDDR5X PHYs running at 9.6Gbp/s, which is currently the highest data rate available (32 data bits x 9.6Gb/s = 307Gb/s per DRAM).

Cadence stands at the forefront of AI inference hardware support, being the first IP company to roll out GDDR7 PHYs capable of impressive speeds up to 36Gb/s across various process nodes. This milestone builds on Cadence's established leadership in GDDR6 PHY IP, which has been available since 2019. The company caters to a diverse client base spanning AI inference, graphics, automotive, and networking equipment.

While GDDR7 continues to utilize standard PCB board technology, the increased signal speeds seen in GDDR6 (20Gbp/s) and now GDDR7 (36Gb/s) calls for careful attention with the physical design to ensure optimized system performance. In addition to providing the PHY, Cadence also offers comprehensive PCB and package reference design, which are essential in helping customers achieve optimal signal and power integrity (SI/PI) for their systems.

Cadence is dedicated to ensuring customer success beyond just providing hardware. They provide expert support in SI/PI, collaborating closely with customers throughout the design process. This approach ensures that customers can benefit from Cadence's expertise in navigating the complexities of high-speed design and achieving optimal performance in their AI inference systems.

As the AI market continues to advance, Cadence remains at the forefront by offering a comprehensive memory IP portfolio tailored for every segment of this dynamic market. From DDR5 and HBM3E, which cater to the intensive demands of training in servers and high-performance computing (HPC), to LPDDR5X designed for low-end inference at the network edge and in consumer devices, Cadence's offerings cover a wide range of applications.

Looking to the future, Cadence is dedicated to innovating at the forefront of memory system performance, ensuring that the evolving needs of AI training and inference are met with the highest standards of excellence. Whether it's pushing the boundaries with GDDR7 or exploring new technologies, Cadence is dedicated to driving the AI revolution forward, one breakthrough at a time.

Learn more about Cadence GDDR7 PHY

Learn more about Cadence Simulation VIP for GDDR7.

The demand for higher-performance computing is greater than ever. Cutting-edge applications in artificial intelligence (AI), big data analytics, and databases require high-speed memory systems to handle the ever-increasing volumes and complexities of data. Advancements in cloud computing and machine virtualization are stretching the limits of current capabilities. AI applications hosted in the cloud rely on fast access and reduced latency in memory systems, which is amplified by an increasing number of CPU and GPU cores.

Introducing the DDR5 Multiplexed Rank DIMM (MRDIMM), the next-generation memory module technology designed to meet the needs of high-performance computing (HPC) and AI in cloud applications. By leveraging existing DDR5 DRAM memory devices, MRDIMM modules not only double the DRAM data rate but also maintain the RAS capabilities of the industry-proven RDIMM modules, setting a new precedent for memory module performance.

Let’s compare RDIMM and MRDIMM modules using the same DRAM parts. Today, high-speed production DDR5 RDIMM modules run at 5600Mbps. Those modules use DDR5 DRAM parts, which also run at 5600Mbps. An MRDIMM module using the same DDR5 5600Mbps DRAM parts will run at a blazing 11.2Gbps.

One key metric for best-in-class performance, low bit error rate (BER), and ease of adoption is the eye diagram. The eye diagram illustrates at-speed system margin and accurately represents DDR system quality when captured with a pseudo-random binary sequence (PRBS)-like pattern. The diagram below illustrates Cadence’s 3nm silicon write eye diagram for DDR5 MRDIMM IP running at 12.8Gbps.

Cadence 3nm DDR5 MRDIMM 12.8Gbps test chip write eye diagram, design kit is available today

The eye diagram is captured using a PRBS-like pattern, incorporating a package and system board representative of a typical MRDIMM channel. Using PRBS-like patterns is crucial for capturing accurate eye diagrams. Repetitive clock-like data patterns create deceptively “open eyes” that do not reflect the real system performance. Effects like intersymbol interference, simultaneous switching, reflections, and crosstalk are not accurately reflected in the eye diagrams for parallel interfaces like DDR using non-random data streams. Relying on improperly captured eye diagrams inevitably leads to a significantly worse real system BER than conveyed by that eye diagram.

Doubling the DDR5 RDIMM data rate is challenging. Achieving high performance while optimizing for area and power requires multiple design techniques. Feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and T-coils are required to reach 12.8Gbps MRDIMM data rates in multi-channel systems. Building a production-worthy 12.8Gbps DDR5 MRDIMM IP requires engineering expertise that comes from many generations of memory interface design and production experience. Cadence has developed this expertise through multiple DDR5/4, LPDDR5X/5, and GDDR6 designs in different technology nodes and foundries. For instance, Cadence’s GDDR6 IP is available in three foundries and ten process nodes, with mass production at speeds exceeding 22Gbps.

For your next project, consider DDR5 12.8Gbps MRDIMM, a technology that not only doubles the bandwidth of DDR5 RDIMM but also promises rapid proliferation into next-generation AI, data center, HPC, and enterprise applications. With its cutting-edge capabilities, the Cadence DDR5 12.8Gbps MRDIMM IP is ready to power the future of computing.

As vehicles transition into interconnected ecosystems, artificial intelligence and advanced technologies become increasingly crucial. Infotainment systems have evolved beyond mere music players to become central hubs for connectivity, entertainment, and navigation. With global demand for comfort, convenience, and safety rising, the automotive infotainment market is experiencing significant growth. Valued at USD14.99 billion in 2023, it is projected to grow at a compound annual growth rate (CAGR) of 9.9% from 2024 to 2030.

To keep pace with this evolution, infotainment systems must accommodate a range of workloads, including audio, voice, AI, and vision technologies. This requires a flexible, scalable Digital Signal Processor (DSP) solution that acts as an offload engine for the main application processor. Integrating a single DSP for varied functions offers a cost-effective solution for high-performance, low-power processing, which aligns well with the needs of Electric Vehicles (EVs).

If you missed the detailed presentation by Casey Ng, Product Marketing Director at Cadence at CadenceLIVE 2024, register at the CadenceLIVE On-Demand site to access it and other insightful presentations. Stay ahead of the curve and explore the future of innovative electronics with us.

Cadence Infotainment Solution: Leading the Charge

Cadence Tensilica HiFi DSPs play a crucial role in enhancing audio capabilities in vehicle infotainment systems. They support applications like voice recognition, hands-free calling, and deliver immersive audio experiences. This technology is also paramount for features such as active noise control, which reduces road and cabin noise, and acoustic event detection for identifying unusual sounds like broken glass. One notable innovation is the "audio bubble," enabling personalized audio zones within the vehicle, ensuring passengers enjoy distinct audio settings.

Cadence HiFi DSP technology enriches the driving experience for electric vehicles by mimicking traditional engine sounds, while its advanced audio processing ensures optimal performance across various digital radio standards. It significantly contributes to noise reduction, hence improving the cabin experience. Integrating a Double Precision Floating Point Unit (FPU) stands out, as it upgrades audio performance and Signal-to-Noise Ratio (SNR) through efficient 64-bit processing, allowing control over numerous speakers without hitches.

These advancements distinguish the DSP as an essential tool in evolving infotainment systems, offering unmatched performance and adaptability. Tensilica HiFi processors, crucial to advanced infotainment SoCs, serve as efficient offload processors, augmenting real-time execution and energy efficiency. Cadence’s ecosystem, with over 200 codecs and software partnerships, propels the evolution of innovative infotainment systems. Introducing the HiFi 5s DSP marks a new era in connected car experiences, setting the stage for groundbreaking advancements.

Exploring Tomorrow with HiFi 5s DSP Technology

The HiFi 5s represents the apex of audio and AI digital signal processing performance. Built on the Xtensa LX8 platform, it introduces capabilities like auto-vectorization, which allows standard C code to be automatically optimized for performance. This synergy of hardware and software co-design marks a significant step forward in DSP technology. By leveraging its extended Single Instruction, Multiple Data (SIMD) capabilities alongside features like a double-precision floating-point unit (DP_FPU), the HiFi 5s delivers unparalleled precision and speed improvements in signal and audio processing tasks. Equally notable are its branch prediction and L2 cache enhancements, which optimize system performance by refining the control code execution and recognizing codec efficiency. The application of such enhancements are particularly beneficial in real-world scenarios.

AI-Powered Audio

Cadence's focus on AI integration with the HiFi 5s demonstrates significant improvements in audio clarity through AI-powered solutions.

• AI models learn from real-world data and adapt dynamically, while classic DSP algorithms rely on fixed rules.
• AI can be fine-tuned for specific scenarios, whereas classic DSP lacks flexibility.
• AI handles extreme and marginal noise patterns better, generalizes well across different environments, and is robust against varying noise characteristics.

Cadence's dedication to artificial intelligence marks a pivotal shift in audio processing. Traditional DSP algorithms, bound by rigid rules, are eclipsed by AI's ability to learn dynamically from real-world data. This adaptability equips AI models to tackle challenging noise patterns and offer unmatched clarity even in noisy environments, making them ideal for automotive and consumer audio applications.

Realtime AI-Optimized Speech Enhancements by OmniSpeech and ai|coustics

OmniSpeech

Our partner, OmniSpeech, has advanced AI-based audio processing that enhances the performance of audio software, specifically for omnidirectional and dipole microphones. Impressively, their technology operates with less than 32MHz and requires only 418kB of memory.

Test results show that background noise is significantly reduced when AI employs a single omnidirectional microphone, outperforming non-AI solutions. Additionally, when using a dipole microphone with AI, there is a 3.5X improvement in the weighted Signal-to-Noise Ratio (SNR) and more than a 28% increase in the Global Mean Opinion Score (GMOS) across various background noise.

ai|coustics

ai|coustics, a Cadence partner specializing in advanced audio technologies, utilizes real-time AI-optimized speech enhancement algorithms. They leverage an extensive speech-quality dataset containing thousands of hours and 100 languages to transform low-quality audio into studio-grade audio. Their process includes:

• De-reverb, which eliminates room resonances, echoes, and reflections

• Removing artifacts from downsampling and codec compression

• Dynamic and adaptive background noise removal

• Reviving audio materials with analog and digital distortions

• Providing support for all languages, accents, and a variety of speakers

Applications include:

• Automotive: Enhances clarity of navigation commands and communication for driver safety

• Consumer audio: Improves voice clarity for better dialogue understanding in TV programs. Optimizes speech intelligibility in communication for both uplink and downlink audio streams

• Smart IoT: Boosts voice command detection and response quality

Performance Enhancements

The advancements in branch prediction and L2 cache integration have significantly boosted performance metrics across various systems. With HiFi 5s, branch prediction increases codec efficiency by an average of 5%, reaching up to 16% in optimal conditions. L2 cache improvements have drastically enhanced system-level performance, evidenced by a 2.3X boost in EVS decoder efficiency. Adding MACs and imaging ISA in imaging use cases has led to substantial advancements. When comparing HiFi 5s to HiFi 5, imaging ISA performance improvements range with >60% average performance improvements.

The Crescendo of the Future

As Cadence continues to blaze trails in DSP technology, the HiFi 5s emerges as the quintessential solution for consumer and automotive audio use cases. With a robust framework for auto-vectorization, an unmatched double-precision FPU, AI-driven audio solutions, and comprehensive system enhancements, Cadence is orchestrating the next era of audio processing, where every note is clearer, every sound richer, and every experience more engaging. It is not just the future of audio—it's the future of how we experience the world around us.

 Discover how Cadence Automotive Solutions can transform your business today!

Staying ahead of the curve is essential to meeting customer needs. Cadence has consistently demonstrated its commitment to innovation, and its latest IP portfolio available on TSMC's 3nm (N3) process is no exception. Today, rapid advancements in AI/ML, hyperscale computing (HPC), and the automotive industry are driving significant changes in technology. Let's explore the impressive array of IP that Cadence offers on this advanced node.

Memory Solutions: High-Speed and Power-Efficient

Cadence's DDR5 12.8G MRDIMM IP supports the highest speed grade Gen2 MRDIMMs and features a fully hardened PHY optimized to the customer's floorplan. The LPDDR5X IP is silicon-proven at 9.6Gbps and is ideal for power-sensitive applications, offering a fully integrated memory subsystem.

GDDR7: Leading the Way in Graphics Memory

Cadence has achieved a significant milestone with the world's first silicon-proven GDDR7 IP, supporting data rates up to 32Gbps. This IP offers the best price/performance ratio for AI interfaces, making it a game-changer in the graphics memory domain.

PCIe and CXL Solutions: Robust and Reliable

Cadence's PCIe 3.0 IP is a mature and production-proven solution available across a wide range of process nodes from 28nm to 3nm. It offers a versatile multi-link architecture for optimum SoC configurability and flexible use cases. The PCIe 6.0 and CXL 3.x solutions are silicon-proven, power-optimized, and highly robust, with jitter-tolerant capabilities. These IP are the only subsystem proven with eight lanes of controller and PHY in silicon, ensuring interoperability with leading test vendors and OEMs.

UCIe PHY: Setting New Standards

The UCIe PHY IP from Cadence are set to be generally available after successful silicon characterization in both standard and advanced package options on the TSMC N3 (3nm) process. These IP demonstrate significantly better power, performance, and area (PPA) metrics than the specifications, with a bit error rate (BER) better than 1E-27 compared to the spec of 1E-15. The power consumption is also notably lower than the spec limit, ensuring a simpler integration with a best-in-class power profile.

112G PHY IP: Pushing the Boundaries of Performance

Cadence's 112G PHY IP are designed to meet the demands of high-speed data transmission. The 112G-ULR PHY IP, characterized in the 3nm process, showcases exceptional performance with support for insertion loss over 45dB at data rates ranging from 1.25Gbps to 112.5Gbps. This IP is optimized for both power and area, making it a versatile choice for various applications. The 112G-VSR/MR PHY IP also stands out with its excellent power and performance metrics, making it ideal for short-reach applications and optical interconnects. Additionally, the 112G PAM4 PHY solutions cater to hyperscale, AI, HPC, and optics applications, featuring a mature DSP-based SerDes architecture with advanced techniques such as reflection cancellation.

Cadence's IP portfolio on TSMC N3 shows innovation and expertise to solve today's design challenges. From high-speed PHY IP to robust PCIe and CXL solutions and advanced memory IP, Cadence continues to lead the way in semiconductor IP development. These solutions not only meet but exceed industry standards, ensuring that customers can confidently achieve their design goals. Stay tuned for more updates on Cadence's groundbreaking advancements in semiconductor technology.

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Is there any way to instruct the tool to reduce the low metals effort and route more on top layers?