1 Japanese Yen = 139.8628 Indonesian Rupiah

1 Japanese Yen = 3.0292 Hungarian Forint

1 Japanese Yen = 0.0076 British Pound Sterling

1 Japanese Yen = 1.203 Algerian Dinar

1 Japanese Yen = 0.516 Dominican Peso

1 Japanese Yen = 0.0663 Chinese Yuan Renminbi

1 Japanese Yen = 0.0035 Bahraini Dinar

1 Japanese Yen = 0.6231 Argentine Peso

Which is the only palindromic song by a palindromic group to have entered the US charts?

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In the book “The World of _____” by Bennett Alan Weinberg and Bonnie K Bealer, there is a photograph of a label from a jar of pharmaceutical-grade crystals. It reads:

“WARNING: MAY BE HARMFUL IF INHALED OR SWALLOWED. HAS CAUSED MUTAGENIC AND REPRODUCTIVE EFFECTS IN LABORATORY ANIMALS. INHALATION CAUSES RAPID HEART RATE, EXCITEMENT, DIZZINESS, PAIN, COLLAPSE, HYPOTENSION, FEVER, SHORTNESS OF BREATH. MAY CAUSE HEADACHE, INSOMNIA, VOMITING, STOMACH PAIN, COLLAPSE AND CONVULSIONS.”

Fill in the blank.

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X is a song written by Y and famously covered by Z. Time Magazine’s Josh Tyrangiel described it thus:

Y murmured the original like a dirge, but except for a single overwrought breath before the music kicks in, Z treated the 7-min. song like a tiny capsule of humanity, using his voice to careen between glory and sadness, beauty and pain, mostly just by repeating the word X. It’s not only Z’s best song — it’s one of the great songs, and because it covers so much emotional ground and is not (yet) a painfully obvious choice, it has become the go-to track whenever a TV show wants to create instant mood. ‘X can be joyous or bittersweet, depending on what part of it you use,’ says Sony ATV’s Kathy Coleman. ‘It’s one of those rare songs that the more it gets used, the more people want to use it.’

Name X, Y and Z.

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Check out Norman Mailer’s ten favourite American novels.

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A few customers have recently asked whether we can provide schematic-based ERC checks.  This is no doubt spurred by a recent product announcement by one of our competitors.  No - I'm not going to say who, and I'm not going to provide a link to their product page. 

We have had layout-based ERC checks as part of our Assura physical verification product since release 3.2 became available last August.  A quick check with our field AEs revealed that it's also possible to use Assura for ERC checks based on netlists and schematics, as well as layouts.  One of our AEs has put some instructions together, and it actually looks pretty easy.  Ask your friendly Cadence physical verification expert for a copy of the document, and tell them to send out an email on the Cadence internal Assura AE email alias if they can't find it right away.  While you're at it, ask about the 10x performance improvement that we made in Assura 3.2. 

It's interesting that our competitor has made a separate product from this when we give it away for free with Assura.  Marketing, I guess. 

The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model?  I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

In my last post I talked about the layout, schematic and netlist ERC capabilities of Assura. 

"But", I hear you ask, "is it programmable?"

One of the characteristics that makes Assura such a natural fit within the Virtuoso custom design platform is that it shares the platform's programming language, SKILL.  So yes, it's programmable - in the very same language that your Pcells are written in. 

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...(read more)

What is the meaning of this error?

I used already two ports (PORT1 and PORT2 for input and output, respectively.

-------------------------------------------------------------------------------------------------------------------------

Also when I apply the PSP analysis for S-parameter the value of maximum S21 value (4.75 dB) is much lower than the maximum power gain (17.6 dB).

while the same circuit is designed using  ADS program the two values are approximately the same around (17.1 dB).

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I am designing a resistive feedback TIA which needs a capacitor in its feedback loop for stability.

I would like to know the effect of a feedback capacitor on the phase margin to determine the optimal capacitance value.

My plan is to add it to the results after the stb analysis by using the direct plot>main form > phase margin (add to outputs).However it not getting added to my results list.

What could be a problem? Is there a way to add phase margin to the results using the calculator? 

I also find that the gain from the stability analysis(the closed loop gain) is different from that of the gain obtained for the closed loop simulation in AC analysis. Why is the difference, how is it computed in stability analysis?

Thanks,

-Rakesh.

I’m writing this on August 15. It is our Independence Day. A young Kashmiri Muslim told me in Srinagar a few months ago that this is the day on which everyone there tries to stay indoors. This is not because the people support Pakistan, but because they are most suspect on August 15. You are questioned, searched, and locked. If any of the readers have had a chance to view Sanjay Kak’s powerful documentary Jashn-e-Azadi (How We Celebrate Freedom) you’ll see how Sanjay, coming in to Srinagar for a visit around Independence Day, is struck by the fact that the only people present for the ceremony are the cops and members of the armed forces. (That’s Rave Out #1. For Jashn-e-Azadi.)

Last week’s announcement of the Indian Express-CNN/IBN poll, that an overwhelming majority of Kashmiris in the valley want azadi, also underlines the importance of a genuine rethinking on the question of independence rather than empty, nationalist sabre-rattling. (Anyway, that’s Rave Out #2. For Indian Express and CNN/IBN, as well as the good folk at CSDS who designed the poll.)

This is a good day for re-opening the pages of 13 December: A Reader, in which thirteen writers and journalists point out the injustice involved in the quick media-lynching of SAR Geelani and the denial of a fair trial to Afzal Guru. (This would be Rave Out #3, for the book, although wouldn’t it be great if the book weren’t needed?)

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Over ten years ago, Suzanne Vega hit a terribly sexy groove with an album called Nine Objects of Desire that made me seek out every CD she has done since then. She’s kept us waiting for six years for her new studio effort, but it’s such vintage Vega that the reward is well worth the wait.

The first thing to note on Beauty & Crime is that producer Jimmy Hogarth and mixer Tchad Blake  have tuned the album’s tracks entirely to suit Vega’s rather inflexible, breathy voice. With the sonic help, Vega is freed up to focus on enunciating the layers behind her lyrics. Yet Hogarth and Blake also manage to seed each song with finely crafted arrangements and subtle hooks that make them musically interesting.

Although Vega uses a large canvas to record her ruminations, her most touching songs are those that are personal. On “Ludlow Street” she quietly mourns the passing of her brother: “I find each stoop and doorway’s incomplete/without you there”.

On the superbly produced “Bound”, she seems to be confirming her longtime friend Paul Mills’s continuing interest in her after her divorce from Michael Froom in 2001. On “As You Are Now” she manages – against all odds - to fit in a parent’s love for her child in four sweet verses.

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A couple of evenings ago, my cousin Debika and I were discussing how we’d react if we were told we had just a few months to live. She said she would try and do everything she liked in that time, and surround herself with her family. I said that I’d be inclined to save people I cared for the pain of watching me die—whatever that took. Ironically and unexpectedly, shortly after this conversation, we found ourselves watching François Ozon’s remarkable film Time to Leave.

The film begins with its protagonist, Romain, discovering that he is terminally ill with cancer, and deciding not to bother with treatment. He does not tell his friends or family of his condition. He is rude to his sister, and drives her to tears. He tells his lover, Sasha, that he does not love him, and drives him to move out of their house. This is a transparent lie, but though we see it, Sasha doesn’t. He confides to his grandmother—marvellously played by Jeanne Moreau—because she is like him, and “will die soon.” But even in this winding up, complications ensue.

Melvil Poupaud plays Romain, and is magnificent – understated, yet effortlessly expressive. But it is Ozon’s storytelling that makes this film memorable. It is spare, focussing only on the essential, and revealing its essence. There is not a frame out of place in this heartbreaking film that ends, like Romain, too soon and in great beauty.

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I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

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Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for...(read more)

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies...(read more)

Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and...(read more)

With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...(read more)

How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.(read more)

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed...(read more)

Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.(read more)

Status2k remote add administrator exploit.

Genere par KDPics version 1.18 remote add administrator exploit.

Limny CMS version 2.0 suffers from a cross site request forgery vulnerability that allows for a malicious attacker to have an administrator account created. Proof of concept code included.

PBBoard version 2.0.5 suffers from add administrator and shell upload vulnerabilities.

NinkoBB version 1.3RC4 change / add administrator cross site request forgery exploit.

Advanced Management For Services Sites remote add administrator exploit.

DL_Stats suffers from cross site scripting, arbitrary administrative access and remote SQL injection vulnerabilities.

Sysax Multi Server add administrator exploit.

PageDirector CMS suffers from add administrator and remote SQL injection vulnerabilities.

Web@All versions 1.1 and below remote administrative settings changing exploit.

Simple PHP Newsletter suffers from a remote administrative password changing vulnerability when the install script is left in place.

WESPA PHP Newsletter version 3.0 suffers from a remote administrative password changing vulnerability when the install script is left in place.

Izlebizi Video Script remote add administrator account exploit.

112 bytes small Win32/PerfectXp-pc1/sp3 (Tr) add administrator shellcode.

ZOHO ManageEngine ADSelfService Plus version 4.5 Build 4521 suffers from an authentication bypass vulnerability.

Weboptima CMS suffers from add administrator and remote shell upload vulnerabilities.

Traidnt Upload 3 add administrator exploit that leverages cookie manipulation.

Desktop Central versions 7 and forward suffer from an add administrator vulnerability.

phpBugTracker 1.7.5 suffers from cross site scripting, authorization bypass, and SQL injection vulnerabilities.