Winds are from the West at 12.7 gusting to 28.8 MPH (11 gusting to 25 KT). The pressure is 1013.2 mb and the humidity is 54%. The wind chill is 29. Last Updated on May 9 2020, 11:53 am EDT.

Winds are from the West at 23.0 gusting to 28.8 MPH (20 gusting to 25 KT). The pressure is 1010.8 mb and the humidity is 49%. The wind chill is 21. Last Updated on May 9 2020, 11:56 am EDT.

Winds are from the Northwest at 15.0 gusting to 24.2 MPH (13 gusting to 21 KT). The pressure is 1011.5 mb and the humidity is 52%. The wind chill is 23. Last Updated on May 9 2020, 11:53 am EDT.

Arduino’s MKR family of products got two new wireless connectivity boards added to its range of products. These include MKR WiFi 1010 and MKR NB 1500, both aimed at streamlining IoT product/service development.

Arduino’s blog notes that “the Arduino MKR WiFi 1010 is the new version of the MKR1000 with ESP32 module on board made by U-BLOX.”

MKR WiFi 1010: For prototyping of WI-FI based IoT applications

The core difference of MKR WiFi 1010 compared to MKR WiFi 1000 is that the former can be put to use in production-grade IoT apps and it has ESP32-based module manufactured by u-blox. The former enables to add 2.4GHz WiFi and Bluetooth capability to the application. Additionally, it comes with a programmable dual-processor system (an ARM processor and a dual-core Espressif IC).

MKR NB 1500: For on-field monitoring systems and remote-controlled LTE-enabled modules

The Arduino MKR NB 1500 is based on new low-power NB-IoT (narrowband IoT) standard. This makes it appropriate for IoT apps running over cellular/LTE networks.

Key use cases of this board are remote monitoring systems and remote-controlled LTE-enabled modules. It supports AT&T, T-Mobile USA, Telstra, Verizon over the Cat M1/NB1 deployed bands 2, 3, 4, 5, 8, 12, 13, 20 and 28.

Arduino also pitches this board to be used in IoT apps which used to rely on alternative IoT networks such as LoRa and Sigfox. It promises to save power compared to GSM or 3G cellular-based connections.

Winds are from the West at 12.7 gusting to 20.7 MPH (11 gusting to 18 KT). The humidity is 75%. The wind chill is 22. Last Updated on May 9 2020, 11:55 am EDT.

Winds are from the Northwest at 17.3 gusting to 31.1 MPH (15 gusting to 27 KT). The pressure is 1014.7 mb and the humidity is 55%. The wind chill is 29. Last Updated on May 9 2020, 11:54 am EDT.

Winds are from the Northwest at 11.5 gusting to 25.3 MPH (10 gusting to 22 KT). The pressure is 1013.0 mb and the humidity is 52%. The wind chill is 31. Last Updated on May 9 2020, 11:53 am EDT.

[Daily Maverick] The last legal challenge to the prosecution of former President Jacob Zuma and French arms company Thales has been dismissed by the Constitutional Court. On Friday, the apex court ruled that Thales' attempt to persist in having the prosecution permanently stayed had no chances of success.

[African Arguments] Domestic abuse has spiked under COVID-19. Cash transfers are no panacea, but they've been shown to reduce violence and can be adapted.

Winds are from the West at 13.8 gusting to 21.9 MPH (12 gusting to 19 KT). The humidity is 64%. The wind chill is 19. Last Updated on May 9 2020, 11:55 am EDT.

Winds are from the West at 27.6 gusting to 35.7 MPH (24 gusting to 31 KT). The pressure is 1010.6 mb and the humidity is 50%. The wind chill is 25. Last Updated on May 9 2020, 11:53 am EDT.

Researchers highlight risk of asymptomatic infection, as Europe begins easing lockdown

• Coronavirus – latest updates
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More than 10 times as many people in Germany as thought may have been infected with coronavirus, researchers have said, as Italy led swathes of Europe out of lockdown and officials said the continent’s outbreak was mostly past its peak.

Researchers from Bonn University said on Monday that their preliminary study, based on fieldwork in the town of Gangelt in Heinsberg municipality, which had one of Germany’s highest death tolls, showed the risk of infection by asymptomatic carriers.

Coronavirus has infected more than 3.5 million people and caused nearly 250,000 deaths worldwide, according to the Johns Hopkins University tracker.

China’s state broadcaster CCTV attacked the US secretary of state’s “insane and evasive remarks” on the origins of the pandemic. Mike Pompeo said there was “enormous evidence” to show the virus originated in a lab in China.

As Donald Trump presses states to reopen their economies, his administration is privately projecting daily deaths will almost double to about 3,000 by 1 June, according to an internal document seen by the New York Times.

Japan’s prime minister, Shinzo Abe, extended the country’s national state of emergency to 31 May, adding that he would consider lifting it earlier if experts decided that was possible based on regional infection trends.

World leaders, with the exception of Trump, stumped up nearly €7.4bn (£6.5bn) to research Covid-19 vaccines and therapies, pledging the money would also be used to distribute any vaccine to poor countries on time and equitably.

Figures from human rights commissioner paint different picture to that provided by police

• Coronavirus – latest updates
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Reported cases of domestic violence in Russia have more than doubled during the country’s coronavirus lockdown, according to the Russian human rights commissioner, who painted a different picture to that provided by police data.

Complaints and reports made to Russian non-governmental organisations spiked from roughly 6,000 in March to more than 13,000 in April, Tatyana Moskalkova said on Tuesday. “The picture is rather non-optimistic,” the RIA Novosti news agency quoted her as saying.

Related: 'Calamitous': domestic violence set to soar by 20% during global lockdown

Related: How the killing of an abusive father by his daughters fuelled Russia's culture wars

Fake social media accounts also used to support Ron Paul’s presidential bid and the Occupy movement

Iran’s state broadcaster experimented with using fake social media accounts to influence the outcome of the 2014 Scottish independence referendum and other western elections, according to a report from Facebook released on Tuesday.

The Iranian network, one of eight to be suspended for so-called “coordinated inauthentic behaviour” by the social media giant in April, points to efforts by state-linked groups to try to use Facebook to influence foreign democratic contests years before Russia’s alleged campaign against the 2016 US presidential contest.

Decades after Bhopal, lack of law enforcement and political will plagues Indian industry

The gas leak at a chemical factory in Visakhapatnam will immediately remind many in India and beyond of the 1984 Bhopal disaster, widely considered the world’s worst industrial disaster.

So far, the scale of the tragedies are very different. Eleven people are confirmed to have died in Visakhapatnam – but with hundreds hospitalised and thousands affected, there are fears the toll will rise. In Bhopal, 4,000 people died within days of the toxic gas leak from a pesticide plant in the central Indian city, and thousands more in the following years.

More details have emerged on a virtual draft in early June. Plus, the latest on when, where and how the season could resume.

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...(read more)

Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will store and charge the pucks when not in use.

I'm trying to work out the best way to charge the battery. I'm thinking of having metal "pads" on the rr.com puck that pass through the puck's plastic shell and then make contact with the PCB on the inside, and having a similar system on the charging dock. I'm thinking of having SMD "contact sprints" mounted to the underside of the PCB and have these mate against metal pins that protrude through the puck, but it's the later of which I'm struggling to find. For a visual, think about "restaurant pagers" and how they charge.

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test reduced to 12 hours, dramatic test coverage increase.

Trolling through the CDNLive archives, I discovered another gem. At the May 2013 CDNLive in Munich, Thomas Henkel and Henriette Ossoinig of Advantest presented a paper titled “Timing-accurate emulation of a mixed-signal SoC using Palladium XP”. Advantest makes advanced electronics test equipment. Among the semiconductor designs they create for these products is a test processor chip with over 100 million logic transistors, but also with lots of analog functions.They set out to find a way to speed up their full-chip simulations to a point where they could run the system software. To do that, they needed about a 50X speed-up. Well, they did it!

Figure 1: Advantest SoC Test Products

To skip the commentary, read Advantest's paper here. 

Problem Statement

Software is becoming a bigger part of just about every hardware product in every market today, and that includes the semiconductor test market. To achieve high product quality in the shortest amount of time, the hardware and software components need to be verified together as early in the design cycle as possible. However, the throughput of a typical software RTL simulation is not sufficient to run significant amounts of software on a design with hundreds of millions of transistors.  

Executing software on RTL models of the hardware means long runs  (“deep cycles”) that are a great fit for an emulator, but the mixed-signal content posed a new type of challenge for the Advantest team.  Emulators are designed to run digital logic. Analog is really outside of the expected use model. The Advantest team examined the pros and cons of various co-simulation and acceleration flows intended for mixed signal and did not feel that they could possibly get the performance they needed to have practical runtimes with software testbenches. They became determined to find a way to apply their Palladium XP platform to the problem.

Armed with the knowledge of the essential relationship between the analog operations and the logic and software operations, the team was able to craft models of the analog blocks using reduction techniques that accurately depicted the essence of the analog function required for hardware-software verification without the expense of a continuous time simulation engine.

The requirements boiled down to the following:

• Generation of digital signals with highly accurate and flexible timing

• Complete chip needs to run on Palladium XP platform

• Create high-resolution timing (100fs) with reasonable emulation performance, i.e. at least 50X faster than simulation on the fastest workstations

Solution Idea

The solution approach chosen was to simplify the functional model of the analog elements of the design down to generation of digital signal edges with high timing accuracy. The solution employed a fixed-frequency central clock that was used as a reference.Timing-critical analog signals used to produce accurately placed digital outputs were encoded into multi-bit representations that modeled the transition and timing behavior. A cell library was created that took the encoded signals and converted them to desired “regular signals”. 

Automation was added to the process by changing the netlisting to widen the analog signals according to user-specified schematic annotations. All of this was done in a fashion that is compatible with debugging in Cadence’s Simvision tool.  Details on all of these facets to follow.

The Timing Description Unit (TDU) Format

The innovative thinking that enabled the use of Palladium XP was the idea of combining a reference clock and quantized signal encoding to create offsets from the reference. The implementation of these ideas was done in a general manner so that different bit widths could easily be used to control the quantization accuracy.

Figure 2: Quantization method using signal encoding

Timed Cell Modeling

You might be thinking – timing and emulation, together..!?  Yes, and here’s a method to do it….

The engineering work in realizing the TDU idea involved the creation of a library of cells that could be used to compose the functions that convert the encoded signal into the “real signals” (timing-accurate digital output signals). Beyond some basic logic cells (e.g., INV, AND, OR, MUX, DFF, TFF, LATCH), some special cells such as window-latch, phase-detect, vernier-delay-line, and clock-generator were created. The converter functions were all composed from these basic cells. This approach ensured an easy path from design into emulation.

The solution was made parameterizable to handle varying needs for accuracy.  Single bit inputs need to be translated into transitions at offset zero or a high or low coding depending on the previous state.  Single bit outputs deliver the final state of the high-resolution output either at time zero, the next falling, or the next rising edge of the grid clock, selectable by parameter. Output transitions can optionally be filtered to conform to a configurable minimum pulse width.

Timed Cell Structure

There are four critical elements to the design of the conversion function blocks (time cells):

                Input conditioning – convert to zero-offset, optional glitch preservation, and multi-cycle path

                Transition sorting – sort transitions according to timing offset and specified precedence

                Function – for each input transition, create appropriate output transition

                Output filtering – Capability to optionally remove multiple transitions, zero-width, pulses, etc.

Timed Cell Caveat

All of the cells are combinational and deliver a result in the same cycle of an input transition. This holds for storage elements as well. For example a DFF will have a feedback to hold its state. Because feedback creates combinational loops, the loops need a designation to be broken (using a brk input conditioning function in this case – more on this later). This creates an additional requirement for flip-flop clock signals to be restricted to two edges per reference clock cycle.

Note that without minimum width filtering, the number of output transitions of logic gates is the sum of all input transitions (potentially lots of switching activity). Also note that the delay cell has the effect of doubling the number of output transitions per input transition.

Figure 3: Edge doubling will increase switching during execution

SimVision Debug Support

The debug process was set up to revolve around VCD file processing and directed and viewed within the SimVision debug tool. In order to understand what is going on from a functional standpoint, the raw simulation output processes the encoded signals so that they appear as high-precision timing signals in the waveform viewer. The flow is shown in the figure below.

Figure 4: Waveform post-processing flow

The result is the flow is a functional debug view that includes association across representations of the design and testbench, including those high-precision timing signals.

Figure 5: Simvision debug window setup

Overview of the Design Under Verification (DUV)

Verification has to prove that analog design works correctly together with the digital part. The critical elements to verify include:

• Programmable delay lines move data edges with sub-ps resolution

• PLL generates clocks with wide range of programmable frequency

• High-speed data stream at output of analog is correct

These goals can be achieved only if parts of the analog design are represented with fine resolution timing.

Figure 6: Mixed-signal design partitioning for verification

How to Get to a Verilog Model of the Analog Design

There was an existing Verilog cell library with basic building blocks that included:

- Gates, flip-flops, muxes, latches

- Behavioral models of programmable delay elements, PLL, loop filter, phase detector

With a traditional simulation approach, a cell-based netlist of the analog schematic is created. This netlist is integrated with the Verilog description of the digital design and can be simulated with a normal workstation. To use Palladium simulation, the (non-synthesizable) portions of the analog design that require fine resolution timing have to be replaced by digital timing representation. This modeling task is completed by using a combination of the existing Verilog cell library and the newly developed timed cells.

Loop Breaking

One of the chief characteristics of the timed cells is that they contain only combinational cells that propagate logic from inputs to outputs. Any feedback from a cell’s transitive fanout back to an input creates a combinational loop that must be broken to reach a steady state. Although the Palladium XP loop breaking algorithm works correctly, the timed cells provided a unique challenge that led to unpredictable results.  Thus, a process was developed to ensure predictable loop breaking behavior. The user input to the process was to provide a property at the loop origin that the netlister recognized and translated to the appropriate loop breaking directives.

Augmented Netlisting

Ease of use and flow automation were two primary considerations in creating a solution that could be deployed more broadly. That made creating a one-step netlisting process a high-value item. The signal point annotation and automatic hierarchy expansion of the “digital timing” parameter helped achieve that goal. The netlister was enriched to identify the key schematic annotations at any point in the hierarchy, including bit and bus signals.

Consistency checking and annotation reporting created a log useful in debugging and evolving the solution.

Wrapper Cell Modeling and Verification

The netlister generates a list of schematic instances at the designated “netlister stop level” for each instance the requires a Verilog model with fine resolution timing. For the design in this paper there were 160 such instances.

The library of timed cells was created; these cells were actually “wrapper” cells comprised of the primitives for timed cell modeling described above. A new verification flow was created that used the behavior of the primitive cells as a reference for the expected behavior of the composed cells. The testing of the composed cells included had the timing width parameter set to 1 to enable direct comparison to the primitive cells. The Cadence Incisive Enterprise Simullator tool was successfully employed to perform assertion-based verification of the composed cells versus the existing primitive cells.

Mapping and Long Paths

Initial experiments showed that inclusion of the fine resolution timed cells into the digital emulation environment would about double the required capacity per run. As previously pointed out, the timed cells having only combinational forward paths creates a loop issue. This fact also had the result of creating some such paths that were more than 5,000 steps of logic. A timed cell optimization process helped to solve this problem. The basic idea was to break the path up by adding flip-flops in strategic locations to reduce combinational path length. The reason that this is important is that the maximum achievable emulation speed is related to combinational path length.

Results

Once the flow was in place, and some realistic test cases were run through it, some further performance tuning opportunities were discovered to additionally reduce runtimes (e.g., Palladium XP tbrun mode was used to gain speed). The reference used for overall speed gains on this solution was versus a purely software-based solution on the highest performance workstation available.

The findings of the performance comparison were startlingly good:

• On Palladium XP, the simulation speed is 50X faster than on Advantest’s fastest workstation

• Software simulation running 25 days can now be run in 12 hours -> realistic runtime enables long-running tests that were not feasible before

• Now have 500 tests that execute once in more than 48 hours

• They can be run much more frequently using randomization and this will increase test coverage dramatically

Steve Carlson

Whitepaper called Solving Computer Forensic Case Using Autopsy.

This exploit leverages both invalid typecast and memory disclosure vulnerabilities in Microsoft Silverlight 5 in order to achieve code execution. This exploit code demonstrates remote code execution by popping calc.exe. It was obtained through the Packet Storm Bug Bounty program. Google flags this as malware so only use this if you know what you are doing. The password to unarchive this zip is the word "infected".

Microsoft Silverlight 5 suffers from invalid typecast and memory disclosure vulnerabilities that, when leveraged together, allow for arbitrary code execution. A memory disclosure vulnerability exists in the public WriteableBitmap class from System.Windows.dll. This class allows reading of image pixels from the user-defined data stream via the public SetSource() method. BitmapSource.ReadStream() allocates and returns byte array and a count of array items as out parameters. These returned values are taken from the input stream and they can be fully controlled by the untrusted code. When returned "count" is greater than "array.Length", then data outside the "array" are used as input stream data by the native BitmapSource_SetSource() from agcore.dll. Later all data can be viewed via the public WriteableBitmap.Pixels[] property. Exploitation details related to these findings were purchased through the Packet Storm Bug Bounty program.

CA Technologies support is alerting customers about a medium risk vulnerability that may allow a local attacker to gain additional privileges with products using CA Common Services running on the AIX, HP-UX, Linux, and Solaris platforms. The vulnerability, CVE-2016-9795, occurs due to insufficient validation by the casrvc program. A local unprivileged user can exploit the vulnerability to modify arbitrary files, which can potentially allow a local attacker to gain root level access.

The Windows kernel does not properly isolate broadcast messages from low integrity applications from medium or high integrity applications. This allows commands to be broadcasted to an open medium or high integrity command prompts allowing escalation of privileges. We can spawn a medium integrity command prompt, after spawning a low integrity command prompt, by using the Win+Shift+# combination to specify the position of the command prompt on the taskbar. We can then broadcast our command and hope that the user is away and doesn't corrupt it by interacting with the UI. Broadcast issue affects versions Windows Vista, 7, 8, Server 2008, Server 2008 R2, Server 2012, RT. But Spawning a command prompt with the shortcut key does not work in Vista so you will have to check if the user is already running a command prompt and set SPAWN_PROMPT false. The WEB technique will execute a powershell encoded payload from a Web location. The FILE technique will drop an executable to the file system, set it to medium integrity and execute it. The TYPE technique will attempt to execute a powershell encoded payload directly from the command line but it may take some time to complete.

FDI levels have already fallen throughout Iran's main sphere of influence in the region. 

The coronavirus pandemic could change human behaviour more permanently in future.

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 

Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf.

Besides perks such as tax breaks, Belarus’s six free economic zones offer investors convenient logistics and, for companies from neighbouring Ukraine and Russia, a geopolitical safe place to do business. Wendy Atkins reports.