Legal Plus creates and manages annual summit, forum and seminar throughout Asia, Middle East and Europe and partners with leading industry global companies to promote the ever changing landscape on essential legal, financial, regulatory and compliance issues.

These events are invitation only, tailored to general/corporate counsel, chief compliance & risk professionals, accountants, directors, private practice lawyer to gain up to date skills, information and expert advice from the expert practitioners speaking at the events. The events will also provide them with essential knowledge to assist to run their business with transparency, integrity as well as up to date knowledge to make their company a leader in their field.

For sponsorship and speaking opportunities, please visit our website or contact Jason Sinclair at Jason.Sinclair@legalplus-asia.com or call +852 9262 2838.

The Dubai & MENA: 7th International Arbitration & Corporate Crime Summit will be held at Shangri-La Dubai Hotel on 22 January 2020.   The event will bring together international and local speakers to present the most up to date information on Arbitration and Corporate Crime.  It will also be an excellent opportunity to catch-up and meet fellow legal professionals in the region.

Registration is now open. Contact us today or view the latest flyer for registration and program details.
Click here to Download the Brochure

Registration Enquiry: bettina.yan@legalplus-asia.com
Speaking / sponsor Enquiry: jason.sinclair@legalplus-asia.com

Speakers:

• John Bishop, International Independent, Arbitrator, Chairman - AM Session
• Adrian Darbishire QC, QEB Hollis Whiteman, Chairman - PM Session
• Robert Stephen, Registrar, DIFC-LCIA Arbitration Centre (DIFC-LCIA) - Opening Address
• Yves Derains, Founding Partner, Derains & Gharavi International - Keynote Speaker
• Sami Houerbi, Director for Eastern Mediterranean, Middle East & Africa, ICC International Court of Arbitration, Abu Dhabi/Tunis; Partner, Houerbi Law Firm Moderator - Grand Keynote Panel
• And many more

Complimentary seats for In-house/ General Counsel.
Contact us at: legalpluseventsasia@legalplus-asia.com to secure your seat. Condition applies.

To read more in details about the event, click here

The secret to  success is focusing your energy, not in fighting the old, but building the new! 

Today, we are in the era of transitional change and  revolution in the legal field.

Chief Justice Bhosale of Telangana & AP High Court in a recent dialogue quoted that the "Indian judiciary is going to crumble under its own weight".

This is owed to the inefficiency of the process and the large population, which makes the  future of judicial dispute resolution hazy!

A survey of 1000 largest corporates of the US showed that 79% of them used  ADR for dispute resolution which shows the new global shift in the legal arena. 

Now, being a new field, it is loaded with question marks at every step. For efficiently building and growing with the 'new' what we need as young lawyers is  guidance. 

And so, LAWyersClubIndia in collaboration with Gaurav Goyal, MCIArb has requested Mr. RATAN K SINGH FCIArb for a webinar on  Career in  Arbitration'. 

Mr. Singh is a pioneer in the field of arbitration practice and has decades of experience, having argued many cases, chaired numerous matters as an  arbitrator and lectured students and  lawyers all over the world. 

Excited?
Join us for this magnificent hour at 4 on the 22nd.

Tag the aspiring Arbitrators and Practitioners in your network!

Meeting Link:
https://zoom.us/meeting/register/tJwodOGrrT8pGNBoG9sWMQIWjIUSc6fvxCgA  

SC RESERVES ORDER TO DETERMINE BALANCE OF CONCERNS IN PLEA TO RESTORE 4G IN J&K The Supreme Court Bench comprising of Justices NV Ramana, SK Kaul and BR Gavai reserved its judgment on Monday, after hearing both sides ofthe PILs filed by Foundatio

Among the ten of millions of people left idle or thrown out of work by the COVID-19 crisis, garment workers have been among the hardest hit, as orders dry up and shutdowns leave factories shuttered, giving workers plenty to protest at a time when lockdowns are keeping them at home

BEAR ADMINISTRATION BUILDING DEMOLITION AND RECONSTRUCTION

In a bid to curb the transmission of novel Coronavirus, India suspended public transport services and enforced a nearly two-month country-wide lockdown that is currently set to end on May 17.

The company manufactures 38 APIs and intermediates across various therapeutic categories — respiratory, diabetology, gastroenterology, pain management, orthopedics, etc. The company has more than 850 formulation products.

Around 2,000 Indians will be evacuated from the island nation. And for this purpose two Ships of the navy – INS Jalshwa and INS Magar are being used.

The government had last week permitted the companies to restore their manufacturing operations in red, green and organ zones with certain riders.

The Anholt-Ipsos Nation Brands Index has a task of ranking the nations and in it, Canada was a leading country for immigration. In it, there are ranks for 50, nations and Canada was also selected as the best destination for investment.Making Great ProgressAdditionally,…

The immigration authorities of Saskatchewan conducted a final draw of 2019 in the Entrepreneur stream on December 5.Making a Gradual ProcessIn the Saskatchewan Immigrant Nominee Program 62 were invitations issued for immigration where the Candidates…

Prime Minister Justin Trudeau assigned the twin tasks to Marco Mendicino, the Immigration Minister. These are Management of a million new arrivals seeking permanent residents as well as creating a fresh Municipal Nominee Program.Well Defined ResponsibilitiesThe…

The Prime Minister of Canada has addressed the recently appointed Immigration Minister in a recent mandate letter. The mandate letter represents the top preferences for the Canadian immigration future, which comprises increasing immigration goals and…

Ontario immigration is seeking an enhanced allocation of provincial immigrants from the Canadian federal government it receives every year. It wants the allocation in the Ontario Immigrant Nominee Program at 13,300 by 2021, and it is 7,000 in this year. Reasons…

Nova Scotia Province had a record-breaking growth in population and the credit goes to immigrants as well as interprovincial migrants.Impressive Performance by the ProvinceAs per the estimates of Statistics Canada the growth in population was 12,339…

In 2019, Ontario has issued 7,391 nominations in its Ontario Immigrant Nominee Program as per an announcement. OINP had an initial allocation target standing 6,650, and in December 700 places were offered to it by IRCC. It included 41 nominations in…

We present the facts of Express Entry as an option for candidates who have credentials that are similar to the credentials of Meghan and Harry. Their qualifying for permanent residence in Canada is a matter of discussion. There is news about the potential…

1. KBC 2020 Registrations Begin, Iulia Vantur Reacts to Marriage Rumours with Salman Khan  News18
2. Salman Khan, Jacqueline Fernandez promote new song Tere Bina at his farmhouse: ‘This is our cheapest...  Hindustan Times
3. Iulia On Marriage Rumours With Salman Khan: Spending Life With Someone More Important Than Papers  News18
4. Salman Khan shoots song titled 'Tere Bina' with Jacqueline Fernandez at his Panvel farmhouse; reveals det  Times of India
5. Iulia Vantur opens up on marriage rumours with Salman Khan: To be happy with someone is more important than papers  Times of India
6. View Full coverage on Google News

Reserve Bank of India cancels Certificate of Registration of 10 NBFCs

Bandhan Bank to Start Operations from August 23 2015

IDFC Bank will start banking operation from Oct 1, 2015

As per the reports, the companies with a presence in China are back in business with easing of restrictions, while India extended its lockdown further till 3rd May.  How Are Things In China? The trade association Nasscom has said member companies across the sector are operating with almost 80% attendance. Basically, the lockdown in China […]

The post Indian IT Firms Doing Chinese Operations Is Working With 80% Capacity! Chinese Economy Back On Track? first appeared on Trak.in . Trak.in Mobile Apps: Android | iOS.

Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution, a next-generation RTL synthesis tool that takes physical awareness in some new directions.

Here are four important things to know about Genus technology:

• A massively parallel architecture improves turnaround time by up to 5X while maintaining quality of results
• The Genus solution synthesizes up to 10M+ instances flat without impacting power, performance and area (PPA)
• The Genus solution provides tight correlation with the Innovus Implementation System, using the same placement and routing algorithms
• Globally focused PPA optimization saves up to 20% datapath area and power

Compared to previous-generation products such as the Cadence Encounter RTL Compiler Advanced Physical Option, the Genus solution approaches physical synthesis in a different way. The Encounter solution applied physical optimization “at the tail end of synthesis,” said David Stratman, senior principal product manager at Cadence. “We were doing a final incremental push, but we could only do so much, since we had locked in a lot of the earlier steps from a logical-only synthesis perspective.”

Genus Synthesis Solution supports the physical synthesis features in the previous Encounter solution, but it also brings the full physical scope upstream to RTL logic designers. “It’s going to enable the unit-level RTL designer to gain the benefits of physical synthesis without having to understand it,” Stratman said. As an example, users can apply generic (unmapped) placement at the earliest stages of synthesis, using a lightweight version of the Innovus placement engine. The bottom line: “Genus is a full solution where every step of synthesis can be done physically.”

Getting Massively Parallel

If you bring physical data into synthesis, you need a way to improve capacity and runtimes, especially with today’s gigantic advance-node SoCs. That’s why a massively parallel architecture is the cornerstone of the Genus solution. In this way, the Genus solution is following in the footsteps of the Innovus Implementation System, which also provides a massively parallel architecture.

Both the Innovus and Genus solutions can handle blocks of 10M instances flat. Given that SoCs today may have up to 100M instances, and often up to 50-100 top-level blocks, this is an important capability. Many tools today will only handle blocks of 1M instances. As a result, design teams often have to constrain block sizes.

Genus technology offers timing-driven, multi-level design partitioning across multiple threads and machines. It enables a near-linear runtime scaling without impacting PPA. According to Stratman, the Genus solution will scale well beyond 64 CPUs for a large design, with a “sweet spot” around 8-20 CPUs for today’s typical block sizes. Runs that used to take days, he noted, can now be done in hours.

As shown below, Genus technology leverages parallelism at three levels. The Genus solution can distribute design partitions to multiple threads or CPUs, and also supports local algorithm-level multithreading on each machine with shared memory. An adaptive scheduler ensures the best use of the available CPUs.

Fig. 1 – Genus Synthesis Solution provides three levels of parallelism

With its massive parallelism, Stratman said, Genus technology can obtain production-level quality of results (QoR) in runtimes typically seen in “prototype-level” synthesis runs. The “secret sauce,” he said, is in the partitioning. Cadence has found a way to generate partitions in a way that “slices the design more intelligently, and takes advantage of the Genus database to merge partitions without losing timing, power, or area,” Stratman said.

Playing in the Sandbox

In the Genus Synthesis Solution, a process called “sandboxing” allows any subset or partition of a design to be extracted along with full timing and a physical context. Optimization algorithms will treat a sandbox as a complete design.

The “Clipper” flow clips out or extracts the context of the larger SoC blocks. “It’s kind of a skeleton floorplan but it has all the timing information,” Stratman said. These extracted contexts include all the critical physical information to make the right RTL synthesis choices at the unit level. This information is used to streamline the handoffs between unit-level RTL designers, integration engineers, and implementation engineers. It’s a way for logic designers to gain some physical knowledge without having to be a physical synthesis expert, or without having to run a full top-level synthesis.

Fig. 2 – Clipper flow provides context for unit-level blocks

Correlation with Innovus Implementation System

Although Genus technology can work with third-party IC implementation systems, it shares algorithms and engines with Innovus Implementation System, as well as a common user interface. As shown below, both the Genus and Innovus solutions use a table-based Quantus QRC parasitic extraction, effective current source model (ECSM) and composite current source (CCS) delay calculations, and a unified global routing engine. Timing and wire length claim a 5% correlation.

Fig. 3 – Genus Synthesis Solution offers tight correlation with Innovus Implementation System

Genus technology doesn’t model everything to the same level of accuracy as the Innovus solution, however. “We chose to be lighter weight and more nimble to get expected runtimes,” Stratman said. A tight correlation is possible because the Genus and Innovus solutions use a similar code base. This correlation will be tighter than that between Encounter RTL Compiler Advanced Physical Option and the Encounter Digital Implementation System today.

Genus Synthesis Solution uses a new Hybrid Global Router that provides the ability to resolve congestion and construct layer-aware, timing-driven wire topologies. This accelerates analysis and debug, and reduces iterations. Users can avoid blockages and see a full Manhattan route as opposed to “flight lines.” Layer awareness is particularly important, given the large RC variations within the metal stack at advanced process nodes.

A version of the Innovus GigaPlace engine is available within the Genus solution. Here, users can do an RTL-level generic gate placement early in the synthesis flow (“generic gate” means there is no mapping into standard cell libraries, but there’s still an area estimate). This helps designers understand PPA tradeoffs earlier.

While users can go all the way to a design-rule “legal” placement with Genus Synthesis Solution, this isn’t generally recommended. “You can do a placement and use the same algorithms as GigaPlace and get a nice correlation without all the runtimes and additional steps of doing a fully legal placement,” Stratman said.

So where does Genus technology end and Innovus technology begin? That’s up to the user. You could use the Genus solution for logical synthesis and run all physical implementation in the Innovus system. If you run physical synthesis within the Genus solution, there’s more work earlier in the flow, but you get better insights into downstream problems and reduce iterations.

“Physical synthesis should be no more than 2X [runtime] of logic synthesis,” Stratman said. “All of the runtime that moves up should be shaved off of the place-and-route stages, because now you can do lightweight incremental optimization and incremental placement. The overall flow should be runtime neutral or better.”

Be Globally Aware

Finally, Genus Synthesis Solution offers a globally focused early PPA optimization across the whole datapath, delivering up to a 20% area reduction in the datapath. Stratman noted that this capability is a follow-on to an RCP feature called “globally focused mapping” that can determine the best cells to use in a library. What’s new with the Genus solution is that this concept has been applied at the arithmetic level.

For example, there are many ways to configure a multiplier – you may want to prioritize speed, power, or size. In the past, Stratman noted, synthesis tools have not been very good at globally optimizing the architecture selection for PPA optimization. “We can [now] find the most efficient global datapath implementation for a given region,” he said.

For further information about the Cadence Genus Synthesis Solution, including a datasheet and technical product brief, see this landing page.

Richard Goering

Related Blog Posts

Designer View – RTL Synthesis Success Strategies at 28nm and Below

Front-End Design Summit: The Future of RTL Synthesis and Design for Test

Physically-Aware Synthesis Helps Design a New Computer Architecture

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference (DAC 2015) described collaboration models that are working today.

The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left to right in the photo below:

• Prof. Xin Li, Electrical and Computer Engineering, Carnegie-Mellon University (CMU)
• Chuck Alpert, Senior Software Architect, Cadence
• Prof. Laleh Behjat, Department of Electrical and Computer Engineering, University of Calgary

Alpert, who was filling in for Zhuo Li, Software Architect at Cadence, was the vice chair of DAC 2015 and will be the general chair of DAC 2016 in Austin, Texas. “My team at Cadence really likes to collaborate with universities,” he said. “We’re a big proponent of education because we really need the best and brightest students in our industry.”

Contests Boost EDA Research

One way that Cadence collaborates with academia is participation in contests. “It’s a great way to formulate problems to academia,” Alpert said. “We can have the universities work on these problems and get some strategic direction.”

For example, Cadence has been involved with the annual CAD contest at the International Conference on Computer-Aided Design (ICCAD) since the contest was launched in 2012. This is the largest worldwide EDA R&D contest, and it is sponsored by the IEEE Council on EDA (CEDA) and the Taiwan Ministry of Education. Its goals are to boost EDA research in advanced real-world problems and to foster industry-academia collaboration.

Contestants can participate in one of more problems in the three areas of system design, logic synthesis and verification, and physical design. The 2015 contest has attracted 112 teams from 12 regions. Cadence contributes one problem per year in the logic synthesis area. Zhuo Li was the 2012 co-chair and the 2013 chair. The awards will be given at ICCAD in November 2015.

Another step that Cadence has taken, Alpert said, is to “hire lots of interns.” His own team has four interns at the moment. One advantage to interning at Cadence, he said, is that students get to see real-world designs and understand how the tools work. “It helps you drive your research in a more practical and useful direction,” he said.

The Cadence Academic Network co-sponsors the ACM SIGDA PhD Forum at DAC, and Xin Li and Zhuo Li are on the organizing committee. This event is a poster session for PhD students to present and discuss their dissertation research with people in the EDA community. This year’s forum was “packed,” Alpert said, and it’s clear that the event needs a bigger room.

Finally, Alpert noted, Cadence researchers write and publish technical papers at DAC and other conferences, and Cadence people serve on the DAC technical program committee. “We try to be involved with the academic community on a regular basis,” Alpert said. “We want the best and the brightest people to go into EDA because there is still so much innovation that’s needed. It’s a really cool place to be.”

Research Collaboration Exposes Failure Rates

Xin Li presented an example of a successful research collaboration between CMU and Cadence. The challenge was to find a better way to estimate potential failure rates in memory. As noted in a previous blog post, PhD student Shupeng Sun met this challenge with a new statistical methodology that won a Best Poster award at the ACM SIGDA PhD Forum at DAC 2014.

The new methodology is called Scaled-Sigma Sampling (SSS). It calculates the failure rate and accounts for variability in the manufacturing process while only requiring a few hundred, or a few thousand, sample circuit blocks. Previously, millions of samples were required for an accurate validation of a new design, and each sample could take minutes or hours to simulate. It could take a few weeks or months to run one validation.

The SSS methodology requires greatly reduced simulation times. It makes it possible, Li noted, to run simulations overnight and see the results in the morning.

Li shared his secret for success in collaborations. “I want to emphasize that before the collaboration, you have to understand the goal. If you don’t have a clear goal, don’t collaborate. Once you define the goal, stick to it and make it happen.”

Contest Provides Learning Experience

Last year Laleh Behjat handed two of her new PhD students a challenge. “I told them there is an ISPD [International Symposium for Physical Design] contest on placement, and I expect you to participate and I expect you to win. Not knowing anything about placement, I don’t think they realized what I was asking them.”

The 2015 contest was called the Blockage-Aware Detailed Routing-Driven Placement Contest. Results were announced at the end of March at ISPD. And the University of Calgary team, despite its lack of placement experience, took second place.

Such contests provide a good learning tool, according to Behjat. Graduate students in EDA, she said, “have to be good programmers. They have to work in teams and be collaborative, be able to innovate, and solve the hardest problems I have seen in engineering and science. And they have to think outside the box.” A contest can bring out all these attributes, she said.

Further, Behjat noted, contest participants had access to benchmarks and to a placement tool. They didn’t have to write tools to find out if their results were good. Industry sponsors, meanwhile, got access to good students and new approaches for solving problems.

“You can see Cadence putting a big amount of time, effort and money to get students here and get them excited about doing contests,” she said. She advised students in the theater audience to “talk to people in the Cadence booth and see if you can have more ideas for collaboration.”

Richard Goering

Related Blog Posts

EDA Plus Academia: A Perfect Game, Set and Match

Cadence Aims to Strengthen Academic Partnerships

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

Hello everyone,

I am Vinay and I am currently developing some digital circuits for my chip design for my master's thesis at University at Buffalo.

I am fairly very new to Verilog and I don't seem to follow some of the things others find very easy.

Following are the things that I want to do to which I have no clue:

1. Develop certain arithmetic functionality in Verilog

2. Generate netlist for the verilog code

3. Feed the netlist file to Cadence encounter to be able to generate Digital Circuits' layout for my chip

I can use Cadence Virtuoso and Encounter for this but I don't know the exact procedure to get this done.

Could someone please describe the detailed process for doing the things mentioned above.

Thank you.

Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...(read more)

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!!

But:

• How to do it?
• Is there any specific switch required?
• What is the flow/script when Joules is used from within Genus?
• Are all the Joules commands supported?

To answer to all these questions is just a click away in the form of video on “Genus-Joules Integration”; refer it on https://support.cadence.com (Cadence login required).

Video Title: Genus-Joules Integration (Video)

Direct Link: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091CnXUAU&pageName=ArticleContent

Related Resources

Enhance the Genus Synthesis experience with videos: Genus Synthesis Solution: Video Library

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

• Is there any scope to improve power consumption of my design?
• What is the best-case power?
• Pin-point hot spots in my design?
• How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based, where analysis is done by Joules and is explored/implemented by user.

Power Exploration capabilities include:

• Efficiency metrics
• Pin point RTL location
• Cross probe to stim
• Centralize all power data

 Do you want to explore more? What is the flow? What commands can be used?

There is a ONE-STOP solution to all these queries in the form of videos on Joules Power Exploration features on https://support.cadence.com (Cadence login required).

Video Links:

How to Analyze Ideal Power Using Joules RTL Power Solution GUI? (Video)

What is Ideal Power Analysis Flow in Joules RTL Power Solution? (Video)

How to Apply Observability Don’t Care (ODC) Technique in Joules? (Video)

How to Debug Wasted Power Using Ideal Power Analyzer Window in Joules GUI? (Video)

Related Resources

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

•An in silico clinical trial is underway with the 3DEXPERIENCE platform to evaluate the Living Heart simulated 3D heart for transforming how new devices can be tested •Five-year extension of their collaborative research agreement aims to spur medical device innovation by enabling innovative, new product designs •Both Dassault Systèmes and the FDA recognize the transformative impact of modeling and simulation on public health and patient safety

•Dassault Aviation will rely on six Dassault Systèmes industry solution experiences to integrate business processes, improve performance and reduce costs •Deployment marks next step in Dassault Aviation’s digital transformation plan through a platform approach, launched in 2018 •Dassault Systèmes’ 3DEXPERIENCE platform will power artificial intelligence-based application for intelligent enterprise services

Managed DSLS Service will be upgraded on Feb, 29th (starting Saturday Feb, 29th 2020 - 3AM - UTC+1)

Hashes is a cross-platform tool that generates and injects different keys with the same hash code in order to test web applications against hash collision attacks. Written in Java. Has support for Java, PHP, ASP, and V8.

XSSer is an open source penetration testing tool that automates the process of detecting and exploiting XSS injections against different applications. It contains several options to try to bypass certain filters, and various special techniques of code injection.

XSSer is an open source penetration testing tool that automates the process of detecting and exploiting XSS injections against different applications. It contains several options to try to bypass certain filters, and various special techniques of code injection.

WordPress Event-Registration plugin version 5.43 suffers from an arbitrary file upload vulnerability.

CentOS Control Web Panel version 0.9.8.838 suffers from a user enumeration vulnerability.

CentOS-WebPanel.com Control Web Panel (CWP) versions 0.9.8.836 through 0.9.8.840 suffer from a user enumeration vulnerability.

CentOS-WebPanel.com Control Web Panel (CWP) version 0.9.8.848 suffers from a user enumeration vulnerability.

NEC Univerge SV9100/SV8100 WebPro version 10.0 suffers from a remote configuration download vulnerability. The gzipped telephone system configuration file 'config.gz' or 'config.pcpx' that contains the unencrypted data file 'conf.pcpn', can be downloaded by an attacker from the root directory if previously generated by a privileged user.

Whitepaper called Windows User Accounts Penetration Testing. Written in Persian.

Whitepaper called Azure Cloud Penetration Testing.

The Microsoft Windows kernel's Registry Virtualization does not safely open the real key for a virtualization location leading to enumerating arbitrary keys resulting in privilege escalation.

AVideo Platform version 8.1 suffers from an information disclosure vulnerability that allows for user enumeration.