A recent exhibition shows how soldiers sent in votes during the Civil War and World War II, as many Americans would in 2020 following the spread of the Covid-19 pandemic

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COSMOS analysis predicts results to estimated 95 percent accuracy of final-stage testing, validating designs most likely to succeed under real-world conditions

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For Immediate Release Contact: William J. Potter William.potter@delaware.gov 302-761-8163 Wilmington, Del. Feb. 13, 2018 – Delaware workforce training providers will have the chance over the next few months to compete for public funds to train adults and youth in needed job skills thanks to a recently released Request For Proposal. The Delaware Workforce Development Board, […]

The Delaware Department of Agriculture (DDA) announced they will be distributing $199,600 in relief funds through the Seafood Processors Pandemic Response and Safety (SPRS) Block Grant Program to eligible Delaware seafood processors, dealers, and processing vessels who were financially impacted by the COVID-19 pandemic.

After months of diligent preparation and a successful application period that began on August 19, 2024, and closed on September 30, 2024, the Office of the Marijuana Commissioner (OMC) received 1,269 paid license applications – substantially exceeding initial projections.  Fees received by the OMC total $4,069,000. All applications are currently under review to ensure compliance […]

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An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want to quantify the impact of the number of cores, local memory size, system memory latency, and interconnect bandwidth. Software teams wish to have a practical development platform that is not excruciatingly slow. This blog shares a recipe for simulating Cadence DSPs in a multi-core design as separate x86 processes. The purpose is to reduce simulation time for customers with simple multi-core models where cores interact only through shared memory. It uses a Vision Q8 multi-core design to share details of the XTSC (Xtensa SystemC) model, software application, commands, and debugging. Note the details shared are for a simulation run on an Ubuntu Linux machine, Xtensa tools version RI-2023.11, and core configuration XRC_Vision_Q8_AODP. Complex vs. Simple Model A complex model (Figure 1) is one in which one core accesses another core's local memory, or there are inter-core interrupts. Simulation runs as a single x86 process. Figure 1 A simple model (Figure 2) is one in which cores interact only through shared memory. Shared memory is a file on the Linux host. Figure 2 Multiple x86 Process – Simple Model As depicted in Figure 3, each core is simulated using a separate x86 process. Cores use barriers and locks placed in shared memory for synchronization and data sharing. Locks are placed in un-cached memory that support exclusive subordinate access. The XTSC memory component, xtsc_memory , supports exclusive subordinate access. Cadence software tools provide a way to define memory regions as cached or uncached. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK . Figure 3 Demo Application A demo application performs a 128x128 matrix multiplication. Work is divided so that each of the 32 cores computes four rows of the 128x128 result matrix. Cores use barriers to synchronize. Cadence tools provide APIs for synchronization and locking. Please refer to Cadence's System Software Reference Manual for more details. Note without a higher-level lock, prints from all cores will get mixed up. Therefore, in the demo application, only core#0 prints. SystemC Simulation The following sample command runs the 32-core simulation in such a way that each core is a separate x86 process. It runs a matrix multiplication application in cycle-accurate mode with logging off. >>for (( N=0; N >xtsc-run -define=NumCores=32 -define=N=0 -define=LOGGING=0 -define=TURBO=0 --xxdebug=sync -i=coreNN.inc -sc_main=sc_main.cpp -no_sim Modify the sc_main.cpp generated for core#0 to create a generic sc_main.cpp to build a single simulation executable for all cores. The Xtensa SDK includes Makefile targets to build custom simulations. By default, the simulation runs in cycle-accurate mode. Fast functional (Turbo) mode provides additional improvement over cycle-accurate mode. Note that the fast functional mode has an initialization phase, so gains are visible only when running an application with longer run times. Simulation Wall Time The table captures simulation wall time improvements. Note that these are illustrative wall time numbers. Actual wall time numbers and improvements will depend on your host machine's performance and your application. Simulation Type Wall Time Comments Single process cycle accurate mode 17500 seconds Multiple x86 processes cycle accurate mode 1385 seconds 12X faster than single process Multiple x86 processes turbo mode 415 seconds 3X faster than cycle accurate mode Debugging Attaching a debugger to each of the individual x86 core simulation processes is possible. Synchronous stop/resume and core-specific breakpoints are also supported. Configure the Xplorer launch configuration and attach it to the running simulation processes as follows (Figure 5) Figure 5 Figure 6 shows 32 debug contexts. Figure 6 As shown, using Xtensa SDK, you can create a multi-core simulation that functions as a practical software development platform. Please visit the Cadence support site for information on building and simulating multi-core Xtensa systems.

Hi,

Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? 

Cheers,

Antonio

Port-au-Prince, Haiti — A transitional council created to reestablish democratic order in Haiti signed a degree Sunday firing the country's interim Prime Minister Garry Conille and replacing him with Alix Didier Fils-Aime, a businessman who was previously considered for the job. The decree, set to be published on Monday, was provided to The Associated Press by a government source. It marks even more turmoil in an already rocky democratic transition process for Haiti, which hasn't held democratic elections in years in large part due to the soaring levels of gang violence plaguing the Caribbean nation. Fils-Aime, is the former president of Haiti's Chamber of Commerce and Industry and in 2015 ran an unsuccessful campaign for Senate. The businessman studied at Boston University and was previously considered for the position as a private sector candidate for the post before Conille took the seat. Conille, a longtime civil servant who has worked with the United Nations, served as prime minister for only six months. The transitional council was established in April, tasked with choosing Haiti's next prime minister and Cabinet with the hope that it would help quell turmoil Haiti. But the council has been plagued with politics and infighting and has long been at odds with Conille. Organizations like the Organization of American States tried and failed last week to mediate disagreements in an attempt to save the fragile transition, according to reporting from The Miami Herald. The process suffered another blow in October when three members on the council faced corruption accusations, from anti-corruption investigators alleging that they demanded $750,000 in bribes from a government bank director to secure his job. The report was a significant blow to the nine-member council and is expected to further erode people's trust in it. Those same members accused of bribery, Smith Augustin, Emmanuel Vertilaire and Louis Gerald Gilles, were among those to sign the decree. Only one member, Edgard Leblanc Fils, did not sign the order.

[UNHCR] UNHCR, the UN Refugee Agency has just concluded a three-day event, hosting partners and Governments from the East and Horn of Africa, Great Lakes Region and Yemen, to review strategies for comprehensive solutions to the ongoing displacement crisis in Somalia. The meeting brought together representatives from Uganda, Yemen, Djibouti, Ethiopia and Kenya, as well as the regional body, Intergovernmental Authority on Development (IGAD) and provided a platform for sharing insights and aligning efforts among

Title: Diets Heavy in 'Ultra-Processed' Foods Could Harm the Brain
Category: Health News
Created: 7/28/2022 12:00:00 AM
Last Editorial Review: 7/29/2022 12:00:00 AM

The noncoding RNA BC200 is elevated in human cancers and is implicated in translation regulation as well as cell survival and proliferation. Upon BC200 overexpression, we observed correlated expression of a second, smaller RNA species. This RNA is expressed endogenously and exhibits cell-type-dependent variability relative to BC200. Aptamer-tagged expression constructs confirmed that the RNA is a truncated form of BC200, and sequencing revealed a modal length of 120 nt; thus, we refer to the RNA fragment as BC120. We present a methodology for accurate and specific detection of BC120 and establish that BC120 is expressed in several normal human tissues and is also elevated in ovarian cancer. BC120 exhibits remarkable stability relative to BC200 and is resistant to knockdown strategies that target the 3' unique sequence of BC200. Combined knockdown of BC200 and BC120 exhibits greater phenotypic impacts than knockdown of BC200 alone, and overexpression of BC120 negatively impacts translation of a GFP reporter, providing insight into a potential translational regulatory role for this RNA. The presence of a novel, truncated, and stable form of BC200 adds complexity to the investigation of this noncoding RNA that must be considered in future studies of BC200 and other related Alu RNAs.

The strength of reproductive isolation (RI) between two or more lineages during the process of speciation can vary by the ecological conditions. However, most speciation research has been limited to studying how ecologically dependent RI varies among a handful of broadly categorized environments. Very few studies consider the variability of RI and its effects on speciation at finer scales—that is, within each environment due to spatial or temporal environmental heterogeneity. Such variation in RI across time and/or space may inhibit speciation through leaky reproductive barriers or promote speciation by facilitating reinforcement. To investigate this overlooked aspect of speciation research, we conducted a literature review of existing studies of variation in RI in the field and then conducted individual-based simulations to examine how variation in hybrid fitness across time and space affects the degree of gene flow. Our simulations indicate that the presence of variation in hybrid fitness across space and time often leads to an increase in gene flow compared to scenarios where hybrid fitness remains static. This observation can be attributed to the convex relationship between the degree of gene flow and the strength of selection on hybrids. Our simulations also show that the effect of variation in RI on facilitating gene flow is most pronounced when RI, on average, is relatively low. This finding suggests that it could serve as an important mechanism to explain why the completion of speciation is often challenging. While direct empirical evidence documenting variation in extrinsic RI is limited, we contend that it is a prevalent yet underexplored phenomenon. We support this argument by proposing common scenarios in which RI is likely to exhibit variability and thus influence the process of speciation.

Surprisingly little attention has been given to the impact of selfing on speciation, even though selfing reduces gene flow between populations and affects other key population genetics parameters. Here we review recent theoretical work and compile empirical data from crossing experiments and genomic and phylogenetic studies to assess the effect of mating systems on the speciation process. In accordance with theoretical predictions, we find that accumulation of hybrid incompatibilities seems to be accelerated in selfers, but there is so far limited empirical support for a predicted bias toward underdominant loci. Phylogenetic evidence is scarce and contradictory, including studies suggesting that selfing either promotes or hampers speciation rate. Further studies are therefore required, which in addition to measures of reproductive barrier strength and selfing rate should routinely include estimates of demographic history and genetic divergence as a proxy for divergence time.

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By Aimee Raleigh, Principal at Atlas Venture, as part of the From The Trenches feature of LifeSciVC Ever wondered what goes into diligencing a new idea, program, company, or platform? While each diligence is unique and every investor will have

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For the first time, scientists have created a flexible programmable chip that is not made of silicon. The new ultralow-power 32-bit microprocessor from U.K.-based Pragmatic Semiconductor and its colleagues can operate while bent, and can run machine learning workloads. The microchip’s open-source RISC-V architecture suggests it might cost less than a dollar, putting it in a position to power wearable healthcare electronics, smart package labels, and other inexpensive items, its inventors add.

For example, “we can develop an ECG patch that has flexible electrodes attached to the chest and a flexible microprocessor connected to flexible electrodes to classify arrhythmia conditions by processing the ECG data from a patient,” says Emre Ozer, senior director of processor development at Pragmatic, a flexible chip manufacturer in Cambridge, England. Detecting normal heart rhythms versus an arrhythmia “is a machine learning task that can run in software in the flexible microprocessor,” he says.

Flexible electronics have the potential for any application requiring interactions with soft materials, such as devices worn on or implanted within the body. Those applications could include on-skin computers, soft robotics, and brain-machine interfaces. But, conventional electronics are made of rigid materials such as silicon.

Open-source, Flexible, and Fast Enough

Pragmatic sought to create a flexible microchip that cost significantly less to make than a silicon processor. The new device, named Flex-RV, is a 32-bit microprocessor based on the metal-oxide semiconductor indium gallium zinc oxide (IGZO).

Attempts to create flexible devices from silicon require special packaging for the brittle microchips to protect them from the mechanical stresses of bending and stretching. In contrast, pliable thin-film transistors made from IGZO can be made directly at low temperatures onto flexible plastics, leading to lower costs.

The new microchip is based on the RISC-V instruction set. (RISC stands for reduced instruction set computer.) First introduced in 2010, RISC-V aims to enable smaller, lower-power, better-performing processors by slimming down the core set of instructions they can execute.

“Our end goal is to democratize computing by developing a license-free microprocessor,” Ozer says.

RISC-V’s is both free and open-source, letting chip designer dodge the costly licensing fees associated with proprietary architectures such as x86 and Arm. In addition, proprietary architectures offer limited opportunities to customize them, as adding new instructions is generally restricted. In contrast, RISC-V encourages such changes.

A bent Flex-RV microprocessor runs a program to print ‘Hello World’. Pragmatic Semiconductor

“We chose the Serv designed by Olof Kindgren... as the open source 32-bit RISC-V CPU when we designed Flex-RV,” Ozer says. “Serv is the smallest RISC-V processor in the open-source community.”

Other processors have been built using flexible semiconductors, such as Pragmatic’s 32-bit PlasticARM and an ultracheap microcontroller designed by engineers in Illinois. Unlike these earlier devices, Flex-RV is programmable and can run compiled programs written in high-level languages such as C. In addition, the open-source nature of RISC-V also let the researchers equip Flex-RV with a programmable machine learning hardware accelerator, enabling artificial intelligence applications.

Each Flex-RV microprocessor has a 17.5 square millimeter core and roughly 12,600 logic gates. The research team found Flex-RV could run as fast as 60 kilohertz while consuming less than 6 milliwatts of power.

All previous flexible non-silicon microprocessors were tested solely on the wafers they were made on. In contrast, Flex-RV was tested on flexible printed circuit boards, which let the researchers see how well it operated when flexed. The Pragmatic team found that Flex-RV could still execute programs correctly when bent to a curve with a radius of 3 millimeters. Performance varied between a 4.3 percent slowdown to a 2.3 percent speedup depending on the way it was bent. “Further research is needed to understand how bending conditions such as direction, orientation and angle impact performance at macro and micro scales,” Ozer says.

Silicon microchips can run at gigahertz speeds, much faster than Flex-RV, but that shouldn’t be a problem, according to Ozer. “Many sensors—for example, temperature, pressure, odor, humidity, pH, and so on—in the flexible electronics world typically operate very slowly at hertz or kilohertz regimes,” he says. “These sensors are used in smart packaging, labels and wearable healthcare electronics, which are the emerging applications for which flexible microprocessors will be useful. Running the microprocessor at 60 kHz would be more than enough to meet the requirements of these applications.”

Ozer and his team suggest each Flex-RV might cost less than a dollar. Although Ozer did not want to say how much less than a dollar it might cost, he says they are confident such low costs are possible “thanks to low-cost flexible chip fabrication technology by Pragmatic and a license-free RISC-V technology.”

The scientists detailed their findings online 25 September in the journal Nature.

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Get a sneak peak at the industry�s smallest and smartest bone conduction sound processor. Now the first hearing implant with Made for iPhone� technology.

If we talk about the frequency, the TDS return may be revised multiple times, which allows taxpayers to make corrections as and when needed. However, it is advisable to avoid excessive revisions to prevent complexities in record-keeping.

We filed Form 27Q for TDS on a foreign company who doesn't have a PAN in India. Hence we wrote PANNOTAVBL. Deduction was made as per rate in DTAA. Hence higher rate was not required. Now we have received a notice saying that there is an error in the return as PAN number is not mentioned for 1 ded

My ITR3 for AY 2023-24 has been processed by CPC under OLD REGIME without recognizing the Taxation Option exercised undersection 115BAC for NEW REGIME by filing FORM 10IE during AY 2022-23 on 01-Jun-2022, which has been CONTINUED for AY 2023-24, as EVIDENT in the ITR3 filed for this Assessment Year. I have also Registered my grievance in this regard in the e-portal of the IT Department and have sought RECTIFICATION FIVE TIMES under Section 154 but have got the same RECTIFICATION ORDER repeating the same MISTAKE with processing done under OLD REGIME with TAX DEMAND of Rs.87,000. (Similar thing had happened in AY 2022-23 but it was corrected by RECTIFICATION). I am in continuous correspondence through email and written communication several times with the Department, including grievances raised on E-PORTAL, but the issue remains UNRESOLVED. I have also registered my grievance in this regard in CPGRAMS Portal of GOI which is pending.
I request advice on further course of action to resolve the issue including as to whether i can file an Appeal under Section 264 .
G S Prakash