A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

A microcapsule comprising A) a core containing a hydrophobic liquid or wax, B) a polymeric shell comprising a) a polymer formed from a monomer mixture containing: i) 1 to 95% by weight of a hydrophobic mono functional ethylenically unsaturated monomer, ii) 5 to 99% by weight of a polyfunctional ethylenically unsaturated monomer, and iii) 0 to 60% by weight of other mono functional monomer, and b) a further hydrophobic polymer which is insoluble in the hydrophobic liquid or wax. The invention includes a process for the manufacture of particles and the use of particles in articles, such as fabrics, and coating compositions, especially for textiles.

The present invention relates to a process for preparing cyclic compounds having at least eight carbon atoms and at least one keto group, to the cyclic compounds obtained by this process and to the use thereof, in particular as fragrance or for providing a fragrance.

A method for isolating 2,2,4,4-tetramethyl-1,3-cyclobutanediol (TMCD) solids from an isolated feed slurry formed in a TMCD process comprising TMCD, a liquid phase, and impurities by (a) treating the isolated feed slurry in a product isolation zone to produce an isolated TMCD product wet cake, a mother liquor, and impurities; wherein the product isolation zone can comprise at least one rotary pressure drum filter.

The present invention produces ethanol in a reactor that comprises a catalyst composition and a feed stream comprising acetic acid and a recycled liquid stream comprising ethyl acetate. The catalyst composition comprises a first catalyst comprising platinum, cobalt, and/or tin and a second catalyst comprising copper. The crude ethanol product may be separated and ethanol recovered.

The present invention is directed to processes for the recovery of ethanol from a crude ethanol product obtained from the hydrogenation of acetic acid using a low energy process. The crude ethanol product is separated in one or more columns. At least one of the columns is operated at a controlled pressure to enhance separation of ethanol and organics. In one embodiment, there are at least two columns that operate at controlled pressures.

The present invention is directed to processes for recovering ethanol obtained from the hydrogenation of acetic acid. Acetic acid is hydrogenated in the presence of a catalyst in a hydrogenation reactor to form a crude ethanol product. The crude ethanol product is separated in one or more columns to recover ethanol. In some embodiments, less than 10 wt. % ethanol is recycled to the hydrogenation reactor.

A process for selective formation of ethanol from acetic acid by hydrogenating acetic acid in the presence of a catalyst comprises a first metal on an acidic support. The acidic support may comprise an acidic support material or may comprise an support having an acidic support modifier. The catalyst may be used alone to produced ethanol via hydrogenation or in combination with another catalyst. In addition, the crude ethanol product is separated to obtain ethanol.

Disclosed herein are processes for alcohol production by reducing an esterification product, such as ethyl acetate. The processes comprise esterifying acetic acid and an alcohol such as ethanol to produce an esterification product. The esterification product may be recovered using an extractive separation. The esterification product is reduced with hydrogen in the presence of a catalyst to obtain a crude reaction mixture comprising the alcohol, in particular ethanol, which may be separated from the crude reaction mixture.

A catalyst composition for converting ethanol to higher alcohols, such as butanol, is disclosed. The catalyst composition comprises at least one alkali metal, at least a second metal and a support. The second metal is selected from the group consisting of palladium, platinum, copper, nickel, and cobalt. The support is selected from the group consisting of Al2O3, ZrO2, MgO, TiO2, zeolite, ZnO, and a mixture thereof.

A para-methoxy protected benzaldehyde useful in preparation of treprostinil, and of formula: (Formula (1)) is prepared by subjecting to Claisen re-arrangement a substituted benzaldehyde of formula (1a): (Formula (Ia)) to form the m-hydroxy-substituted benzaldehyde of formula (1b): (Formula (Ib)) and then reacting compound (1b) with a p-methoxybenzyl (PMB) compound to form a PMB-substituted benzaldehyde of formula (1).

The present invention provides an easy process for purifying phenol by separating carbonyl compounds through selective hydrogenation of the compounds to the corresponding alcohols then distillation. The phenol purification process of the present invention comprises bringing phenol into contact with a copper-based catalyst in the presence of hydrogen to convert carbonyl compounds contained in the phenol to the corresponding alcohol compounds, and separating the alcohol compounds and phenol by distillation.

In a process for producing phenol, cyclohexylbenzene is contacted with oxygen in the presence of an oxidation catalyst comprising a cyclic imide under oxidation conditions effective to produce a product comprising cyclohexylbenzene hydroperoxide and unreacted cyclic imide catalyst. At least a portion of the product is contacted with a cleavage catalyst under conditions effective to convert at least a portion of the cyclohexylbenzene hydroperoxide into a second product comprising further unreacted cyclic imide catalyst, phenol, and cyclohexanone. A portion of the further unreacted cyclic imide catalyst may then be removed from the second product and optionally recycled back to the oxidation step.

Disclosed are processes relating to the production of polyglycerol ethers of fatty alcohols, in particular, one step process using fatty alcohol and glycerine to synthesize polyglycerides of fatty alcohols will provide a 100% renewable surfactant that is cost effective efficient and CMR free. The synthetic methods mentioned in prior art uses hazardous chemicals as glycidyl ethers, epichlorohydrin that are listed as CMR and known carcinogens and hazardous to handle.

A polyether polyol based on renewable materials is obtained by the in situ production of a polyether from a hydroxyl group-containing vegetable oil, at least one alkylene oxide and a low molecular weight polyol having at least 2 hydroxyl groups. The polyol is produced by introducing the hydroxyl group-containing vegetable oil, a catalyst and an alkylene oxide to a reactor and initiating the alkoxylation reaction. After the alkoxylation reaction has begun but before the reaction has been 20% completed, the low molecular weight polyol having at least 2 hydroxyl groups is continuously introduced into the reactor. After the in situ made polyether polyol product having the desired molecular weight has been formed, the in situ made polyether polyol is removed from the reactor. These polyether polyols are particularly suitable for the production of flexible polyurethane foams.

In a process for the dehydrogenation of dehydrogenatable hydrocarbons, a feed comprising dehydrogenatable hydrocarbons is contacted with a catalyst comprising a support and a dehydrogenation component under dehydrogenation conditions effective to convert at least a portion of the dehydrogenatable hydrocarbons in the feed. The catalyst is produced by a method comprising treating the support with a liquid composition comprising the dehydrogenation component or a precursor thereof and at least one organic dispersant selected from an amino alcohol and an amino acid.

Processes are disclosed for the conversion of a carbohydrate source to hexamethylenediamine (HMDA) and to intermediates useful for the production of hexamethylenediamine and other industrial chemicals. HMDA is produced by direct reduction of a furfural substrate to 1,6-hexanediol in the presence of hydrogen and a heterogeneous reduction catalyst comprising Pt or by indirect reduction of a furfural substrate to 1,6-hexanediol wherein 1,2,6-hexanetriol is produced by reduction of the furfural substrate in the presence of hydrogen and a catalyst comprising Pt and 1,2,6-hexanediol is then converted by hydrogenation in the presence of a catalyst comprising Pt to 1,6 hexanediol, each process then proceeding to the production of HMDA by known routes, such as amination of the 1,6 hexanediol. Catalysts useful for the direct and indirect production of 1,6-hexanediol are also disclosed.

The present invention relates to a process for heat integration in the preparation of saturated C3-C20-alcohols, in which a hydrogenation feed comprising at least one C3-C20-aldehyde is hydrogenated in the presence of a hydrogen-comprising gas in a hydrogenation zone and a discharge is taken off from the hydrogenation zone and subjected to distillation in at least one distillation column to give a fraction enriched in saturated C3-C20-alcohols.

A filtration method is disclosed for recovering purified polyether polyol comprising the steps of providing an aqueous solution of a polyether polyol containing an alkali metal catalyst residual formed from a transesterification process utilizing an alkali metal catalyst, contacting the aqueous solution with a stoichiometric excess of magnesium sulfate, magnesium sulfite or a combination thereof to form a second aqueous solution, wherein said stoichiometric excess is based on the amount of said alkali metal catalyst residual. Water is removed from the second aqueous solution at a temperature above a set limit of said polyether polyol to produce a dehydrated slurry containing a polyether polyol phase substantially free of residual alkali metal and a precipitated solid phase comprising sulfate and/or sulfite salts of the alkali metal catalyst, magnesium hydroxide, and excess magnesium sulfate and/or sulfite, wherein the particle size distribution of said precipitated solid phase is controlled to minimize the amount of particles therein that are smaller than 3 microns. The dehydrated slurry is then passed through a filtration system to separate the polyether polyol phase from the precipitated solid phase.

An improved method for recovering a purified polyether polyol comprising the steps of providing an aqueous solution of a polyether polyol containing an alkali metal catalyst residual formed from a transesterification process, contacting the aqueous solution with a stoichiometric excess of magnesium sulfate to form a second aqueous solution, removing water from said second aqueous solution at a temperature above the melt temperature of said polyether polyol to produce a dehydrated slurry containing a molten polyether polyol phase essentially free of residual alkali metal and a precipitated solid phase comprising sulfate and/or sulfite salts of the alkali metal catalyst, magnesium hydroxide, and excess magnesium sulfate and/or sulfide, passing the dehydrated slurry of through a filtration system comprising a filtration press to separate the molten polyether polyol phase from the precipitated solid phase, wherein the filtration press is treated with a filter aid that is essentially free of transition metal oxide content, separating the molten polyether polyol phase substantially free of water, residual alkali metal catalyst and transition metal contaminants from the precipitated solid phase and recovering polyether polyol from the separated polyether polyol phase.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

A process for preparing a particle defoamer. The particle defoamer of 55%-75% of a carrier, 15%-35% of a silicone emulsion, 3%-10% of a texturing agent and 2%-10% of a solvent, based on the total weight of the particle defoamer; the process for preparing the particle defoamer is: (1)first adding a carrier A1 into a mixer, and then adding thereto a silicone emulsion B1, and stirring uniformly; (2)adding a carrier component A2 to the mixture obtained in (1), and stirring uniformly; (3)adding a silicone emulsion B2 to the mixture obtained in (2), and, after uniformly stirring, adding the solvent thereto and stirring uniformly; and (4)pelleting and drying by baking the mixture obtained in(3), so as to produce the product.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

A ceramic substrate includes a substrate body formed of ceramic and having a pair of surfaces each assuming a rectangular shape as viewed in plane, and a metallization layer formed on the surface of the substrate body and adapted to braze a metal frame thereon. A composite material layer is disposed between the surface of the substrate body and the metallization layer and is formed such that a ceramic portion, a metal portion 10m formed of a metal similar to a metal component of the metallization layer or a metal which, together with a metal component of the metallization layer, forms an all proportional solid solution, and a glass portion exist together. The thickness of the composite material layer is thinner than that of the metallization layer. A plating layer is deposited on the surface of the metallization layer.

Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.

An image processing apparatus including: image processor which processes broadcasting signal, to display image based on processed broadcasting signal; communication unit which is connected to a server; a voice input unit which receives a user's speech; a voice processor which processes a performance of a preset corresponding operation according to a voice command corresponding to the speech; and a controller which processes the voice command corresponding to the speech through one of the voice processor and the server if the speech is input through the voice input unit. If the voice command includes a keyword relating to a call sign of a broadcasting channel, the controller controls one of the voice processor and the server to select a recommended call sign corresponding to the keyword according to a predetermined selection condition, and performs a corresponding operation under the voice command with respect to the broadcasting channel of the recommended call sign.

An apparatus for processing an audio signal and method thereof are disclosed. The present invention includes receiving a downmix signal and side information; extracting control restriction information from the side information; receiving control information for controlling gain or panning at least one object signal; generating at least one of first multi-channel information and first downmix processing information based on the control information and object information, without using the control restriction information; and, generating an output signal by applying the at least one of the first multichannel information and the first downmix processing information to the downmix signal, wherein the control restriction information relates to a parameter indicating limiting degree of the control information.