A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.

An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A signal transfer circuit may include a pass gate coupled between first and second nodes; and a control unit suitable for controlling the pass gate to prevent a current flowing from the second node to the first node during turn-on of the pass gate.

A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

A duty cycle correction circuit may include: a phase mixing section capable of mixing a first integrated signal generated by integrating a positive clock signal, with a first compensation signal generated by differentiating and integrating the positive clock signal and a negative clock signal, respectively, to generate a first phase-mixed signal, and mixing a second integrated signal generated by integrating the negative clock signal, with a second compensation signal generated by integrating and differentiating the positive clock signal and the negative clock signal, respectively, to generate a second phase-mixed signal; and a noise removal section capable of receiving and removing a common mode noise between the first phase-mixed signal and the second phase-mixed signal by adjusting a cross-point therebetween, and outputting first and second duty-corrected clock signals.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

An example circuit includes: a slew rate driver configured to provide an output voltage; a first voltage provider configured to provide a first input voltage to the slew rate driver in response to the output voltage being within a first range; and a second voltage provider configured to provide a second input voltage to the slew rate driver in response to the output voltage being within a second range. The slew rate driver is further configured to change the output voltage based at least in part on the first input voltage or the second input voltage.

A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

To provide a clock selection circuit capable of reducing clock omission generated when switching from a state of being synchronized with a first clock to a second clock. The clock selection circuit is equipped with a clock detection circuit which detects a first clock to output a detected signal, a switch which outputs the first clock when the detected signal is at a first level and outputs a second clock when the detected signal is at a second level different from the first level, and a one-shot circuit which outputs a one-shot pulse in response to switching of the detected signal from the first level to the second level. The output of the switch and the output of the one-shot circuit are added to be outputted as an output clock.

A clock-signal generator circuit, for generating an output clock signal starting from an input clock signal, includes: a monostable stage having a clock input configured to receive the input clock signal, a control input configured to receive a control signal, and an output configured to supply the output clock signal having a duty cycle variable as a function of the control signal; and a feedback loop, operatively coupled to the monostable stage for generating the control signal as a function of a detected value, and of a desired value, of the duty cycle of the output clock signal.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A half-bridge circuit comprises a high supply contact and a low supply contact. A half-bridge output contact is connectable to drive a load and has a high-side between the high supply contact and the half-bridge output contact and a low-side between the half-bridge output contact and the low supply contact. A high-side bidirectional vertical power transistor at the high-side has a source connected to the high supply contact, and a low-side bidirectional vertical power transistor at the low-side, transistor has a source connected to the low supply contact. The high-side bidirectional vertical power transistor and low-side bidirectional vertical power transistor are connected in cascode and share a common drain connected to the half-bridge output contact, and are controllable to alternatingly allow a current flow from the high supply contact to the half-bridge output contact or from the half-bridge output contact to the low supply contact.

A device for controlling a first control gate transistor, including: a second transistor and a third transistor series-connected between a first and a second terminals of application of a power supply voltage, the junction point of these transistors being connected to the gate of the first transistor; a terminal of application of a digital control signal; a circuit for generating an analog signal according to variations of the power supply voltage; and for each of the second and third transistors, a circuit of selection of a control signal of the first transistor representative of said digital signal or of said analog signal.

A driving circuit includes a first switching element operating in a turned-on state or a turned-off state depending on a control voltage; a second switching element operating complementarily to the first switching element depending on the control voltage; a constant voltage circuit unit turning on depending on a source-gate voltage of the first switching element to maintain a constant voltage; a current adjusting circuit operating in a turned-on state or a turned-off state depending on the control voltage, and adjusting an operating current flowing to a ground depending on a current control signal in the turned-on state of the current adjusting circuit; a current control circuit controlling the operating current by providing the current control signal to the current adjusting circuit in a turned-on state of the constant voltage circuit unit; and a signal transfer circuit providing the control voltage to a gate of the second switching element.

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

A printhead cartridge cradle is provided having a frame, a printed circuit board pivotally supported by the frame, a cover pivotally supported by the frame to pivot between a closed position at which a printhead cartridge is secured within the frame and the printed circuit board is pivoted to connect control circuitry on the printed circuit board with a controller of the secured cartridge and an open position at which access for the cartridge with the frame is provided and the printed circuit board is pivoted to disconnect the control circuitry and controller, and a motor operatively connected to a maintenance gear and actuator arrangement and a wiper gear and actuator arrangement for maintaining and wiping a printhead of the secured cartridge under control of the connected control circuitry.

A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

There are provided an optical disk and an optical disk recording method which are capable of stable data reading in a case where a recording linear density is increased. According to an optical disk of the present disclosure, a run-in pattern recorded in a groove track and a run-in pattern recorded in a land track are made different patterns so that no great change is caused in the amplitude of an acquired signal due to interference between adjacent recording patterns, and thus, data may be stably read.

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.

An integrated reformer and combustion apparatus for use in a fuel cell system comprises at least one reformer plate (3) at which in use a reforming reaction can take place and at least one combustion plate (1) at which in use a combustion reaction can take place. The plates are arranged in a stack such that the reformer plates (3) and combustion plates (1) are interspersed. The apparatus is arranged such that in use a reforming reaction and a combustion reaction can take place simultaneously, the combustion reaction providing heat for the reforming reaction. A further fluid circuit (19, 29) may be provided in thermal communication with at least one of the reformer unit and the combustion unit so as to allow the temperature of that unit to be controlled.

A printed circuit board includes a substrate including a surface layer and a first ground layer; a high-frequency signal generation part provided in the surface layer of the substrate; at least one high-frequency signal connector mounting portion formed in the surface layer of the substrate; at least one high-frequency signal line formed in the surface layer of the substrate, and extend from the high-frequency signal generation part to the at least one high-frequency signal connector mounting portion; and at least one high-frequency signal connector disposed in the at least one high-frequency signal connector mounting portion, wherein an end of the first ground layer is exposed to a side surface of the substrate, and when the high-frequency signal connector is disposed in the at least one high-frequency signal connector mounting portion, a ground of the high-frequency signal connector is in contact with the end of the first ground layer.

A battery connector is provided which is used to electrically connect a button battery. The connector has an insulating housing and positive and negative terminals. The housing has a limiting space for receiving and fixing the battery. The positive terminal has a positive contact portion which extends into the space and a first tail portion which maintains an electrical connection with a circuit board. The negative terminal has a negative contact portion which extends into the space so as to contact a negative electrode on a bottom surface of the battery, a second tail portion which maintains an electrical connection with the board, and a connection portion which is brought to move by the negative contact portion so as to electrically connect with the board when the battery is received in the space. The battery connector can be provided as part of a circuit module having an indicating member.

An arrangement for an electronic device is disclosed. A plurality of electrically conductive pins is positioned in respective vias of the circuit carrier, the pins extend from a first face of the circuit carrier to a contact end in order to electrically contact one or more components. The arrangement is equipped with an electrically insulating layer on a circuit carrier face, which is the first or a second face, in the region of the pin, the insulating layer having a prefabricated element which is positioned on the face of the circuit carrier. A portion of each pin, the portion being arranged adjacently to the respective via on the face, is surrounded by the material of the insulating layer in a continuously lateral manner.

An electronic device including a signal generating circuit and a movable sensing circuit is provided. The signal generating circuit generates a sensory signal through a signal source. The movable sensing circuit generates a feedback signal in response to a detection signal from the signal generating circuit, and transmits the feedback signal to the signal generating circuit. The signal generating circuit obtains a first distance value between the signal source and the movable sensing circuit based on the feedback signal, and adjusts the intensity of the sensory signal according to the first distance value.

A testing device for FMCW radar includes an input for receiving a chirp signal generated by the radar. An IQ down-converter coupled to the input down-converts the chirp signal. A digitizer extracts digitized IQ signals from the down-converted chirp signal. A processor coupled to the digitizer determines at least one of frequency linearity and phase noise of the chirp signal.

In a piezoelectric ejector assembly, a piezoelectric actuator is attached to an ejector mechanism, while a drive signal generator and a controller are coupled to the actuator. The drive signal generator is configured to generate a drive signal for driving the actuator to oscillate the ejector assembly. The controller is configured to control the drive signal generator to drive the actuator at a resonant frequency of the ejector assembly, and an auto-tuning circuit is provided to define the optimum drive signal frequency.

In nanoimprinting processes, photo-cured products often separate from the substrate and stick to the mold due to insufficient adhesion between the photo-cured product and the substrate. This causes a defect of pattern separation. An adhesion layer composition used for forming an adhesion layer between a substrate and a photocurable composition includes a compound (A) having at least two functional groups, and a solvent (B). The functional groups include at least one functional group capable of being bound to the substrate, selected from the group consisting of hydroxy, carboxy, thiol, amino, epoxy, and (blocked) isocyanate, and at least one hydrogen donating group as a functional group capable of being bound to the photocurable composition.

A switch-scanning circuit includes a chip and switching units. The chip includes pins having an output operation mode and an input operation mode, and a processing unit. The processing unit sets one of the pins as an input pin and the rest of the pins as output pins sequentially according to a clock signal, uses a scan signal to provide different voltages to the output pins, and then determines states of button switches according to a voltage of the input pin. The switching unit includes a power source resistance, switches and resistors. A first terminal and a second terminal of the power source resistance are electrically connected to a power source and a first pin respectively. The resistors have terminals electrically connected the first pin and terminals of the switches. The other terminals of the switches are connected to the pins other than the first pin.

A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register analog-to-digital converter (SAR ADC). In the method, whether to regulate a binary weight corresponding to each of digital bits is determined according to the number of completed comparison cycles to provide a first coding sequence. The first coding sequence is directly compensated according to uncompleted comparison cycles to provide a correct digital output code.

A digital-to-analog converter (DAC) and a high-voltage tolerance circuit are provided. The DAC includes a high-voltage tolerance circuit. The high-voltage tolerance circuit is configured to generate a reference voltage, and select the reference voltage or a first power-source voltage to control the node voltage of each branch of an operational amplifier circuit of the high-voltage tolerance circuit according the logical signal level of an input signal.

Continuous-time analog-to-digital converters (ADCs) such as continuous-time delta-sigma ADCs and continuous-time pipeline ADCs, has input resistor structure at the input. The input resistor structure is typically tunable, and the tunability is usually provided by metal-oxide semiconductor field effect transistor (MOSFET) switches. Core MOSFETs, which has a terminal-to-terminal voltage

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.

A circuit board includes a substantially planar component carrier and a microstrip which is applied to a surface of the component carrier. The microstrip extends towards a connection transition which is arranged on a lateral edge of the component carrier. A waveguide portion of an antenna element which is produced by a 3D printing process is coupled to this connection transition.

A circuit board is provided and the circuit board is used for being attached to a matching board. The circuit board includes a first circuit pattern and an attaching state inspection area, and the attaching state inspection area further includes a third circuit pattern. A liquid crystal display device is further provided, including the circuit board and the matching board, the matching board includes a second circuit pattern matching the circuit board. It is more accurate to judge the attaching state between the circuit board and the matching board by detecting the deformation state of the conductive particles in vacant areas at different locations after the circuit board is attached to the matching board.

According to one embodiment, a laminated film includes a first adhesive layer, a first insulating layer which faces the first adhesive layer, a first metal layer which is located between the first adhesive layer and the first insulating layer, and a first porous layer which is located between the first adhesive layer and the first insulating layer and faces the first metal layer.

Disclosed are a circuit fault detection system and method for a circuit fault detection. A circuit fault detection system includes: a detection circuit including a diode, a first resistor, and a second resistor, which are positioned between an applied voltage source and a top of a detection target circuit in series, and a third resistor and a fourth resistor, which are positioned between the detection target circuit and a ground in series, an input unit including a first input terminal configured to receive a voltage measured between the first resistor and the second resistor as an input, and a second input terminal configured to receive a voltage measured between the third resistor and the fourth resistor as an input, a controller configured to detect a failure in the detection target circuit and in an operation of the detection target circuit based on values of the voltages detected by the input unit; and a display unit configured to provide a warning to a user when the failure is detected.

A system can include at least one circuit breaker. The system can also include a prognostic and health monitoring (PHM) system. The PHM system can include at least one measuring device that measures at least one parameter associated with the at least one circuit breaker. The PHM system can also include a controller that receives measurements made by the at least one measuring device and analyzes the measurements to evaluate a performance of the at least one circuit breaker. The measurements can be made while the at least one circuit breaker is in service.

Technologies for controlling degradation of a sensor mote including detecting a trigger event and initiating degradation of at least a portion of the sensor mote in response to the trigger event. The trigger event may be embodied as any type of event detectable by the sensor mote such as a trigger signal, particular sensed data, expiration of a reference time period, completion of a task, and so forth. The sensor mote may imitate the degradation by, for example, controlling a valve to release a chemical stored in the sensor mote or allow a substance into the sensor mote.

An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier with a feedback capacitor; a switch that drives charging and discharging of the feedback capacitor; an additional capacitor; and a coupling circuit, which alternatively connects the additional capacitor in parallel to the feedback capacitor or else decouples the additional capacitor from the feedback capacitor. The switch opens at a first instant, where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor from the feedback capacitor in a way synchronous with a second instant, where the first component assumes a second zero value.

The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive wirings and electro-conductive contact sheet group both laid on the surface of the substrate, where the substrate is overlaid with solder resist, and the solder resist has no contact with the electro-conductive contact sheet group.

An optical circuit includes solid state photonics. The optical circuit includes a phased array of solid state waveguides that perform beamsteering on an optical signal. The optical circuit includes a modulator to modulate a bit sequence onto the carrier frequency of the optical signal, and the beamsteered signal includes the modulated bit sequence. The optical circuit includes a photodetector to detect a reflection of the beamsteered optical signal. The optical circuit autocorrelates the reflection signal with the bit sequence to generate a processed signal.

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

In an example arrangement an apparatus includes a semiconductor substrate having a front side surface including circuitry and a backside surface opposing the front side surface; a plurality of metal conductors formed over a front side surface of the semiconductor substrate; at least one cavity opening etched in a backside surface of the semiconductor substrate; and a radiator formed in a portion of the metal conductors and configured to radiate signals through the cavity opening in the backside surface. Methods and additional apparatus arrangements are also disclosed.

An electric circuit device connecting first and second external elements, the electric circuit device including: a first electronic component; a first bus bar electrically connected to the first electronic component; a second bus bar electrically connected to the electronic component and overlapped with the first bus bar in a direction perpendicular to main surfaces of the first and second bus bars; a first external terminal electrically connecting the first bus bar to the first external element; a second external terminal electrically connecting the second bus bar to the second external element; a first region in the first external terminal electrically coupled to the first external element; and a second region in the second external terminal electrically coupled to the second external element, and at least partially overlapped with the first region in the direction.

A ground fault circuit interrupter (GFCI) breaker testing system can include an enclosure having at least one wall that forms a cavity. The system can also include at least one GFCI breaker disposed within the cavity. The system can further include a sensing circuit assembly having at least one switch, where the at least one switch is electrically coupled to the at least one GFCI breaker. The system can also include a user interface assembly disposed, at least in part, outside the cavity, where the user interface assembly is coupled to the sensing circuit assembly, where the user interface assembly instructs the at least one switch to test the at least one GFCI breaker.