A bootstrap assist circuit and a startup circuit comprising a voltage controlled switch and a startup ramp voltage generator connected to the voltage controlled switch that will control a high side switch, a dimming interface or an enable/disable input function. Said system is used to provide a bootstrap technique to continuously switch a floating high side switch (MOSFET) by continuously charging a capacitor and then “level shifting” said capacitor voltage across the gate and source of the said high side switch to turn the switch on.

A reference voltage circuit for generating a reference voltage to be referred when a pixel signal is digitally converted, includes ramp voltage generating means for generating a ramp voltage which drops from a predetermined initial voltage at a certain gradient, a transistor for forming, together with the ramp voltage generating means, a current mirror circuit, and gain change means for changing a current value of a current flowing from a predetermined power supply via the transistor to change the gradient of the ramp voltage generated by the ramp voltage generating means.

A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.

A power-supply circuit for a DC appliance includes an input unit including a first terminal and a second terminal so as to receive a DC current, an output unit including a third terminal to output the DC current entered by the input unit and a fourth terminal, a connection unit including a first conductive line and a second conductive line so as to interconnect the input unit and the output unit, a rectifier unit including first to fourth diodes coupled as a bridge diode format so as to rectify the input DC current in a predetermined direction, an inductor unit that is connected in series to the rectifier unit in such a manner that the input DC current is gradually increased from an abrupt change time point of the DC current, and a condenser unit that is connected in series to the inductor unit.

A power control circuit for a power supply system including a control unit, a driving circuit and a power supply unit is disclosed. The power control circuit includes a current detection unit, a voltage detection unit and a power detection unit. The current detection unit is used for detecting a current signal. The voltage detection unit is used for detecting a voltage signal. The power detection unit is connected with the current detection unit, the voltage detection unit and the control unit for acquiring a power signal according to the current signal and voltage signal. By comparing an adjustable power reference signal with the power signal, the control unit issues a control signal to the driving circuit. In response to the control signal, the power supply unit is driven by the driving circuit to output an adjusted power to the load according to the adjustable power reference signal.

A mode controller shifts, along with increase in an electric power in first and second of chopper circuits and, operation modes of the first and the second of the chopper circuits from a first mode to a third mode via a second mode. An operation controller causes, in the first mode, the first of chopper circuit to perform an chopping operation, and the second of chopper circuit to suspend the chopping operation, in the second mode, causes the first and the second of chopper circuits to alternatively perform the chopping operations, and in the third mode causes both of the first and the second of chopper circuits to perform the chopping operations.

A train system that includes a plurality of train units including a first train unit and second train unit coupled together. Each first and second train unit includes a controller configured to detect a change in train configuration of the train units, and comprising a plurality of inputs; train integrity signal lines spanning each train unit and coupled with the controller at the plurality of inputs and configured to transmit signals between a front end and a rear end of the train system, the signals indicating a status of train integrity of the train system; and a plurality of relays in communication with the controller, and configured to indicate a coupling or non-coupling status of each train unit.

A sequential monitoring system is for an interlocking logic system and a track circuit system including a plurality of track circuits. The sequential monitoring system includes an interface between the interlocking logic system and the track circuit system; and a processor structured to monitor a state of each of the track circuits, validate a sequence of state changes of the track circuits, and interrupt and correct invalid track circuit state indications between the track circuit system and the interlocking logic system. The interface normally passes inputs from the track circuit system to outputs to the interlocking logic system. When an out of sequence event occurs, the processor applies a quarantine to a minimum of three of the track circuits in a quarantined area, thereby inhibiting use of an unoccupied track circuit in the quarantined area.

A device and method for manufacturing integrated circuit packaging using a mold plunger with position compensation in a manufacturing setting. In an embodiment, a compensating mold plunger, which may be used during the manufacture of an integrated circuit package, engages a die set on a carrier and within a bushing. This may be done to inject a mold compound on top of the die/carrier. If the bushing that is housing the die/carrier tandem is misaligned with the plunger in any lateral direction, the amount of pressure may be compromised. A compensating mold plunger includes a flexible portion that allows for the head of the plunger to properly engage the die/carrier despite any possible misalignments. Further, different die/carrier combinations may also be used with a compensating mold plunger because the pressure and force applied may be uniform inside a bushing despite the contents of the bushing.

An equalizer circuit includes an phase-to-phase connectors including an phase-to-phase capacitor and four phase-to-phase switches, four output buffers, and control signal generation circuitry. One terminal of each phase-to-phase switches is connected to one of four connection paths on which four conversion signals being different in phase by 90° are input. The other one terminal of each phase-to-phase switches is connected to the phase-to-phase capacitor. Each output buffer is connected to one of the four connection paths and outputs an output signal. The control signal generation circuitry outputs control signals to control turning-on/off of the respective four phase-to-phase switches. A closing of the first, second, third, and fourth phase-to-phase switches are started from any one of phase-to-phase switches in one of a first ascending circulation and a first descending circulation based on the 4-phase control signals.

A half-rate clock data recovery circuit includes: a voltage-controlled oscillator (VCO) for generating a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit for dynamically controlling the VCO to adjust the phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit for instructing the adjusting circuit to respectively utilize different control value combinations to control the VCO in the multiple test periods, and for recording multiple recovered-signal quality indicators respectively corresponding to the multiple test periods. Afterwards, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to the best quality indicator among the multiple recovered-signal quality indicators to control the VCO.

An electronic lock with power failure control circuit includes a lock mechanism having a latchbolt movable between extended and a retracted positions and an electrically powered lock actuator to lock and unlock the latchbolt. The power failure control circuit includes a microcontroller and the lock is connected to a primary power source and an auxiliary power source, preferably supercapacitors and charger that can be turned on by the microcontroller and off when the charger signals a full charge. A power monitor circuit detects low voltage on the primary power supply and sets a power failure interrupt causing the microcontroller to execute power failure instructions that control the actuator so that the lock is placed into a desired locked or unlocked final state during the power failure. upon detection of the return of good power, the system resets the lock.

An industrial fluid circulating system having at least one fluid circulation circuit, includes a plurality of pumps connected in parallel to circulate the fluid through each of the fluid circulation circuit, a separate motor driving each pump, a load detector to sense operating loads on the system and each circuit, and a speed control to vary the speed of each motor to thereby vary the pumping capacity of each pump in response to the detected load on the system, each pump of each respective circuit running simultaneously at a substantially similar speed or a predetermined equal reduced speed of the respective circuit or an almost equal reduced speed or a similar reduced speed.

A peripheral interface circuit and a peripheral memory system are provided. The peripheral interface circuit includes an interface sequencer, an input/output controller, a register unit and a data buffer. The interface sequencer receives requests from the input/output controller and accesses the peripheral memory in response to the requests. The data buffer is randomly accessed by address. If target data of the data access request exists in the data buffer, the input/output controller returns data from the data buffer in response to the request; if target data of the data access request does not exist in the data buffer, the input/output controller sends an interface request to the interface sequencer to access the peripheral memory and keeps a copy of at least the target data in the data buffer.

A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.

A fluid-dynamic circuit includes a source of a pressurized fluid; a distributor valve for distributing the pressurized fluid to transport lines; a feeding line for feeding the pressurized fluid, which is interposed between the source and the valve; a main user apparatus, which is reciprocatingly operated by an actuator that includes a slider sealably fitted in a sliding seat of a containing element divided thereby into a first chamber and a second chamber in opposite positions and having variable volumes; and second and third transport lines for the pressurized fluid, which are interposed between the distributor valve and the first and second chamber respectively, a first derived transport line being interposed between the valve and at least one of the second and third transport lines, and having a normally closed quick discharge device mounted thereto, whose opening is designed to be controlled by the actuator.

The present disclosure is directed to a refractory metal core for use in forming varying thickness microcircuits in turbine engine components, a process for forming the refractory metal core, and a process for forming the turbine engine components. The refractory metal core is used in the casting of a turbine engine component. The core is formed by a sheet of refractory metal material having a curved trailing edge portion integrally formed with a leading edge portion.

A device for processing a hydrocarbon resource may include a hydrocarbon processing container configured to receive the hydrocarbon resource therein and having a pair of opposing ends with an enlarged width medial portion therebetween. The device may also a spirally wound electrical conductor surrounding the hydrocarbon processing container, and a radio frequency (RF) circuit coupled to the spirally wound electrical conductor and configured to supply RF power to the hydrocarbon resource while tracking a load resonance of the RF circuit. The RF circuit may be configured to generate magnetic fields within the hydrocarbon processing container parallel with an axis thereof.

An integrated circuit includes a pulse generator to provide an excitation pulse to an output terminal and a comparator to receive a signal in response to the excitation pulse and for comparing the signal to a threshold to produce a comparator output signal corresponding to oscillations in the signal. The integrated circuit further includes a counter to count pulses in the comparator output signal and a discriminator circuit to compare a count value of the counter to a damping threshold and for providing an output signal having a first value when the count value is equal to or exceeds the damping threshold and otherwise having a second value.

A laundry drying unit includes a process air circuit and a component arranged in the process air circuit. Provided above the component is a washing tank for dispensing a cleaning fluid, with a flow of cleaning fluid dispensed from the washing tank to the component being controlled by a controllable valve. The valve can be controlled on the basis of an amount of cleaning fluid in the washing tank.

The present invention provides an OLED gate driving circuit structure, comprising an OLED panel, a gate charge/discharge driving circuit, a logic process unit and a source driving circuit; the gate charge/discharge driving circuit is located at one side of the OLED panel, and the gate charge/discharge driving circuit comprises a plurality of output ends, and each output end is electrically coupled to the logic process unit with one signal line; the logic process unit is located inside the OLED panel, and the logic process unit receives a scan signal transmitted by the gate charge/discharge driving circuit through the signal line, and converts the scan signal into a discharge scan signal and a charge scan signal to be provided to the OLED panel; the source driving circuit is coupled to the OLED panel, and provides a data signal to the OLED panel, and only one gate driving integrated circuit is utilized in the structure for achieving the charge and discharge procedures of the gate driving circuit to save the hardware cost and to simplify the panel layout circuit and to make the frame of the panel narrower.

A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.

A driver IC for driving a display panel, a display device and a method for driving the driver IC are provided. The driver IC is provided with N pins corresponding to N signal transmission lines of the display panel respectively. Each pin is connected to one corresponding signal transmission line through one transmission wire. The N pins include a first pin and a second pin. The transmission wires include a first transmission wire connected to the first pin and a second transmission wire connected to the second pin and having a length less than the first transmission wire. The driver IC includes a signal generation module configured to generate N driving signals. The N driving signals include a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin and having a current intensity less than the first driving signal.

A gate driving circuit in a display device includes a plurality of stages connected in cascade. An ith stage from among the plurality of stages includes a first output unit, a control unit, a pull-down unit, and an inverter unit. The first output unit includes a first output transistor including a first control electrode, a second control electrode overlapping with the first control electrode, an input electrode, and an output electrode. A signal outputted from an inverter unit of an i−1th stage is applied to the second control electrode.

A voltage regulation circuit is provided, including a reverse processing module for processing a first initial voltage of a common voltage generating module so as to obtain a reverse voltage of AC voltage; and an integration module for regulating the first initial voltage according to the reverse voltage of the AC voltage so as to make a liquid crystal drive voltage equal to a preset value. The liquid crystal drive voltage is a difference value of between a second initial voltage and the first initial voltage which is regulated.

A GOA circuit located in a display panel is disclosed. The GOA circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a first boost thin film transistor, a second boost thin film transistor, a boost capacitor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film transistor. Through the first boost thin film transistor, the second boost thin film transistor, and the boost capacitor, a voltage level of a gate output signal outputted by a gate of the second thin film transistor is lifted.

A touch drive circuit and a driving method therefor, an array substrate and a touch display apparatus relate to a field of display. The driving method includes: during touch scanning time period in one frame, by each of output control unit (2), receiving a touch enable signal, a common voltage signal and a touch scanning signal, and receiving an output signal of an shift register unit connected with the output control unit; and outputting, by each of the output control units, the touch scanning signal to a touch drive electrode connected with the touch control unit in a first time period according to the touch enable signal and the output signal of the shift register unit connected with the output control unit, wherein the first time period is scanning time allocated to the touch drive electrode in one frame of time.

A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

A phase-locked loop circuit and method for providing for compensation for an offset. A phase-locked loop circuit comprises a phase detector, a compensation circuit, a loop filter, and a VCO. The phase detector is coupled to receive a first input signal and a second input signal. The phase detector is configured to output one or more of a plurality of output signals indicative of a difference between the first input signal and the second input signal. The compensation circuit is coupled to receive the output signals and to reduce a voltage offset between the output signals. The compensation circuit is further configured to provide a plurality of compensated output signals. The loop filter is coupled to receive the compensated control signals. The loop filter is configured to output a first control signal. The VCO is coupled to receive the first control signal and to output the second input signal based on the first control signal. A method of operating a phase-locked loop circuit comprises receiving and comparing a first input signal and a second input signal and providing output signals indicative of the comparison. The method compensates for a voltage offset between the output signals and provides compensated output signals indicative of the compensation. The method filters the compensated control signals and provides a control signal indicative of the filtration. The method provides the second input signal based on the first control signal. Lower skew between the input and output may be achieved.

A tractor includes a prime mover, a driven implement selectively engaged with the prime mover, and a switch for selectively engaging and disengaging the driven implement with the prime mover. The switch has three positions including a disengaged position, a momentary position, and an engaged position located between the disengaged position and the momentary position. The prime mover can be started with the switch in the disengaged position. The prime mover can be started with the switch in the engaged position when the switch was previously moved to the momentary position before being moved to the engaged position, such that after operation of the prime mover is stopped, the prime mover can be restarted without changing the position of the switch.

A hydraulic circuit includes a clutch actuator operatively associated with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. To measure the filling rate of the hydraulic actuator, a reference actuator having a predetermined filling rate is disposed in parallel with the hydraulic actuator and in fluid communication with the hydraulic fluid source. If hydraulic pressure associated with the reference actuator does not correspond to the hydraulic pressure associated with the clutch actuator, a compensation valve can appropriately respond by selectively directing hydraulic fluid to or from the clutch actuator. In a further embodiment, the reference actuator and compensation valve may be replaced with an electrohydraulic valve utilizing feedback from the hydraulic pressure present at the inlet of the clutch actuator.

A hydraulic circuit includes a clutch actuator operatively with a clutch that may be disposed in a transmission. A hydraulic fluid source supplies pressurized hydraulic fluid for the clutch actuator. An on-off valve is disposed in fluid communication between the clutch actuator and the hydraulic fluid source; the on-off valve configured to fill the clutch actuator with hydraulic fluid. An accumulator is disposed in parallel with the on-off valve and in fluid communication with the clutch actuator. The accumulator is adapted to receive hydraulic fluid redirected from the clutch actuator and to provide a counter-pressure for modulating the clutch actuator.

A charge pump circuit includes a capacitor, a first switch between the capacitor and a power supply terminal, a second switch between the capacitor and an output terminal, a third switch between the output terminal and the capacitor, a fourth switch between the capacitor and a ground terminal, and a control unit configured to generate control signals for the switches. The control signals include first signals generated during a first period that cause first and third switches to be in an ON state and second and fourth switches to be in an OFF state, second signals generated during a second period that cause first and third switches to be in an OFF state and second and fourth switches to be in an ON state, and third signals generated between the first and second periods, that cause the ON/OFF state of each of the switches to be switched at different times.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

A load-driving circuit for receiving a supply of power from a power source and driving a load, wherein the load-driving circuit is provided with: a high-side switching element; a low-side switching element; a high-side current detection circuit connected in parallel to the high-side switching element, the high-side current detection circuit detecting a high-side driving current; and a fault detection circuit for detecting the fault state of the load-driving circuit from the output result of the high-side current detection circuit. The high-side current detection circuit is provided with a high-side sense switching circuit operating in response to a gate signal that is different from the high-side switching element, the high-side sense switching circuit comprising a device of the same type as the high-side switching element. The output result of the high-side current detection circuit, the gate signal of the high-side switching element, and the gate signal of the high-side sense switching element are input and the fault states are detected apart from each other when the connection terminal between the load-driving circuit and the load is in a state of short circuit with the positive electrode side of the power source or in a state of short circuit with the negative electrode side of the power source.

A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.