Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?

Hello,

I am using ultrasim Version 18.1.0.314.isr5  64bit 03/26/2019 06:33 (csvcm20c-2).

When I run my netlist, ultrasim is blocked in the first DC stage and takes forever. Then it will fail or never progress. I am using a 22nm BSIMBULK model. I tried to tune different accuracy and convergence aids options but noting works.

 When I run the same netlist with spectre it works fine with no problem.

Also, If I use another model (not BULKSIM), ultrasim will work and converge with no problem.

My first feeling is that ultrasim has a problem with using BSIMBULK model.

Could you please advice,

Thank you,

Kotb

Before I ask this, I am aware that I can output an s-parameter file from an SP analysis.

I'm wondering if there is a simple way of creating an s-parameter model of a component.

As an example, if I have an S-parameter model that has 200 ports and 150 of those ports are to be connected to passive components and the remaining 50 ports are to be connected to active components, I can simplify the model by connecting the 150 passive components, running an SP analysis, and generating a 50 port S-parameter file.

The problem is that this is cumbersome. You've got to wire up 50 PORT components and then after generating the s50p file, create a new cellview with an nport component and connect the 50 ports with 50 new pins.

Wiring up all of those port components takes quite a lot of time to do, especially as the "choosing analyses" form adds arrays in reverse (e.g. if you click on an array of PORT components called X<0:2> it will add X<2>, X<1>, X<0> instead of in ascending order) so you have to add all of them to the analyses form manually.

Is any way of taking a schematic and running some magic "generate S-Parameter cellview from schematic cellview"  function that automates the whole process?

Key Findings:  Nearly 100% of SoCs are mixed-signal to some extent.  Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome.  Without the magical models, the process breaks down for lack of performance, or holes in the chip verification.

In the last installment of The Low Road, we were at the mixed-signal verification party. While no one talked about it, we all saw it: The party was raging and everyone was having a great time, but they were all dancing around that big elephant right in the middle of the room. For mixed-signal verification, that elephant is named Modeling.

To get to a fully verified SoC, the analog portions of the design have to run orders of magnitude faster than the speediest SPICE engine available. That means an abstraction of the behavior must be created. It puts a lot of people off when you tell them they have to do something extra to get done with something sooner. Guess what, it couldn’t be more true. If you want to keep dancing around like the elephant isn’t there, then enjoy your day. If you want to see about clearing the pachyderm from the dance floor, you’ll want to read on a little more….

Figure 1: The elephant in the room: who’s going to create the model?

 Whose job is it?

Modeling analog/mixed-signal behavior for use in SoC verification seems like the ultimate hot potato.  The analog team that creates the IP blocks says it doesn't have the expertise in digital verification to create a high-performance model. The digital designers say they don’t understand anything but ones and zeroes. The verification team, usually digitally-centric by background, are stuck in the middle (and have historically said “I just use the collateral from the design teams to do my job; I don’t create it”).

If there is an SoC verification team, then ensuring that the entire chip is verified ultimately rests upon their shoulders, whether or not they get all of the models they need from the various design teams for the project. That means that if a chip does not work because of a modeling error, it ought to point back to the verification team. If not, is it just a “systemic error” not accounted for in the methodology? That seems like a bad answer.

That all makes the most valuable guy in the room the engineer, whose knowledge spans the three worlds of analog, digital, and verification. There are a growing number of “mixed-signal verification engineers” found on SoC verification teams. Having a specialist appears to be the best approach to getting the job done, and done right.

So, my vote is for the verification team to step up and incorporate the expertise required to do a complete job of SoC verification, analog included. (I know my popularity probably did not soar with the attendees of DVCON with that statement, but the job has to get done).

It’s a game of trade-offs

The difference in computations required for continuous time versus discrete time behavior is orders of magnitude (as seen in Figure 2 below). The essential detail versus runtime tradeoff is a key enabler of verification techniques like software-driven testbenches. Abstraction is a lossy process, so care must be taken to fully understand the loss and test those elements in the appropriate domain (continuous time, frequency, etc.).

Figure 2: Modeling is required for performance

AFE for instance

The traditional separation of baseband and analog front-end (AFE) chips has shifted for the past several years. Advances in process technology, analog-to-digital converters, and the desire for cost reduction have driven both a re-architecting and re-partitioning of the long-standing baseband/AFE solution. By moving more digital processing to the AFE, lower cost architectures can be created, as well as reducing those 130 or so PCB traces between the chips.

There is lots of good scholarly work from a few years back on this subject, such as Digital Compensation of Dynamic Acquisition Errors at the Front-End of ADCS and Digital Compensation for Analog Front-Ends: A New Approach to Wireless Transceiver Design.

Figure 3: AFE evolution from first reference (Parastoo)

The digital calibration and compensation can be achieved by the introduction of a programmable solution. This is in fact the most popular approach amongst the mobile crowd today. By using a microcontroller, the software algorithms become adaptable to process-related issues and modifications to protocol standards.

However, for the SoC verification team, their job just got a whole lot harder. To determine if the interplay of the digital control and the analog function is working correctly, the software algorithms must be simulated on the combination of the two. That is, here is a classic case of inseparable mixed-signal verification.

So, what needs to be in the model is the big question. And the answer is, a lot. For this example, the main sources of dynamic error at the front-end of ADCs are critical for the non-linear digital filtering that is highly frequency dependent. The correction scheme must be verified to show that the nonlinearities are cancelled across the entire bandwidth of the ADC. 

This all means lots of simulation. It means that the right level of detail must be retained to ensure the integrity of the verification process. This means that domain experience must be added to the list of expertise of that mixed-signal verification engineer.

Back to the pachyderm

There is a lot more to say on this subject, and lots will be said in future posts. The important starting point is the recognition that the potential flaw in the system needs to be examined. It needs to be examined by a specialist.  Maybe a second opinion from the application domain is needed too.

So, put that cute little elephant on your desk as a reminder that the beast can be tamed.

Steve Carlson

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Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor, analog behavioral and real-number model (RNM) and RTL levels, and combination of these.

In recent years, RNM and simulation is being adopted for functional verification by many, due to advantages it offers including simpler modeling requirements and much faster simulation speed (compared to a traditional analog behavioral models like Verilog-A or VHDL-AMS). Verilog-AMS with its wreal continue to be popular choice. Standardization of real number extensions in SystemVerilog (SV) made SV-RNM an even more attractive choice for MS SoC verification.

Verilog-AMS/wreal is scalar real type. SV-RNM offers a powerful ability to define complex data types, providing a user-defined structure (record) to describe the net value. In a typical design, most analog nodes can be modeled using a single value for passing a voltage (or current) from one module to another. The ability to pass multiple values over a net can be very powerful when, for example, the impedance load impact on an analog signal needs to be modeled. Here is an example of a user-defined net (UDN) structure that holds voltage, current, and resistance values:

When there are multiple drives on a single net, the simulator will need a resolution function to determine the final net value. When the net is just defined as a single real value, common resolution functions such as min, max, average, and sum are built into the simulator.  But definition of more complex structures for the net also requires the user to provide appropriate resolution functions for them. Here is an example of a net with three drivers modeled using the above defined structural elements (a voltage source with series resistance, a resistive load, and a current source):

To properly solve for the resulting output voltage, the resolution function for this net needs to perform Norton conversion of the elements, sum their currents and conductances, and then calculate the resolved output voltage as the sum of currents divided by sum of conductances.

With some basic understanding of circuit theory, engineers can use SV-RNM UDN capability to model electrical behavior of many different circuits. While it is primarily defined to describe source/load impedance interactions, its use can be extended to include systems including capacitors, switching circuits, RC interconnect, charge pumps, power regulators, and others. Although this approach extends the scope of functional verification, it is not a replacement for transistor-level simulation when accuracy, performance verification, or silicon correlation are required:  It simply provides an efficient solution for discretely modeling small analog networks (one to several nodes).  Mixed-signal simulation with an analog solver is still the best solution when large nonlinear networks must be evaluated.

Cadence provides a tutorial on EEnet usage as well as the package (EEnet.pkg) with UDN definitions and resolution functions and modeling examples. To learn more, please login to your Cadence account to access the tutorial.

ગુજરાત સ્થાપના દિવસ અંગે PM Modi એ Tweet કરીને ગુજરાતની જનતાને આપી શુભેચ્છાઓ

Modi સરકારે ત્રીજી વખત Lockdown માં કર્યો વધારો, જાણો કેટલા દિવસ સુધી રહેશે લોકડાઉન ?

ભારતમાં Coronavirus ની 30 રસી પર કામ શરૂ, PM Modi એ કરી સમીક્ષા

Buddha Purnima પર PM Modiએ કહ્યું, ભારત પોતાની વૈશ્વિક જવાબદારીનું કરી રહ્યું છે પાલન

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This Metasploit module attempts to gain root privileges with SUID Xorg X11 server versions 1.19.0 up to 1.20.3. A permission check flaw exists for -modulepath and -logfile options when starting Xorg. This allows unprivileged users that can start the server the ability to elevate privileges and run arbitrary code under root privileges. This module has been tested with CentOS 7 (1708). CentOS default install will require console auth for the users session. Xorg must have SUID permissions and may not start if running. On successful exploitation artifacts will be created consistent with starting Xorg.

Cisco Content Security Virtual Appliance M380 IronPort remote cross site host modification demo exploit.

HPP (HTTP Parameter Pollution) protection patch for ModSecurity version 2.5.9.

Modernz #11. VMS / VAX

Russia remains fDi’s most diversified commodity economy, while second ranked Brazil has displaced Ukraine into third place. Cathy Mullan reports.

In an announcement that was celebrated by the solar industry, yesterday U.S. trade officials said that bi-facial solar modules, which are solar modules that produce energy on both sides of the panel, would be exempt from import tariffs.

Last week, Corvias announced that it had entered the final phase of its geothermal installation and energy upgrades effort at the U.S. Army’s Fort Polk in West-Central Louisiana, a milestone that once complete will not only modernize the aging infrastructure but save the Army significant money and benefit military families.

California, long a progressive leader on renewable energy and climate change mitigation, has neglected a key market segment for renewable energy: the “community-scale,” or “wholesale distributed generation” (DG), market. This market segment is defined as projects below 20 megawatts that connect to the distribution grid and export power to the grid for sale.

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In an announcement that was celebrated by the solar industry, yesterday U.S. trade officials said that bi-facial solar modules, which are solar modules that produce energy on both sides of the panel, would be exempt from import tariffs.

Today’s topics include the impact of section 201 tariffs on module supply and prices. Will they go up? We’ll also talk about developing the next generation solar workforce based on a new report about energy jobs in the U.S.

Experts from Rocky Mountain Institute, the Advanced Energy Economy Institute and America’s Power Plan have released a new report that shows why new utility business models are key to the energy transition.

LONGi Solar this week said that it has invented a new “seamless soldering” technique that could help it produce a more efficient solar module. As a reminder, the more solar cells you can pack into a module, the more efficient it is. And the more efficient your modules, the fewer you need to achieve the wattage you seek in an array. By using less modules, you reduce the overall installed cost of solar.

Last week, Corvias announced that it had entered the final phase of its geothermal installation and energy upgrades effort at the U.S. Army’s Fort Polk in West-Central Louisiana, a milestone that once complete will not only modernize the aging infrastructure but save the Army significant money and benefit military families.

Construction resumed Oct. 4 on tunnel works after a brief work stoppage that began on Sept. 28 at the 20-MW Lower Modi Khola run-of-river hydropower facility.
 

Two companies have come up with a potential solution to help mitigate power outages in California. Recent state utility proposals have called for new measures that would allow California utilities to increase the quantity and duration of Public Safety Power Shutoffs (PSPS) as part of their wildfire mitigation plans. These PSPS, while important, can have severe impacts on businesses, hospitals and others who need reliable power.

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The Americans and the French have been getting on well of late. President Francois Hollande’s successful visit to the White House in February is a case in point — despite the backdrop of his high-profile sex scandal.

New York State is pushing its utility industry to shift away from a century-old business model into a system that can accommodate more power from solar and wind.

Europe’s utilities are re-evaluating their business models due to the energy transition. Members of POWER-GEN Europe’s Advisory Board consider how a reliance on fossil fuels is no longer politically desirable, forcing utilities to transform their portfolios to adapt to radical change.

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