I am gratified to see the continuing adoption of Forecast Value Added by organizations worldwide. FVA is an easy to understand and easy to apply approach for identifying bad practices in your forecasting process. And I'm particularly gratified to see coverage of FVA in two new books, which the authors [...]

The post Vandeput's Data Science for Supply Chain Forecasting (book excerpt) appeared first on The Business Forecasting Deal.

What makes something easy (or difficult) to forecast? This question was answered by Prof. Rob Hyndman on the Forecasting Impact podcast (February 6, 2021), and it's worth a look at his response. Rob was recently named a Fellow of the International Institute of Forecasters, and is someone who is known [...]

The post Hyndman's 5 Conditions for Easy Forecasting appeared first on The Business Forecasting Deal.

M6 Financial Forecasting Competition The Makridakis Open Forecasting Center has announced the M6 Financial Forecasting Competition, to begin in February 2022. This will be a "live" competition running through February 2023, with a focus on forecasts of stock price (returns) and risk, and on investment decisions based on the forecasts. [...]

The post M6 Financial Forecasting Competition announced appeared first on The Business Forecasting Deal.

I've never been much of a fan of forecasting approaches to intermittent demand. In situations like intermittent demand (or other areas where we have little hope of reasonably accurate forecasts), my thinking is "why bother?" If we can't expect to solve the problem with forecasting, we need a different approach. [...]

The post Intermittent Demand Forecasting (new book by Boylan and Syntetos) appeared first on The Business Forecasting Deal.

A man was arrested in Noida on Monday for allegedly fabricating a Transfer Certificate (TC) for his son to show that he was a juvenile when he was arrested in a rape and murder case in 2016, police said.

Arduino’s MKR family of products got two new wireless connectivity boards added to its range of products. These include MKR WiFi 1010 and MKR NB 1500, both aimed at streamlining IoT product/service development.

Arduino’s blog notes that “the Arduino MKR WiFi 1010 is the new version of the MKR1000 with ESP32 module on board made by U-BLOX.”

MKR WiFi 1010: For prototyping of WI-FI based IoT applications

The core difference of MKR WiFi 1010 compared to MKR WiFi 1000 is that the former can be put to use in production-grade IoT apps and it has ESP32-based module manufactured by u-blox. The former enables to add 2.4GHz WiFi and Bluetooth capability to the application. Additionally, it comes with a programmable dual-processor system (an ARM processor and a dual-core Espressif IC).

MKR NB 1500: For on-field monitoring systems and remote-controlled LTE-enabled modules

The Arduino MKR NB 1500 is based on new low-power NB-IoT (narrowband IoT) standard. This makes it appropriate for IoT apps running over cellular/LTE networks.

Key use cases of this board are remote monitoring systems and remote-controlled LTE-enabled modules. It supports AT&T, T-Mobile USA, Telstra, Verizon over the Cat M1/NB1 deployed bands 2, 3, 4, 5, 8, 12, 13, 20 and 28.

Arduino also pitches this board to be used in IoT apps which used to rely on alternative IoT networks such as LoRa and Sigfox. It promises to save power compared to GSM or 3G cellular-based connections.

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector. We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors—by far the main attraction of DevCon this year.

Cadence 128 GT/s TX and RX capability over optics

Block diagram of Cadence PHY for PCIe 7.0 128 GT/s demo setup with linear pluggable optics

As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Anish Mathew presenting “Impact of UIO ECN on PCIe Controller Design and Performance”

In summary, Cadence had a dominating presence on the demo floor with a record number of PCIe demos:

• PCIe 7.0 over optics
• PCIe 7.0 electrical
• PCIe 6.0 RP/EP interop back-to back
• PCIe 6.0 protocol in FLIT mode with Lecroy Exerciser (at Cadence booth)
• PCIe 6.0 protocol in FLIT mode (at the Lecroy booth)
• PCIe 6.0 JTOL with Anritsu and Tektronix equipment (at Tektronix booth)
• PCIe 6.0 protocol with Viavi Protocol Analyzer (at Viavi booth)
• PCIe 6.0 System Level Interop Demo with Gen5 platform (at SerialTek booth)

The Cadence team and its partners did a great job in coordinating and setting up the demos that worked flawlessly. This was the culmination of many weeks of hard work and dedication. Four different vendors featured our IP for PCIe 6.0. They attracted a lot of attention and drove traffic back to us.

Highlights of Cadence demos for PCIe 7.0 and 6.0

Cadence team at the PCI-SIG Developers Conference 2024

Thanks to everyone who attended the 32nd PCI-SIG DevCon. We really appreciate your interest in Cadence IP, and a big thanks to our partners and customers for all the positive feedback and for creating so much buzz for the Cadence brand.

DDR5 DIMM Architectures The DDR5 generation of Double Data Rate DRAM memories has experienced rapid adoption in recent years. In particular, the JEDEC-defined DDR5 Dual Inline Memory Module (DIMM) cards have become a mainstay for systems looking for high-density, high-bandwidth, off-chip random access memory[1]. Within a short time, the DIMM architecture evolved from an interconnected hierarchy of only SDRAM memory devices (UDIMM[2]) to complex subsystems of interconnected components (RDIMM/LRDIMM/MRDIMM[3]). DIMM Designs and Popular Verification Use Cases The growing complexity of the DIMMs presented a challenge for pre-silicon verification engineers who could no longer simply validate against single DDR5 SDRAM memory models. They needed to consider how their designs would perform against DIMMs connected to each channel and operating at gigahertz clock speeds. To address this verification gap, Cadence developed DDR5 DIMM Memory Models that encapsulated all of the architectural complexities presented by real-world DIMMs based on a robust, easy-to-use, easy-to-debug, and easy-to-reconfigure methodology. This memory-subsystem-in-a-single-instance model has seen explosive adoption among the traditional IP Developer and SOC Integrator customers of Cadence Memory Models. The Cadence DIMM models act as a single unit with all of the relevant DIMM components instantiated and interconnected within, and with all AC/Timing parameters among the various components fully matched out-of-the-box, based on JEDEC specifications as well as datasheets of actual devices in the market. The typical use-case for the DIMM models has been where the DUT is a DDR5 Memory Controller + PHY IP stack, and the validation plan mandated compliance with the JEDEC standards and Memory Device vendor datasheets. Unique Use Case for the DIMM Discrete Component Models Although the Cadence DIMM models have enjoyed tremendous proliferation because of their cohesive implementation and unified user API, the actual DIMM Models are built on top of powerful, flexible discrete component models, each of which was designed to stand on its own as a complete SystemVerilog UVM-based VIP. All of these discrete component models exist in the Cadence VIP Catalog as standalone VIPs, complete with their own protocol compliance checking capabilities and their own configuration mappings comprehensively modeling individual AC/Timing parameters. Because of this deliberate design decision, the Cadence DIMM Discrete Component Models can support a unique use-case scenario. Some users seek to develop IC Designs for the various DIMM components. Such users need verification environments that can model the individual components of a DIMM and allow them the option to replace one or another component with their Component Design IP. They can then validate that their component design is fully compatible with the rest of the components on the DIMM and meets the integrity of the overall DIMM compliance with JEDEC standards or Memory Vendor datasheets. The Cadence Memory VIP portfolio today includes various examples that demonstrate how customers can create DIMM “wrappers” by selecting from among the available DIMM discrete component models and “stitching” them together to build their own custom testbench around their specific Component Design IP. A Solution for Unique Component Scenarios The Cadence DDR5 DIMM Memory Models and DIMM Discrete Component Models can provide users with a flexible approach to validating their specific component designs with a fully populated pre-silicon environment. Augmented Verification Capabilities When the DIMM “wrapper” model is augmented with the Cadence DFI VIP[4] that can simulate an MC+PHY stack and offers a SystemVerilog UVM test API to the verification engineer, the overall testbench transforms into a formidable pre-silicon validation vehicle. The DFI VIP is designed as a combination of an independent DFI MC VIP and a DFI PHY VIP connected to each other via the DFI Standard Interface and capable of operating seamlessly as a single unit. It presents a UVM Sequence API to the user into the DFI MC VIP with the Memory Interface of the PHY VIP connected to the DIMM “wrapper” model. With this testbench in hand, the user can then fully take advantage of the UVM Sequence Library that comes with the DFI VIP to enable deep validation of their Component Design inside the DIMM “wrapper” model. Verification Capabilities Further Enhanced A possible further enhancement comes with the potential addition of an instance of the Cadence DIMM Memory Model in a Passive Monitor mode at the DRAM Memory Interface. The DIMM Passive Monitor consumes the same configuration describing the DIMM “wrapper” in the testbench, and thus can act as a reference model for the DIMM wrapper. If the DIMM Passive Monitor responds successfully to accesses from the DFI VIP, but the DIMM wrapper does not, then it exposes potential bugs in the DUT Components or in the settings of their AC/Timing parameters inside the DIMM wrapper. Debuggability, Interface Visibility, and Protocol Compliance One of the key benefits of the DIMM Discrete Component Models that become manifest, whether in terms of the unique use-case scenario described here, or when working with the wholly unified DDR5 DIMM Memory Models, is the increased debuggability of the protocol functionality. The intentional separation of the discrete components of a DIMM allows the user to have full visibility of the memory traffic at every datapath landmark within a DIMM structure. For example, in modeling an LRDIMM or MRDIMM, the interface between the RCD component and the SDRAM components, the interface between the RCD component and the DB components, and the interface between the SDRAM components and the DB components—all are visible and accessible to the user. The user has full access to dump the values and states of the wire interconnects at these interfaces to the waveform viewer and thus can observe and correlate the activity against any protocol violations flagged in the trace logs by any one or more of the DIMM Discrete Component Models. Access to these interfaces is freely available when using the DIMM Discrete Component Models. On the unified DDR5 DIMM Memory Models, a feature called Debug Ports enables the same level of visibility into the individual interconnects amidst the SDRAM components, RCD components, and DB components. When combined with the Waveform Debugger[5] capability that comes built-in with the VIPs and Memory Models offered by Cadence and used with the Cadence Verisium Debug[6] tool, the enhanced debuggability becomes a powerful platform. With these debug accesses enabled, the user can pull out transaction streams, chip state and bank state streams, mode register streams, and error message streams all right next to their RTL signals in the same Verisium Debug waveform viewer window to debug failures all in one place. The Verisium Debug tool also parses all of the log files to probe and extract messages into a fully integrated Smart Log in a tabbed window fully hyperlinked to the waveform viewer, all at your fingertips. A Solution for Every Scenario Cadence's DDR5 DIMM Memory Models and DIMM Discrete Component Models , partnered with the Cadence DFI VIP, can provide users with a robust and flexible approach to validating their designs thoroughly and effectively in pre-silicon verification environments ahead of tapeout commitments. The solution offers unparalleled latitude in debuggability when the Debug Ports and Waveform Debugger functions of the Memory Models are switched on and boosted with the use of the Cadence Verisium Debug tool. [1] Shyam Sharma, DDR5 DIMM Design and Verification Considerations , 13 Jan 2023. [2] Shyam Sharma, DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM) , 23 Sep 2024. [3] Kos Gitchev, DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers , 26 Aug 2024. [4] Chetan Shingala and Salehabibi Shaikh, How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device? , 29 Mar 2022. [5] Rahul Jha, Cadence Memory Models - The Gold Standard , 15 Apr 2024. [6] Manisha Pradhan, Accelerate Design Debugging Using Verisium Debug , 11 Jul 2023.

Hello All,

I'm a novice to this forum and probably this subject has been already discussed here.

My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.

However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.

Does anybody have opinion on this issue?

Many thanks,

Pavel

FDI levels have already fallen throughout Iran's main sphere of influence in the region. 

We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. 

Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf.

The coronavirus pandemic could change human behaviour more permanently in future.

Secularism, Caste, and Class in Contemporary India Secularism, Caste, and Class in Contemporary India

Taipei, Taiwan — Taiwan on Monday said it had closed a probe into pagers that exploded in Lebanon in September and caused a deadly blow to Iran-backed Hezbollah, saying no Taiwanese citizens or companies were involved. Israeli media reported that Israeli Prime Minister Benjamin Netanyahu claimed responsibility for the attack during a cabinet meeting, telling ministers that senior defense officials and political figures were opposed to the detonation of the pagers but that he went ahead with the operation. Security sources have previously said the pagers carried the name of Taiwan-based Gold Apollo, a company which has asserted that it did not make them. Taiwan's government has also said the pagers were not made in Taiwan. Taipei prosecutors, who were investigating the case, said in a statement the AR-924 pager model that exploded in Lebanon was manufactured, traded, and shipped by a firm called Frontier Group Entity, and made outside of Taiwan. They added, however, that Gold Apollo had authorized the company to use the Apollo trademark. "There is no evidence indicating that any domestic manufacturers or individuals were accomplices in the relevant explosions, violating the Counter-Terrorism Financing Act, or engaging in other illegal activities," the prosecutors said in a statement. "No concrete evidence of criminal activity has been discovered in this case, nor have any specific individuals been implicated in any criminal activity, following a comprehensive investigation." Prosecutors have previously confirmed that they questioned Gold Apollo's president and founder Hsu Ching-kuang and a woman called Teresa Wu, the sole employee of a company called Apollo Systems Ltd. In their statement, the prosecutors said Wu acted as a liaison with Frontier, but there was no evidence she "had prior knowledge or participated in any conspiracy or collaboration related to the explosion incidents." The prosecutors said there was some information they did not know, including the exact identities of the Frontier employees Wu communicated with. It said one person was called "T" and was presumably the head of Frontier, while another was called "M" and was presumably the sales director. Gold Apollo told Reuters it had also just seen the prosecutor’s statement, and that it was not immediately able to comment further.

Jawiga siyaasadeed ee Soomaaliya ayaa muddo dheer ahaa mid jaahwareersan  oo cakiran. Saddex xilli ayaa la…

The post Ma la gaaray xilligii uu Raysal Wasaare Xamse Barre is casili lahaa? appeared first on Horseed Media.

OTTAWA, Ontario — Canada has detected its first presumptive case of H5 bird flu in a person, a teenager in the western province of British Columbia, health officials said Saturday. The teenager likely caught the virus from a bird or animal and was receiving care at a children's hospital, the province said in a statement. The province said it was investigating the source of exposure and identifying the teenager's contacts. The risk to the public remains low, Canada's Health Minister Mark Holland said in posting on X. "This is a rare event," British Columbia Health Officer Bonnie Henry said in a statement. "We are conducting a thorough investigation to fully understand the source of exposure here in B.C." H5 bird flu is widespread in wild birds worldwide and is causing outbreaks in poultry and U.S. dairy cows, with several recent human cases in U.S. dairy and poultry workers. There has been no evidence of person-to-person spread so far. But if that were to happen, a pandemic could unfold, scientists have said. Earlier in November, the U.S. Centers for Disease Control and Prevention asked for farm workers who have been exposed to animals with bird flu to be tested for the virus even if they do not have symptoms. Bird flu has infected nearly 450 dairy farms in 15 U.S. states since March, and the CDC has identified 46 human cases of bird flu since April. In Canada, British Columbia has identified at least 22 infected poultry farms since October, and numerous wild birds tested positive, according to the province. Canada has had no cases reported in dairy cattle and no evidence of bird flu in samples of milk.  

TORONTO, canada — A teenager is in critical condition in a British Columbia children's hospital, sick with Canada's first presumptive human case of avian influenza. "This was a healthy teenager prior to this, so no underlying conditions," said provincial health officer Bonnie Henry in a news conference on Tuesday. "It just reminds us that in young people this is a virus that can progress and cause quite severe illness, and the deterioration that I mentioned was quite rapid." British Columbia health officials said on Saturday the province had detected Canada's first human case of H5 bird flu in a teenager. Henry said the province is still identifying the exact strain but assumes the case is H5N1. The World Health Organization says H5N1's risk to humans is low because there is no evidence of human transmission, but the virus has been found in an increasing number of animals, including cattle in the United States. Henry would not disclose the teen's gender or age but said the patient had first developed symptoms on November 2 and was tested on November 8, when admitted to a hospital. Symptoms included conjunctivitis, fever and coughing. As of Tuesday, the teen was hospitalized with acute respiratory distress syndrome, she said. The teen had no farm exposure but had been exposed to dogs, cats and reptiles, Henry said. No infection source had been identified. "That is absolutely an ongoing investigation." More severe illness takes place when the virus binds to receptors deep in the lungs, she said. Public health officials had identified and tested about three dozen contacts and had not found anyone infected with the virus. There has been no evidence that the disease is easily spread between people. But if that were to happen, a pandemic could unfold, scientists have said. Earlier in November, the U.S. Centers for Disease Control and Prevention asked that farm workers exposed to animals with bird flu be tested for the virus even if they did not have symptoms. Bird flu has infected nearly 450 dairy farms in 15 U.S. states since March, and the CDC has identified 46 human cases of bird flu since April. In Canada, British Columbia has identified at least 26 affected premises across the province, Henry said Tuesday, and numerous wild birds have tested positive. Canada has had no cases reported in dairy cattle and no evidence of bird flu in samples of milk.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

A business process outsourcing employee who was slapped by relieved Presidential Anti-Organized Crime Commission spokesman Winston John Casio during a raid on a suspected Philippine offshore gaming operator hub in Bagac, Bataan has filed criminal charges against the official.

MDA team from Karnei Shomron sped to southern Israel on October 7 to save lives

The current conflict in the Middle East will leave a lasting environmental impact, prompting calls for urgent restoration and cross-border cooperation.

[Capital FM] Nairobi -- The Politics surrounding the control of the Sh10.5 billion Road Maintenance Levy Fund between MPs and Governors has continued to stall talks to iron out the stalemate over the equitable revenue share to the devolved units.

Maltese judge quashes extradition to the US of Daniel Meli, ordering that his case be reheard by the magistrates’ court 

This month, the International Monetary Fund (IMF) had an opportunity to end one of its most reviled policies and lift billions of dollars of debt off the backs of crisis-stricken developing countries. It chose not to. The IMF’s ostensible mission is to promote financial stability by providing loans to countries facing economic challenges or crises. […]

Thai diplomats have been urged to take a proactive approach to attracting foreign investors following Donald Trump's US presidential election victory, Prime Minister Paetongtarn Shinawatra said on Tuesday.

The attorney general has submitted documents to the Constitutional Court regarding the case in which former prime minister Thaksin Shinawatra is accused of asserting influence over the Pheu Thai Party.

Security sources have previously said the pagers carried the name of a Taiwan-based company that has asserted that it did not make them.

Opening remarks by Roberta Casali, ADB Vice-President for Finance and Risk Management, at the 2024 Asian Regional Forum on Investment Management of Foreign Exchange Reserves, 25 September 2024, Japan

Donald Trump has said he wouldn’t be a dictator — “except for Day 1.” According to his own statements, he’s got a lot to do on that first day in the White House.

Case study on Singapore explains the country's resilience to swings in capital flows.

In a case study on Korea, a VAR model is used to investigate the effects of capital flows on asset prices.

To attract infrastructure investment to meet national goals for providing electricity to consumers, India needs continued macroeconomic stability as well as an improved policy and regulatory environment.

Lack of access to good road networks is a major constraint on the incomes and welfare of the poor. Using household expenditure survey data for Lao PDR this paper models the causes of poverty and shows the impact on poverty levels of road improvements.

The Supreme Court (SC) on Tuesday announced that the recently established constitutional bench will start hearing cases on November 14 and 15.

Earlier, the SC constituted a three-judge committee to fix cases, issue court rosters, form benches, and decide weekly caseload for its recently established constitutional bench.

The committee held a meeting today which was chaired by Justice Aminud Din Khan (head of the constitutional bench) and attended by Justice Jamal Khan Mandokhail and Justice Muhammad Ali Mazhar, who participated through a telephone call from Karachi.

The SC said in a press release, a copy of which is available with Dawn.com, that the purpose of the meeting was to discuss matters for the formation of the constitutional bench.

During the meeting, the committee was briefed by the court’s registrar’s office regarding the pending constitutional cases, the statement said adding, “[The] committee resolved that priority shall be accorded to the oldest cases.”

On Nov 5, the Judicial Commission of Pakistan (JCP), in its maiden session, had picked Justice Amin as head of the constitutional bench by a seven-to-five majority.

Chaired by Chief Jus­tice of Pakistan (CJP) Jus­tice Yahya Afridi, the reconstituted JCP for­m­ed a seven-member con­stitutional bench, inc­­luding Justices Ami­nud Din Khan, Jamal Khan Mandokhail, Muha­m­mad Ali Mazhar, Ayesha A. Malik, Hassan Azhar Rizvi, Musarrat Hilali and Naeem Akhtar Afghan.

Today’s press release mentioned that Justice Ayesha Malik will not be available on Nov 14 and 15 and “a bench comprising all available Judges shall be constituted to proceed with cases on these dates.”

The SC Registrar Muh­ammad Salim Khan released the court roster of a six-member constitutional bench which will begin hearing cases at 9:30am on Nov 14.

The bench will include Justice Jamal Khan Mandokhail, Justice Muhammad Ali Mazhar, Justice Hasan Azhar Rizvi, Justice Musarrat Hilali and Justice Naeem Akhtar Afghan.

The SC directed the Registrar to schedule cases for hearing before the bench.

The next meeting of the committee will be held on Nov 13 at 12:30pm after Justice Muhammad Ali Mazhar arrives in Islamabad.