People snapped grouping together at popular spots in Milan, defying social-distancing rules just days after the city eased its lockdown, have prompted an Italian virologist to compare it to a ticking coronavirus infection ‘bomb.’
Read Full Article at RT.com

While he says he has no interest in facing a top-ranked boxer, Floyd Mayweather is refusing to rule out a fight with the likes of Conor McGregor or Khabib Nurmagomedov, as long as the money is right.
Read Full Article at RT.com

Outdoors, patterns abound. One need not be a mathematician in order to view and appreciate them. The widening whorls of seeds in a sunflower head are often used to illustrate the Fibonacci sequence of numbers (0, 1, 1, 2, 3, 5, 8….) in which each figure is the sum of the two preceding digits. Other […]

The post Fractals and Flow appeared first on DNERR Blog - State of Delaware.

GSTN added that a taxpayer can now transfer the amount available in an electronic cash ledger from one major head to another major head, keeping the minor head the same.

Schneider and collaborator Ralf Hutter combined the German language lyrics with synthesisers and drum machines to create 'krautrock,' which won Kraftwerk a legion of musician fans, including David Bowie, Madonna, Daft Punk and Kanye West

One of the reasons is bunching together of several regulatory changes announced by the government in a very short span of time without realising their full implication, a classic case of ‘reform for reform’s sake’.

Kishor said the CM may have brought development in Bihar “in comparison to what Lalu Prasad did” but the development indices remain dismal when compared to other states.

End of 2019 and the beginning of 2020 will happen in just a few hours from now. That said, we take a look at some of the successful and flop two-wheelers of the current year.

To Dick Costolo, there’s gold in them thar tweets, and Twitter has just begun to mine it.

The RBI announced the liquidity facility under the TLTRO 2.0 window for NBFCs and MFIs after these institutions failed to get funding under the earlier TLTRO scheme announced late in March.

Implementation of three months moratorium on repayment of loan instalments announced by the RBI was also reviewed during the meeting.

Did you miss last month's Pink Supermoon? Don’t worry! You can witness another supermoon today.

Super Flower Moon 2020: Scintillating images of the full moon, also a 'supermoon', are being shared from across the world.

Industry experts say that lump-sum investments have stopped and even some investors are stopping their SIPs, due to the unpredictable equity markets.

The meeting, to be held via video conference, will also dwell on credit disbursement since March, with the focus on Covid-19-related credit sanction and offtake.

The country's largest domestic airlines had on Friday announced pay cut ranging between 5 and 25 per cent, in addition to its leave-without-pay programme for May, June and July, for senior employees.

Winds are from the West at 12.7 gusting to 36.8 MPH (11 gusting to 32 KT). The pressure is 1006.9 mb and the humidity is 34%. The wind chill is 31. Last Updated on May 9 2020, 11:53 am EDT.

A radical new form of universal basic income could revitalise damaged economies

While countries in east Asia and Europe are gradually taking steps towards reopening their economies, many in the global south are wondering whether the worst of the pandemic is yet to come. As economists who work on poverty alleviation in developing countries, we are often asked what the effects of coronavirus will be in south Asia and Africa. The truth is, we don’t know. Without extensive testing to map the number of cases, it’s impossible to tell how far the virus has already spread. We don’t yet have enough information about how Covid-19 behaves under different conditions such as sunlight, heat and humidity. Developing countries’ more youthful populations may spare them the worst of the pandemic, but health systems in the global south are poorly equipped to deal with an outbreak, and poverty is linked to co-morbidities that put people at a higher risk of serious illness.

Without the information widespread testing provides, many poorer countries have taken an extremely cautious approach. India imposed a total lockdown on 24 March, by which time the country had about 500 confirmed cases. Countries such as Rwanda, South Africa and Nigeria enforced lockdowns in late March, long before the virus was expected to peak. But these lockdown measures can’t last forever. Poorer countries could have used the quarantine to buy time, gather information about how the disease behaves and develop a testing and tracing strategy. Unfortunately, not much of this has happened. And, far from coming to their aid, rich countries have outrun poorer nations in the race for PPE, oxygen and ventilators.

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design or verification engineer can use.

JasperGold was the initial (in fact only) product of Jasper Design Automation, acquired by Cadence in 2014. Jasper pioneered the formal Apps concept several years ago. While the company had previously sold JasperGold as a one-size-fits-all solution, Jasper began selling semi-automated JasperGold Apps that solved specific problems using formal analysis technology.

The new release is the next generation of JasperGold and will be available later this month. It includes three major improvements over previous Cadence and Jasper formal analysis offerings:

• A unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain over previous solutions.
• JasperGold is integrated into the Cadence System Development Suite, where it provides formal-assisted simulation, emulation, and coverage. As a result, System Development Suite users can find bugs three months earlier than existing verification methods.
• JasperGold’s formal analysis engines are integrated with the recently announced Indago debug platform, automating root cause analysis and on-the-fly, what-if exploration.

Best of Both Formal Verification Worlds

Taking advantage of technologies from both Cadence and Jasper, the new JasperGold represents a “best of both worlds” solution, according to Pete Hardee, product management director at Cadence. This solution combines technologies from the Cadence Incisive Enterprise Verifier and Incisive Formal Verifier with JasperGold formal analysis engines.

For example, to ease migration from Incisive formal tools, Cadence has integrated an Incisive common front end into the JasperGold apps platform. Jasper formal engines can run within the Incisive run-time environment. Cadence has also brought some selected Incisive formal engines into JasperGold.

As shown to the right, the JasperGold platform supports both the existing JasperGold front-end parser and the Incisive front-end parser. Hardee observed that this dual parser arrangement simplifies migration from Incisive formal tools to JasperGold, and provides a common compilation environment for people who want to use JasperGold with Incisive simulation. Further, the common run-time environment enables formal-assisted simulation.

The combination of JasperGold engines and Incisive engines supports two use models for formal analysis: formal proofs and bug hunting. In the first case, formal engines try all combinations of inputs without a testbench. The test is driven by formal properties written in languages such as SVA (SystemVerilog assertions) or PSL (Property Specification Language). Completion of a property is exhaustive proof that something can or cannot happen. This provides a “much stronger result” than simulation, Hardee said.

He also noted that formal analysis doesn’t necessarily require that all properties are completed. “You can get a lot of value even if proofs don’t complete,” he said. “Proofs that run deep enough to find bugs are just fine.”

Bug hunting involves random searches, and JasperGold bug hunting engines are very fast. However, these engines don’t necessarily use the most optimal path to get to a bug. So, Cadence engineers brought a constraint solver from Incisive and integrated it into JasperGold. “It looks at the constraints in the environment and gives you a better starting point,” Hardee said. “It takes more up-front time, but once you’ve done that the bug hunting engines can actually take a shorter path and find a bug a lot quicker.”

Another new JasperGold capability from the Incisive Formal Verifier is called “search pointing.” This uses simulation to penetrate deeply into the state space, and then kicks off a random formal search from a given point that you’ve reached in simulation. This technique makes it possible to find bugs that are very deep in the design.

It is probably clear by now that a number of different formal “engines” may be required to solve a given verification problem. Traditionally, a formal tool (or user) will farm a problem out to many engines and see which one works best. To put more intelligence into that process, Cadence launched the Trident “multi-cooperating engine” a couple of years ago. That has now been brought into JasperGold, where it helps “orchestrate” the engines according to what will work best for the design. This is a big part of the reason for the 15X speedup noted earlier in this post.

Integration with System Development Suite

The Cadence System Development Suite is an integrated set of hardware/software development and verification engines, including virtual prototyping, Incisive simulation, emulation, and FPGA-based prototyping. As shown below, JasperGold technology is integrated into the System Development Suite in several places, including formal-assisted debug, formal-assisted verification closure, formal-assisted simulation, formal-assisted emulation, and the Incisive vManager verification planning tool.

Formal-assisted emulation sounds like it should be easy, especially since Cadence has both accelerated verification IP (VIP) and assertion-based VIP. However, there’s a complication. Accelerated VIP represents less verification content than simulation VIP, because you have to remove many checkers to get VIP to compile on a Palladium emulator. That’s because the Palladium requires synthesizable code.

What you can do, however, is use assertion-based VIP in “snoop mode” as shown below. Assertion-based VIP coded in synthesizable SystemVerilog can replace the missing checkers in accelerated VIP. In this diagram, everything in the green box is running in the emulator and is thus completely accelerated.

Another example of formal-assisted emulation has to do with deep traces. As Hardee noted, emulation will produce very long traces, and it can be very difficult to find a point of interest in the trace and determine what caused an error. With formal-assisted emulation, users can find interesting events within the traces and create properties that mark them, so a debugger can find these events and trace back to the root cause.

Formal-assisted verification closure is available with the new JasperGold release. This is possible because you can use the vManager product to determine which tasks were completed by formal engines. It’s important information for verification managers who are not used to formal tools, Hardee noted.

Another aspect of formal-assisted verification closure is the JasperGold Unreachability Analysis (UNR) App, which can save simulation users weeks of time and effort. This App takes in the simulation coverage database and RTL, and automatically generates properties to explore coverage holes and determine if holes are reachable or unreachable. The App then generates an unreachable coverage point database. If the unreachable code does something useful, there’s a bug in the design or the testbench; if not, you don’t have to worry about it. The diagram below shows how it works.

Formal-Assisted Debugging

The third major component of the JasperGold announcement is the integration of formal analysis into the Indago debugging platform. As shown below, this platform has several apps, including the Indago Debug Analyzer. Two formal debug capabilities from the Jasper Visualize environment have been added to the the Indago Debug Analyzer:

• Highlight Relevant Logic: This highlights the “cone of influence,” or the logic that is involved in reaching a given point
• Why: This button highlights the immediate causes for a given event, and allows users to trace backwards in time

More formal capabilities will come with the Indago Advanced Debug Analyzer app, scheduled for release towards the end of 2015. This includes Quiet Trace, a Jasper capability that reduces trace activity to transactions relevant to an event. Also, a what-if analysis allows on-the-fly trace editing and recalculation to explore effects and sensitivities, without having to re-compile and re-execute the simulation.

Finally, Cadence has a Superlint flow that is now fully integrated with the JasperGold Visualize debugger. This two-tiered flow includes a basic lint capability as well as automated formal analysis based on the JasperGold Structural Property Synthesis app. “This could be a very good entry point for designers to start using formal,” Hardee said.

“Formal is taking off,” Hardee concluded. “People are no longer talking about return on investment for formal—they have established that. Now they’re supporting a proliferation of formal in their companies such that a wider set of people experience the benefit from that proven return on investment.”

Further information is available at the JasperGold Formal Verification Platform (Apps) page.

Richard Goering

Related Blog Posts

- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow

- Why Cadence Bought Jasper—A New Era in Formal Analysis

- Q&A: An R&D Perspective on Formal Verification—Past, Present and Future

Hi,

  I wanted to open a discussion on the stylus flowtool.  My purpose is to see if there are users out there who are having success with the tool.  To have some discussions around issues that I am running into and to get a user point of view on the problems I am trying to solve.

  Let's start the conversation with : Is there anyone out there trying to use flowtool?  Do you have a centralized flow, or each user has their own?

Thanks, and I look forward to the conversations...

--Craig Crump

Respected sir,

How can i design and simulate cmos inverter using digital flow and also ineed to do prelayout ans post layout for the same cmos inverter..can i use cadence encounter for this experiments

Hi,

i am designing a broadband (100 MHz -6 GHz BW) receiver chain for  radar/rcs measurement tester. i will put Low noise amplifier after antenna input followed by mixed(10 MHz IF BW and digitizer.

I am facing problem regarding LAN. bandwidth of LAN is  approx 6 GHz(100 MHz-6GHz), gain 25-35 dB, with NF less than 2. I am uncertain about noise floor at the output of LNA.  I dont know exact SNR at the input of LNA but it shall be good.System operation will be on stepped CW waveform so receiver input signal will sweep over the BW and some step size.

so LNA output r noise floor will be? i assume, we can neglect thr role of input noise because it will be lesser than internal noise of LNA.

will it be LNA internal noise (Thermal noise due to BW) only ?

will it be LNA internal noise (Thermal noise due to BW)  + LAN Gain ? -78+25 =-53 dB? internal noise shall be lesser because NF is less than 3 . 

i have practically observed that that output noise floor is much lesser then even thermal noise( over LNA BW). i have gone through some tutorial where  formula says( internal noise+input noise)+gain. in  my case input noise shall be much less than theoretical internal noise. 

Thanks

I am trying to create NoProbeTop using skill language for the chip component.

My code snippet is :
thisNPTShape2 = axlDBCreateOpenShape(path t "MANUFACTURING/NO_PROBE_TOP" nil )

I am getting the below output values:
path = _axlPath@0x24399f41d28.

*WARNING* (axlDBCreateOpenShape): Not a floating-point number! - nil

Can you guide me on how to convert to floating-point/get out of the floating-point error?

Hi all,

I need to develop a digital design/verification solution to compile,elaborate and simulate SV designs (basically a complex xrun wrapper). I am an experienced user of xrun and I have done a number of these wrappers over the years but this one is to be more of a tool, intented to be used Company-wise, so it needs to be very well thought and engineered.

It needs to be robust, simple and extensible. It needs to support multi-snapshot elaboration, run regressions on machine farms, collect coverage, create reports, etc.

I've been browsing the vast amount of documentation on XCELIUM and, although very good, I can't find any document which puts together all the pieces of what I am trying to achieve. I suppose I am more clear on the elaboration, compilation and simulation part but I am really lacking on the other areas like : LSF, regressions coverage, where does vManager fits in all this, etc.

I'd appreciate if someone can comment on whether there is a document which depicts how such a DV flow can be put together from scratch, or whether there is a kind of RAK with some example xrun wrapper.

Thanks

Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.(read more)

This Metasploit module exploits a vulnerability found in the ActiveX component of Adobe Flash Player before 12.0.0.43. By supplying a specially crafted swf file it is possible to trigger an integer underflow in several avm2 instructions, which can be turned into remote code execution under the context of the user, as exploited in the wild in February 2014. This Metasploit module has been tested successfully with Adobe Flash Player 11.7.700.202 on Windows XP SP3, Windows 7 SP1 and Adobe Flash Player 11.3.372.94 on Windows 8 even when it includes rop chains for several Flash 11 versions, as exploited in the wild.

AoA DVD Creator version 2.6.2 suffers from an overflow vulnerability.

AoA Audio Extractor Basic version 2.3.7 suffers from an overflow vulnerability.

AoA MP4 Converter version 4.1.2 suffers from an overflow vulnerability.

This Metasploit module exploits a buffer overflow vulnerability in Advantec WebAccess. The vulnerability exists in the dvs.ocx ActiveX control, where a dangerous call to sprintf can be reached with user controlled data through the GetColor function. This Metasploit module has been tested successfully on Windows XP SP3 with IE6 and Windows 7 SP1 with IE8 and IE 9.

Core Security Technologies Advisory - Advantech WebAccess version 7.2 is vulnerable to a stack-based buffer overflow attack, which can be exploited by remote attackers to execute arbitrary code, by providing a malicious html file with specific parameters for an ActiveX component.

The TRENDnet UltraCam ActiveX Control UltraCamX.ocx suffers from a stack buffer overflow vulnerability when parsing large amount of bytes to several functions in UltraCamLib, resulting in memory corruption overwriting several registers including the SEH. An attacker can gain access to the system of the affected node and execute arbitrary code. Versions TV-IP422WN and TV-IP422W are affected.

The UltraHVCam ActiveX Control 'UltraHVCamX.ocx' suffers from a stack buffer overflow vulnerability when parsing large amount of bytes to several functions in UltraHVCamLib, resulting in memory corruption overwriting several registers including the SEH. An attacker can gain access to the system of the affected node and execute arbitrary code. Versions affected include PT Type ICS2330, Cube Type ICS2030, and Dome Type ICS7522.

The UltraSVCam ActiveX Control 'UltraSVCamX.ocx' suffers from a stack buffer overflow vulnerability when parsing large amount of bytes to several functions in UltraSVCamLib, resulting in memory corruption overwriting several registers including the SEH. An attacker can gain access to the system of the affected node and execute arbitrary code. Versions affected include Bullet Type ICL5132 and Bullet Type ICL5452.

This Metasploit module exploits a buffer overflow in the VideoPlayer.ocx ActiveX installed with the X360 Software. By setting an overly long value to 'ConvertFile()',an attacker can overrun a .data buffer to bypass ASLR/DEP and finally execute arbitrary code.

1 Click Extract Audio version 2.3.6 suffers from an active-x buffer overflow vulnerability.

1 Click Audio Converter version 2.3.6 suffers from an active-x buffer overflow vulnerability.

Micro Focus Rumba versions 9.3 and below suffer from an active-x stack buffer overflow vulnerability.

Avaya IP Office (IPO) versions 9.1.0 through 10.1 suffer from an active-x buffer overflow vulnerability.

BarcodeWiz ActiveX Control versions prior to 6.7 suffers from a buffer overflow vulnerability.

G DATA TOTAL SECURITY version 25.4.0.3 suffers from an active-x buffer overflow vulnerability.

DiskBoss version 7.7.14 Input Directory local buffer overflow proof of concept exploit.

CloudMe version 1.11.2 buffer overflow proof of concept exploit. Original vulnerability discovered by hyp3rlinx.

An ICMP Type 8 (ping) flooder for Windows 95 and above. Includes Delphi source code.

UDP Flooder for Windows 95 and above. It can send udp packets with a user specified data, source and destination port. Includes Delphi source code.

10Strike LANState version 9.32 on x86 Host Check hostname SEH buffer overflow exploit.