Investors in MagnaChip Semiconductor Corporation (NYSE:MX) had a good week, as its shares rose 6.5% to close at...

(United States Federal Circuit) - Ruling of the International Trade Commission that respondent-intervenor uPI violated the Consent Order as to the imports known as "formerly accused products" is affirmed, the modified penalty is affirmed, and the ruling of no violation as to the post-Consent Order products is reversed, where: 1) substantial evidence does not support the Commission's conclusion that uPI's post-Consent Order products were independently developed; and 2) the United States sale or importation of downstream products, which incorporate uPI's formerly accused upstream products and infringe the '190 patent, constitutes a violation of the Consent Order's knowingly aiding or abetting provision.

(California Court of Appeal) - Award of attorney fees to defendant in an underlying action for misappropriation of trade secret by seeking to hire away plaintiff's employees, is affirmed where: 1) the trial court's findings are free of procedural error; 2) the finding of plaintiff's bad faith is amply supported by evidence that defendants did no more than attempting to recruit the employees of a competitor, which they are entitled to do under California state law; and 3) defendant prevailed when plaintiff dismissed the suit to avoid an adverse determination on the merits.

(California Court of Appeal) - In a trademark secrets and employment case arising out of the formation of defendant uPI Semiconductors by employees of plaintiff Richtek, the sustaining of defendants' demurrer is reversed where the trial court improperly took judicial notice of the substantive allegations contained in two 2007 court complaints filed in Taiwan to resolve factual disputes in the case.

(United States Federal Circuit) - Affirmed in part and vacated in part where a jury found that defendant had infringed on plaintiff's patents and had awarded damages based on the entire market value rule. The Federal Circuit court affirmed the infringement judgment, but vacated the damages award stating that the entire market value rule could not be used in this case.

RS Semitech Inc. Semiconductor Equipment Engineer. Provides engineering services to customer companies; Draws up or proposes modification in semiconductor equipment and machines, processes, or use of materials or services which would result in cost reduction or improvement in operations and helps to

(Arizona State University) Cun-Zheng Ning, a professor of electrical engineering in the Ira A. Fulton Schools of Engineering at Arizona State University, and collaborators from Tsinghua University in China discovered a process of physics that enables low-power nanolasers to be produced in 2D semiconductor materials. Understanding the physics behind lasers at nanoscale and how they interact with semiconductors can have major implications for high-speed communication channels for supercomputers and data centers.

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

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I recently attended a webinar presented by Wally Rhines about his new book, Predicting Semiconductor Business Trends After Moore's Law . Wally was the CEO of Mentor, as you probably know. Now he...

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Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

Chief executives of the nation's leading companies like Samsung Electronics, SK Hynix, and LG Display have made a request to the government to relieve the problem of labor shortage in the area of semiconductor and display. Kwon Oh-hyun, vice chairman of Samsung Electronics, said on September 18 in a discussion session held in Kensington Hotel in Seoul's Yoido presided over by Minister of Trade, Industry, and Energy Baek Woon-gyu, "Skilled workers are in short supply in fast-growing industries...

The U.S. needs a more expansive strategy to maintain its lead in this field, and that means working closely with its allies, especially Japan.

SST Announces Qualification of Smartbit™ OTP NVM Technology for ON Semiconductor’s 110 nm CMOS Process

Rep. McSally Visits Microchip Executives to Discuss Semiconductor Supply Chain Resilience in the U.S. Amid Defense Industrial Base Report Findings

Peter Picone, 40, of Methuen, Mass., has been charged with importing counterfeit semiconductors from China for sale in the United States.

The thin, skin-like electronics may usher in a future of earth-friendly gadgets.

An EU-funded project is enabling efficient intra-chip and chip-to-chip communication via a new type of silicon capable of emitting light. It is demonstrating a technological breakthrough that could revolutionise the electronics industry and make devices faster and much more energy efficient.

Imports of Diode & Semiconductors in China increased to 2075000 USD THO in April from 1973300 USD THO in March of 2020. Imports of Diode & Semiconductors in China averaged 999568.20 USD THO from 1996 until 2020, reaching an all time high of 2799480.44 USD THO in December of 2015 and a record low of 35700 USD THO in February of 1996. This page includes a chart with historical data for China Imports of Diode & Semiconductors.

Imports of Semiconductors in the United States increased to 5743.14 USD Million in March from 4983.18 USD Million in February of 2020. Imports of Semiconductors in the United States averaged 2771.22 USD Million from 1989 until 2020, reaching an all time high of 5743.14 USD Million in March of 2020 and a record low of 963.95 USD Million in October of 1990. This page includes a chart with historical data for the United States Imports of Semiconductors.

Responding to oncoming U.S.-China commercial friction in recent years, firms operating in the complex, dense semiconductor ecosystem centered on the United States and Northeast Asia began a gradual evaluation of whether and how to reshape their supply chains and investments, and still maximize profit. As a foundational industry for maintaining economic competitiveness and national security, semiconductors serve as a keystone in U.S. and Japanese technological leadership.  Against the backdrop of nascent U.S.-China technology competition and the standstill from the coronavirus, adjustments  to enhance resiliency and mitigate disruption through developing semiconductor supply chains and investments outside of China, including in Southeast Asia, should be supported.    

The Japanese government’s April 8, 2020, announcement that it will support Japanese corporations in shifting operations out of China and reducing dependency on Chinese inputs reflects this impulse. While impressive sounding, the $2.2 billion Japan allocated as part of its larger stimulus package to counter the headwinds of the coronavirus, is a mere drop in the bucket for the semiconductor industry of what would be an immense cost to totally shift operations and supply chains out of China. Semiconductor manufacturing is among the most capital-intensive industries in the global economy. Moreover, costs within Japan to “bring manufacturing back” are very high. Despite this – while Japan is not the super power it once was in semiconductors – it still has cards to play. 

Concurrently, officials in the United States, through a combination of  concerns over security and lack of supply chain redundancy, are also pushing for new investments to locate a cutting-edge fabrication facility in the continental U.S. One idea is to build a new foundry operated by Taiwanese pure-play giant TSMC. The Trump administration is considering other incentives to increase attractiveness for companies to invest in new front-end facilities in the United States, to maintain the U.S. dominant position in the industry and secure supply for military applications. Global semiconductor companies may be reluctant. After all, investments, facilities, and the support eco-system in China are in place, and revenues from the Chinese market enable U.S. semiconductor firms to reinvest in the research and development that allows them to maintain their market lead. And in the United States, there may be limits on the pool of human capital to rapidly absorb extensive new advanced manufacturing capacity.   

But there are two factors in a geopolitical vise closing at unequal speed on companies in the industry that will increase supply chain disruption: China’s own semiconductor efforts and U.S.-Japanese export controls. As part of the Made in China 2025 industrial policy initiative, General Secretary Xi Jinping and Chinese Communist Party leadership have tripled down to overcome past failures in Chinese efforts to develop indigenous semiconductor manufacturing capability. Following penalties brought by the U.S. Department of Commerce against ZTE and then Huawei, the Chinese leadership’s resolve to reduce its dependence on U.S. semiconductors has crystalized. The Chinese government intends to halve U.S. sourced semiconductor imports by 2025 and be totally independent of U.S. chips by 2030. And while behind in many areas and accounting for the usual state-directed stumbles, Chinese companies have made some progress in designing AI chips and at the lower end of the memory storage market. Even if the overall goals may prove unattainable, firms should heed the writing on the wall – China only wants to buy U.S. chips for the short term and as soon as possible end all foreign dependence. 

Leaders in the United States and Japan are also crafting some of their first salvos in what is likely to be a generation-long competition over technology and the future of the regional economic order with China. The Trump administration, acting on a bipartisan impetus after years of Chinese IP theft and recognizing mounting hardware security concerns, has begun planning to implement additional export controls directed at Chinese companies and certain chips. Japan and the United States have also reportedly initiated dialogue about coordinating export controls in the area of semiconductor manufacturing equipment. 

Collectively, these policies will be highly disruptive to semiconductor value chains and downstream technology companies like Apple and NEC, which are dependent on these networks to maintain a cadence of new products every 18-24 months. Japan’s action to place export controls on critical chemical inputs for South Korean semiconductor firms in the summer of 2019 serves as a warning of the supply chain’s vulnerability to miscalculated policy. In short, Washington and Tokyo must tread carefully. Without support from other key actors like South Korea, Taiwan, and the Netherlands, and by failing to incorporate industry input, poorly calibrated export controls on semiconductors could severely damage U.S. and Japanese companies’ competitiveness.     

A third course out of the bind for semiconductor firms may be available: a combination of on-shoring, staying in China, and relocation. For semiconductor companies, the relocation portion will not happen overnight. Shifting supply chains takes time for a capital-intensive industry driven by know-how that has limited redundancy. Destinations worth exploring from both cost and security perspectives as alternatives to China include South and Southeast Asia. Specific ASEAN countries, namely Vietnam, Malaysia, Thailand, and Singapore, offer good prospects for investment. There is an existing industry presence in several locations in the region. Multinational firms already operating in Malaysia, Thailand, and Vietnam have benefited from diversification during the ongoing U.S.-China trade war, but are still dependent on Chinese inputs. Shifting low-value operations to Southeast Asia, such as systems integration, could likely be done relatively quickly – and some firms have – but shifting or adding additional high-value nodes such as back-end (assembly, packaging, and testing) facilities to the region will require incentives and support. At a minimum, a dedicated, coordinated effort on the part of the United States and Japan is essential to improve the investment environment.   

How can the United States and Japan help? Programs and initiatives are needed to address myriad weaknesses in Southeast Asia. Semiconductor manufacturing requires robust infrastructure, for example stable electricity supply, deep logistical networks, a large talent pool of engineers and STEM workers, and a technology ecosystem that includes startups and small or medium enterprises to fill gaps and provide innovations. The United States and Japan can fund high quality infrastructure, frame curriculum for semiconductor industry training through public-private partnerships, and help build capacity in logistical, regulatory, and judiciary systems.   

The burden in many of these areas will fall on specific Southeast Asian governments themselves, but the United States and Japan should assist. Effectively diversifying the regional technology supply chain to mitigate the impact of pending and future shocks may depend on it.

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Baliga, B. Jayant, 1948- author

Barker Library - QC176.8.N35 C43 2013

Hayden Library - TK7874.85.S474 2012

Hayden Library - TK7874.85.M425 2014

Barker Library - TK7874.85.S45 2015

Hayden Library - TK7874.85.S473 2014

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Hayden Library - QH515.S46 2018

Ndebeka-Bandou, Camille, 1987- author

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IEEE / Institute of Electrical and Electronics Engineers Incorporated