In last week's post, 1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones . I covered 1G mobile, the first analog standards. Then we went digital. 2G The Nordic countries...

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Key findings: 5X to 32X faster low-power verification using Palladium XP emulation

It’s hot in July in Korea, and not just the temperature; the ideas, too. The ideas that flowed at CDNLive Korea were exciting, and that includes a very interesting talk by Jiyeon Park from the System LSI division of Samsung Electronics.  His talk, titled “Enabling Low-Power Verification using Cadence Palladium XP,” struck a chord with the audience and the highlights bear sharing in this forum. This blog captures some of the highlights from the public talk in Seoul this summer.

Motivation

If you are familiar with the breadth of the product lines at Samsung Electronics, you will appreciate the diversity of the end-market requirements that they must fulfill. These markets and products include:

Mobile/Handheld

• Smartphones
• Tablets
• Laptops

Consumer/Digital Home

• High-definition/ultra-high-definition TV
• Gaming consoles
• Computers 

Networking/Data Center

• Servers
• Switches
• Communications

What all of these markets have in common is that energy efficiency is now an integral and leading part of the value equation. For design teams, a good knowledge of power helps the evaluation and use of a host of critical decisions. From design architecture, IP make-versus-buy decisions, and manufacturing process selection, to the use of low-power design techniques, all are critically influenced by power.

Using simulation for low-power verification

Once the decision to overlay power reduction design techniques, such as power shutdown, has been made, new dimensions have been added to the already complex SoC verification task. The RTL verification environment is first augmented with a power intent file; in this case, IEEE 1801 was the format.  The inclusion of this power intent information enables the examination of power domain shutdown, isolation operations, proper retention, and level shifting.

Figure 1: Incisive SimVision power verification elements example

Low-power verification using emulation

Simulation for low-power verification works well, so why emulation? One word—complexity!  It is easy to forget that “design complexity” (usually measured in gates or transistors) is not that same as “verification complexity” (which is really hard to measure). Consider a design with four power domains, three of which are switchable and one that is switchable but also has high- and low-voltage states. That yields nine basic states, and 24 modes of operation to test. Although some of those modes may not be consequential, when paired with hundreds or even thousands of functional tests, you can begin to understand the impact of overlaying low power on the verification problem. Thus, it becomes very desirable to enlist the raw computational power of emulation.

Power off/on scenario on Palladium XP platform

A typical functional test would be augmented to include the power control signals. For power shutoff verification, for instance, the cycles for asserting isolation begin the sequence, followed by state retention, and then finally a power shutdown of the domain must be asserted to verify operation. The figure below calls out a number of checks that ought to be performed.

Figure 2: Power shutoff sequence and associated checks to make

IEEE 1801 support in Palladium XP platform

The IEEE 1801 support found in the Palladium PX platform includes some noteworthy capabilities, as well as some implications to the user. First is a patented memory randomization provided by the Palladium XP platform. This capability includes randomization of memory during shutdown and power up, control over read value during the power-off state, non-volatile memory state retention, and freezing of data on retention. The user should be aware there is about a 10%-20% capacity overhead associated with IEEE 1801-driven low-power verification.

Figure 3: Palladium low-power verification enables schedule improvement

Palladium low-power verification flow

The great thing about the emulation work flow for IEEE 1801 power verification is that the only change is to include that IEEE 1801 power intent file during the compilation stage!

Considerations for emulation environment bring-up

A Universal Verification Methodology (UVM) approach was taken by the Samsung team. This provides a unique structure to the testbench environment that is very conducive to a metric-driven methodology.  Using a testbench acceleration interface, teams can run the testbench on a software simulator and the design on the emulator. In addition, the formalism allows for the case of incomplete designs that do not hinder the verification of the parts that are completed.

Experimental results

The most exciting part of the paper was the results that were obtained. For a minor overhead cost in compile time and capacity, the team was able to improve runtimes of their tests by 5X to 32X. Being able run tests in a fraction of the time, or many more tests in the same time, has always been a benefit for emulation users. Now low-power verification is a proven part of the value provided to Palladium XP platform users.

Figure 4: Samsung low-power verification emulation results

Conclusions

The key conclusions found were:

• No modification was needed for IEEE 1801
• There is a small capacity and compile time overhead
• The emulation and simulation match
• The longer the test, the more the net speed up versus software simulation
• Run times improved from 5X to 32X!

With this flow in place, the teams has begun power-aware testing that includes firmware and software verification to go along with the hardware testing. This expansion enables more capability in optimization of the power architecture. In addition, they are seeing faster silicon bring-up in the context of an applied low-power strategy.

Steve Carlson

hi everyone, 

i'm trying to create a netlist for aging simulation. i would like to simulate how power, Gain and PAE (efficiency) are inlfuenced after 3 hours

i would be grateful if someone can correct my syntax in the netlist since i'm trying to make a sweep HB  simulation where the input power is the parameter.

i did it without any error for the sp (S parameters)  simulation.

you can see the images for both sp and hb simulation netlists. (from left to right: sp aging netlist; hb aging netlist)

i will be grateful if someone can provide me some syntax advices.

thanks,

best regards

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it.

In my coverage bin I can create a range like this A => [queue1Enum[0]:queue1Enum[$]] => [queue2Enum[0]:queue2Enum[$]]. But I only get first and last element then.

typedef enum { red, d_green, d_blue, e_yellow, e_white, e_black } Colors;
 Colors dColors[$];
 Colors eColors[$];
 Lcolors = Colors.first();
 do begin
  if (Lcolors[0].name=='d') begin
   dColors.push_back(Lcolors);
  end
  if (Lcolors[0].name=='e') begin
   eColors.push_back(Lcolors);
  end
 end while(Lcolors != Lcolors.first())

 covergroup cgTest with function sample(Colors c);
   cpTran : coverpoint c{
      bins t[] = (red => dColors =>eColors);   
   }
 endgroup

I have a question regarding simulating IBIS model using Spectre.  IBIS model generation always has the die capacitance included and in the generated IBIS file you will have this value as  “C_comp” value.  Does the Spectre accounts for this capacitance from the IBIS file while computing the time domain voltage waveform during simulation ?  If I add additional capacitance outside in the testbench, to model the die capacitance, then it will be double counting.

Does anyone know if Spectre is already accounting this C_comp during the time domain voltage wave computation from IBIS file, during simulation ?

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.(read more)

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.(read more)

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

• Is there any scope to improve power consumption of my design?
• What is the best-case power?
• Pin-point hot spots in my design?
• How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based, where analysis is done by Joules and is explored/implemented by user.

Power Exploration capabilities include:

• Efficiency metrics
• Pin point RTL location
• Cross probe to stim
• Centralize all power data

 Do you want to explore more? What is the flow? What commands can be used?

There is a ONE-STOP solution to all these queries in the form of videos on Joules Power Exploration features on https://support.cadence.com (Cadence login required).

Video Links:

How to Analyze Ideal Power Using Joules RTL Power Solution GUI? (Video)

What is Ideal Power Analysis Flow in Joules RTL Power Solution? (Video)

How to Apply Observability Don’t Care (ODC) Technique in Joules? (Video)

How to Debug Wasted Power Using Ideal Power Analyzer Window in Joules GUI? (Video)

Related Resources

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

A recap of the blogs published in the Library Characterization Tidbits blog series.(read more)

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.(read more)

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visit News18 Urdu for latest news, breaking news, news headlines and updates from Sant Kabir Nagar on politics, sports, entertainment, cricket, crime and more.

CDS Bipin Rawan: Air Force રવિવારે કોરોના યોદ્ધાઓને સલામ કરવા Flypast કરશે

સામાન્ય રીતે ઘઉં વધારે ગરમ વિસ્તારમાં પેદા નથી થઈ શકતા. તેના કારણે ભારત જેવા દેશમાં આ પાક માત્ર શિયાળામાં ઉગાડવામાં આવે છે

visit News18 Urdu for latest news, breaking news, news headlines and updates from Kaushambi on politics, sports, entertainment, cricket, crime and more.

SBIના ગ્રાહકો આ 5 સ્ટેપ્સનો ઉપયોગ કરી આપના એકાઉન્ટને લગતી જરૂરી સેવાઓનો ઉપયોગ કરી શકશો

રેપો રેટમાં ઘટાડાનો ફાયદો હોમ, કાર કે અન્ય પ્રકારની લોન સહિત અનેક પ્રકારની ઈએમઆઈ ભરનારા કરોડો લોકોને મળવાની આશા છે

રિઝર્વ બેંકના આવી છૂટ બાદ લોન અને ક્રેડિટ કાર્ડ ધારકોના દિમાગમાં અનેક પ્રશ્નો ઉદભવ્યા છે. જો તમને પણ કોઈ મૂંઝવણ છે તો નીચે આપેલા સવાલ-જવાબથી તમારી શંકા કે પ્રશ્નનું સમાધન મેળવી શકો છો.

RBIએ શુક્રવારે બેંકોને તેમના ગ્રાહકોને ટર્મ લોનના EMI ચૂકવવામાં ત્રણ મહિનાની મુદત આપવાની છૂટ આપી છે.

લોકડાઉનના સમય વચ્ચે દેશની સૌથી મોટી બેન્ક એસબીઆઈએ હોમ લોન અને કાર લોનનો વ્યાજ દર ઓછો કરી દીધો છે. બીજી તરફ બચત ઉપર કાતર પણ ફેરવી દીધી છે. એસબીઆઈએ છૂટક એફડી વ્યાજદર ઓછો કરી દીધો છે.

બેન્ક ઓફ ઈન્ડીયાએ રિઝર્વ બેન્ક (RBI) દ્વારા નીતિગત વ્યાજદરમાં ઘટાડાનો પૂરો લાભ ગ્રાહકોને આપવાનો નિર્ણય લેવામાં આવ્યો છે.

કોરોના વાયરસ મહામારીથી બચવા માટે સાવધાની વર્તવા અંગે ભારતીય રિઝર્વ બેન્કના ગવર્નર શક્તિકાંત દાસે સામાન્ય લોકો માટે ખાસ વીડિયો રજૂ કર્યો છે. શક્તિકાંત દાસે આ વીડિયો પોતાના ટ્વિટર હેન્ડલ ઉપર રજૂ કર્યો છે.

વાર્ષિક ધોરણે ગણતરી કરવામાં આવે તો ક્રેડિટ કાર્ડની બાકી રકમ પર વ્યાજનો દર 40 ટકા આસપાસ થયો હોય છે.

Coronavirus: ફ્રૉડથી બચવા માટે દેશની સૌથી મોટી સરકારી બેંક એસબીઆઈએ મહત્વની જાણકારી શેર કરી.

Amazon, BigBasket, Grofers અને MedLife, લોકડાઉન દરમિયાન જીવના જોખમે ડિલિવરી કરતા બહાદૂુરોને બિરદાવે છે.

કોરોના સંકટ વચ્ચે RBIએ આપી મોટી રાહત, રિવર્સ રેપો રેટ 0.25 ટકા ઘટાડ્યો

RBI ગવર્નર શક્તિકાંત દાસે રિવર્સ રેપો રેટમાં 0.25 ટકાના ઘટાડાની મોટી જાહેરાત કરી

RBIએ વ્યાજ દર ઘટાડ્યા, સામાન્ય નાગરિકો અને અર્થવ્યવસ્થા પર શું થશે અસર?

રિઝર્વ બેંક ઓફ ઈન્ડિયાએ કરેલી મોટી જાહેરાતોના કારણે અર્થવ્યવસ્થામાં વેગ આવશે તેવી વડાપ્રધાન મોદીને આશા

યૂએસ બેઝ્ડ મ્યુચ્યુઅલ ફંડ હાઉસ ફ્રેન્કલિન ટેમ્પલટને ભારતમાં 6 Debt Fundsને બંધ કરી દેતાં રોકાણકારોના કરોડો રૂપિયા ફસાયા

BIFનું માનવું છે કે ફેસબુક અને જિયો વચ્ચેની પાર્ટનરશીપ 5 કરોડ માઇક્રો, નાના અને મધ્યમ વેપારોને ફાયદો અપાવશે

સીકેપી સહકારી બેંક (CKP Cooperative Bank Limited)નું લાઇસન્સ રદ. મનીકંટ્રોલના જણાવ્યા પ્રમાણે બેંકના આશરે સવા લાખ ખાતાધારકો પર સંકટ.

લૉકડાઉન વચ્ચે ઠગોએ બેંક ગ્રાહકો સાથે છેતરપિંડી કરવાની નવી જ રીત શોધી કાઢી, એસબીઆઈ તરફથી ચેતવણી જાહેર કરવામાં આવી.

આ બેન્ક દ્વારા MCLRમાં સતત 12મી વખત અને નાણાંકિય વર્ષ 2020-21માં બીજી વખત ઘટાડો કર્યો છે. ઉલ્લેખનીય છે કે આ પહેલા એપ્રિલમાં એસબીઆઈએ વ્યાજદરોમાં 0.35 ટકાનો ઘટાડો કર્યો હતો.