By Tom Garry, in Salford

If rumours are true and this one should be, I started it, we have a special edition of the Weekend show where we talk about the evolution of the role of the CIO with two incredible CIOs as the CIO Association of Canada turns 20. Don’t miss it.  MUSIC UP Can HP make you love […]

In a new report, KPMG has broken down the provincial adoption rate of generative AI across Canada, and found that Quebec led with 26 per cent, ahead of Alberta (23 per cent), British Columbia (22 per cent) and Ontario (20.5 per cent), which nearly tied with Saskatchewan and Manitoba. Atlantic Canada saw the lowest adoption […]

Ransomware is behind the cyber attack on the city of Hamilton, Ont., the municipality’s city manager says. Marnie Cluckie told reporters Monday afternoon that the attack, which was detected the evening of Sunday, Feb. 25, was the result of ransomware. She wouldn’t say what strain of the malware the city has been hit with, how […]

Canada’s national anti-money laundering agency has been hit by a cyber attack. The Financial Transactions and Reports Analysis Centre of Canada (FINTRAC) said Tuesday that over the last 24 hours it has been managing a cyber incident. “The incident does not involve the centre’s intelligence or classified systems,” it said in a statement. “As a […]

A pilot program aimed at training women and non-binary persons for careers in cybersecurity will soon start recruiting its third group of students. The program, offered to students in computer science and related courses in seven Canadian post-secondary institutions, should start looking for candidates next month for the fall academic year, said Vivian Lee, team […]

Artificial intelligence can be the key to unlocking better relationships with work, HP revealed in its new Work Relationship Index (WRI) report. “AI represents a significant opportunity to transform our work dynamics and unlock a more positive and productive environment for all,” stated Dave Shull, president of HP Workforce Solutions at HP Inc.. “To foster […]

A bold new study in Physical Review suggests that a wobble detected in Mars' orbit could be the result of dark matter made up of primordial black holes.

A coronal mass ejection could strike the Earth's magnetosphere this week and cause a geomagnetic storm due to conditions caused by the autumnal equinox.

A spike in earthquakes at Mount Adams, a volcano in Washington state, prompted scientists to install additional monitoring instruments to assess the seismic activity.

Two pioneers of artificial intelligence have won the Nobel Prize in physics for discoveries and inventions that formed the building blocks of machine learning.

SpaceX pulled off a stunning achievement this week, conducting four launches in less than 48 hours with huge implications for the future of space exploration.

Jill Parton, 46, suffered fatal injuries when she was hit by a freight train in Heaton Chapel in the early hours of June 3 this year, an inquest heard

$329/£300 graphics card is said to be "future ready" for your 1080p gaming needs.

A new genus and species of early-diverging oviraptorosaurian dinosaur has been identified from two specimens found in Inner Mongolia, China.

The post New Oviraptorosaur Species Discovered in China appeared first on Sci.News: Breaking Science News.

Scientists from the Leibniz Zentrum für Archäologie and Durham University have examined a collection of 406 engraved schist plaquettes found at the Magdalenian site of Gönnersdorf in Germany.

The post 15,800-Year-Old Engraved Plaquettes Shed Light on Paleolithic Fishing Techniques appeared first on Sci.News: Breaking Science News.

Human cognitive performance can be significantly influenced by the presence of audience members.

The post Study: Chimps Perform Better on Challenging Computer Tasks When They Have Audience appeared first on Sci.News: Breaking Science News.

The World Health Organization has declared mpox a public health emergency of international concern – a new variant of the virus has caused an outbreak in Central and West Africa and spread to Sweden

In children aged 6 to 11, long covid seems to often present as sleep problems or abdominal issues, while adolescents report fatigue and pain

Medical clowns, who play with children in hospitals, may help them be discharged sooner by reducing their heart rates

Interacting with animals seems to provide emotional support to young people with a serious illness, even when the contact is via letters and not face to face

Systems that can harvest water from moisture in the atmosphere could offer a valuable water source in the wake of disasters

A researcher who underwent dozens of brain scans discovered that the volume of her cerebral cortex was 1 per cent lower when she took hormonal contraceptives

Weaving tales of magical fruit and vegetables into your children's stories may encourage them to eat healthy snacks

Most ingredients touted as the key to better health fail to live up to the hype but fibre bucks this trend, with benefits for the whole body, not just the gut

The health benefits of fermented food and drink have long been touted, but firm evidence in favour of kombucha, sauerkraut and kefir is surprisingly elusive

Running, swimming, HIIT or walking – what is the best way to work out? The answer is complicated, and depends on the person, finds Grace Wade

Blood tests have shown that about 7 per cent of workers on dairy farms that had H5N1 outbreaks had antibodies against the disease

Speculation has already run rampant on who Florida Gov. Ron DeSantis will appoint to replace Sen. Marco Rubio if Rubio becomes President-elect Trump's secretary of state.

Immigration and Customs Enforcement has arrested another illegal immigrant charged with child sex offenses, as the state's governor says police won't help the Trump administration.

William McGinley is returning to the Trump White House to serve as his White House Counsel, President-elect Trump announced.

Various Cook Children’s locations are experiencing a spike in cases of salmonella, but the Texas Department of State Health Services has not reported an outbreak.     Since July, the Emergency Department at Cook Children’s Medical Center – Fort Worth has also reported increased numbers of patients with salmonella.   “In... Continue Reading

Researchers from the Centers for Disease Control and Prevention have uncovered critical links between socioeconomic factors — such as income, education level, and poverty — and an increased risk of Salmonella infections linked to ground beef consumption.  In a study published in the Journal of Food Protection, CDC researchers reported... Continue Reading

Myah Saakwa-Mante, a 20-year-old British university student, was caught at Los Angeles International Airport and arrested after allegedly attempting to smuggle T-shirts soaked with methamphetamine.

'Gutfeld!' panelists react to President-elect Trump's choice for 'border czar.'

In the first quarter of Monday's Dolphins-Rams game, ESPN reported that Tyreek Hill said a torn ligament in his wrist became worst after he was detained by police.

Quantum computing is a devilishly complex technology, with many technical hurdles impacting its development. Of these challenges two critical issues stand out: miniaturization and qubit quality.

IBM has adopted the superconducting qubit road map of reaching a 1,121-qubit processor by 2023, leading to the expectation that 1,000 qubits with today’s qubit form factor is feasible. However, current approaches will require very large chips (50 millimeters on a side, or larger) at the scale of small wafers, or the use of chiplets on multichip modules. While this approach will work, the aim is to attain a better path toward scalability.

Now researchers at MIT have been able to both reduce the size of the qubits and done so in a way that reduces the interference that occurs between neighboring qubits. The MIT researchers have increased the number of superconducting qubits that can be added onto a device by a factor of 100.

“We are addressing both qubit miniaturization and quality,” said William Oliver, the director for the Center for Quantum Engineering at MIT. “Unlike conventional transistor scaling, where only the number really matters, for qubits, large numbers are not sufficient, they must also be high-performance. Sacrificing performance for qubit number is not a useful trade in quantum computing. They must go hand in hand.”

The key to this big increase in qubit density and reduction of interference comes down to the use of two-dimensional materials, in particular the 2D insulator hexagonal boron nitride (hBN). The MIT researchers demonstrated that a few atomic monolayers of hBN can be stacked to form the insulator in the capacitors of a superconducting qubit.

Just like other capacitors, the capacitors in these superconducting circuits take the form of a sandwich in which an insulator material is sandwiched between two metal plates. The big difference for these capacitors is that the superconducting circuits can operate only at extremely low temperatures—less than 0.02 degrees above absolute zero (-273.15 °C).

Superconducting qubits are measured at temperatures as low as 20 millikelvin in a dilution refrigerator.Nathan Fiske/MIT

In that environment, insulating materials that are available for the job, such as PE-CVD silicon oxide or silicon nitride, have quite a few defects that are too lossy for quantum computing applications. To get around these material shortcomings, most superconducting circuits use what are called coplanar capacitors. In these capacitors, the plates are positioned laterally to one another, rather than on top of one another.

As a result, the intrinsic silicon substrate below the plates and to a smaller degree the vacuum above the plates serve as the capacitor dielectric. Intrinsic silicon is chemically pure and therefore has few defects, and the large size dilutes the electric field at the plate interfaces, all of which leads to a low-loss capacitor. The lateral size of each plate in this open-face design ends up being quite large (typically 100 by 100 micrometers) in order to achieve the required capacitance.

In an effort to move away from the large lateral configuration, the MIT researchers embarked on a search for an insulator that has very few defects and is compatible with superconducting capacitor plates.

“We chose to study hBN because it is the most widely used insulator in 2D material research due to its cleanliness and chemical inertness,” said colead author Joel Wang, a research scientist in the Engineering Quantum Systems group of the MIT Research Laboratory for Electronics.

On either side of the hBN, the MIT researchers used the 2D superconducting material, niobium diselenide. One of the trickiest aspects of fabricating the capacitors was working with the niobium diselenide, which oxidizes in seconds when exposed to air, according to Wang. This necessitates that the assembly of the capacitor occur in a glove box filled with argon gas.

While this would seemingly complicate the scaling up of the production of these capacitors, Wang doesn’t regard this as a limiting factor.

“What determines the quality factor of the capacitor are the two interfaces between the two materials,” said Wang. “Once the sandwich is made, the two interfaces are “sealed” and we don’t see any noticeable degradation over time when exposed to the atmosphere.”

This lack of degradation is because around 90 percent of the electric field is contained within the sandwich structure, so the oxidation of the outer surface of the niobium diselenide does not play a significant role anymore. This ultimately makes the capacitor footprint much smaller, and it accounts for the reduction in cross talk between the neighboring qubits.

“The main challenge for scaling up the fabrication will be the wafer-scale growth of hBN and 2D superconductors like [niobium diselenide], and how one can do wafer-scale stacking of these films,” added Wang.

Wang believes that this research has shown 2D hBN to be a good insulator candidate for superconducting qubits. He says that the groundwork the MIT team has done will serve as a road map for using other hybrid 2D materials to build superconducting circuits.

The end of Moore’s Law is looming. Engineers and designers can do only so much to miniaturize transistors and pack as many of them as possible into chips. So they’re turning to other approaches to chip design, incorporating technologies like AI into the process.

Samsung, for instance, is adding AI to its memory chips to enable processing in memory, thereby saving energy and speeding up machine learning. Speaking of speed, Google’s TPU V4 AI chip has doubled its processing power compared with that of its previous version.

But AI holds still more promise and potential for the semiconductor industry. To better understand how AI is set to revolutionize chip design, we spoke with Heather Gorr, senior product manager for MathWorks’ MATLAB platform.

How is AI currently being used to design the next generation of chips?

Heather Gorr: AI is such an important technology because it’s involved in most parts of the cycle, including the design and manufacturing process. There’s a lot of important applications here, even in the general process engineering where we want to optimize things. I think defect detection is a big one at all phases of the process, especially in manufacturing. But even thinking ahead in the design process, [AI now plays a significant role] when you’re designing the light and the sensors and all the different components. There’s a lot of anomaly detection and fault mitigation that you really want to consider.

Heather GorrMathWorks

Then, thinking about the logistical modeling that you see in any industry, there is always planned downtime that you want to mitigate; but you also end up having unplanned downtime. So, looking back at that historical data of when you’ve had those moments where maybe it took a bit longer than expected to manufacture something, you can take a look at all of that data and use AI to try to identify the proximate cause or to see something that might jump out even in the processing and design phases. We think of AI oftentimes as a predictive tool, or as a robot doing something, but a lot of times you get a lot of insight from the data through AI.

What are the benefits of using AI for chip design?

Gorr: Historically, we’ve seen a lot of physics-based modeling, which is a very intensive process. We want to do a reduced order model, where instead of solving such a computationally expensive and extensive model, we can do something a little cheaper. You could create a surrogate model, so to speak, of that physics-based model, use the data, and then do your parameter sweeps, your optimizations, your Monte Carlo simulations using the surrogate model. That takes a lot less time computationally than solving the physics-based equations directly. So, we’re seeing that benefit in many ways, including the efficiency and economy that are the results of iterating quickly on the experiments and the simulations that will really help in the design.

So it’s like having a digital twin in a sense?

Gorr: Exactly. That’s pretty much what people are doing, where you have the physical system model and the experimental data. Then, in conjunction, you have this other model that you could tweak and tune and try different parameters and experiments that let sweep through all of those different situations and come up with a better design in the end.

So, it’s going to be more efficient and, as you said, cheaper?

Gorr: Yeah, definitely. Especially in the experimentation and design phases, where you’re trying different things. That’s obviously going to yield dramatic cost savings if you’re actually manufacturing and producing [the chips]. You want to simulate, test, experiment as much as possible without making something using the actual process engineering.

We’ve talked about the benefits. How about the drawbacks?

Gorr: The [AI-based experimental models] tend to not be as accurate as physics-based models. Of course, that’s why you do many simulations and parameter sweeps. But that’s also the benefit of having that digital twin, where you can keep that in mind—it’s not going to be as accurate as that precise model that we’ve developed over the years.

Both chip design and manufacturing are system intensive; you have to consider every little part. And that can be really challenging. It’s a case where you might have models to predict something and different parts of it, but you still need to bring it all together.

One of the other things to think about too is that you need the data to build the models. You have to incorporate data from all sorts of different sensors and different sorts of teams, and so that heightens the challenge.

How can engineers use AI to better prepare and extract insights from hardware or sensor data?

Gorr: We always think about using AI to predict something or do some robot task, but you can use AI to come up with patterns and pick out things you might not have noticed before on your own. People will use AI when they have high-frequency data coming from many different sensors, and a lot of times it’s useful to explore the frequency domain and things like data synchronization or resampling. Those can be really challenging if you’re not sure where to start.

One of the things I would say is, use the tools that are available. There’s a vast community of people working on these things, and you can find lots of examples [of applications and techniques] on GitHub or MATLAB Central, where people have shared nice examples, even little apps they’ve created. I think many of us are buried in data and just not sure what to do with it, so definitely take advantage of what’s already out there in the community. You can explore and see what makes sense to you, and bring in that balance of domain knowledge and the insight you get from the tools and AI.

What should engineers and designers consider when using AI for chip design?

Gorr: Think through what problems you’re trying to solve or what insights you might hope to find, and try to be clear about that. Consider all of the different components, and document and test each of those different parts. Consider all of the people involved, and explain and hand off in a way that is sensible for the whole team.

How do you think AI will affect chip designers’ jobs?

Gorr: It’s going to free up a lot of human capital for more advanced tasks. We can use AI to reduce waste, to optimize the materials, to optimize the design, but then you still have that human involved whenever it comes to decision-making. I think it’s a great example of people and technology working hand in hand. It’s also an industry where all people involved—even on the manufacturing floor—need to have some level of understanding of what’s happening, so this is a great industry for advancing AI because of how we test things and how we think about them before we put them on the chip.

How do you envision the future of AI and chip design?

Gorr: It’s very much dependent on that human element—involving people in the process and having that interpretable model. We can do many things with the mathematical minutiae of modeling, but it comes down to how people are using it, how everybody in the process is understanding and applying it. Communication and involvement of people of all skill levels in the process are going to be really important. We’re going to see less of those superprecise predictions and more transparency of information, sharing, and that digital twin—not only using AI but also using our human knowledge and all of the work that many people have done over the years.

This is a sponsored article brought to you by BESydney.

In July 2024, Sydney woman Katherine Bennell-Pegg made history as the first astronaut to graduate under the Australian flag and the first female astronaut in Australia. Her journey, marked by determination and discipline, showcases Australia’s growing prominence in space exploration and research.

From her academic achievements at the University of Sydney (USYD) to her rigorous training at the European Space Agency (ESA), Bennell-Pegg’s success has paved a path forward for aspiring space and aerospace professionals in Australia and globally.

A journey to the stars begins in Sydney

Katherine Bennell-Pegg was born in Sydney, New South Wales, and grew up in the Northern Beaches area. Her fascination with space began at an early age.

“I always dreamed of being an astronaut,” Bennell-Pegg shared in her “Insights from an Australian Astronaut” Space Forum Speech in July 2024. “When I was young, it was for the adventure, but after more than a decade working in space, it’s now because I know the role it plays in tackling real-world problems and developing new knowledge that can benefit our society, environment and science.”

Sydney: A Hub for Space Innovation

Sydney, the vibrant heart of the state of New South Wales (NSW), stands at the forefront of aerospace innovation in Australia. With its world-class research facilities, leading academic institutions and strategic geographic positioning, Sydney is not only Australia’s gateway to the Indo-Pacific but also a burgeoning hub for international aerospace endeavours.

NSW is home to more than 40 per cent of Australia’s aerospace industry. Substantial investments from both the state and federal governments support this concentration of capabilities, underpinning Sydney’s role as a leader in aerospace. From advanced manufacturing and cybersecurity to quantum technologies and space exploration, this progressive city is truly thriving.

Sydney’s appeal as a desirable location for hosting aerospace conferences and business events is bolstered by its comprehensive infrastructure, vibrant startup community and strategic position as a transport hub.

Sydney’s track record of successfully hosting events highlights the city’s ability to organise impactful international gatherings, including:

• Australian Space Summit
• New Horizons Summit
• CubeSatPlus2024 - NEW SPACE: Unbounded Skies

Sydney will also host the 76th International Astronautical Congress from 29 September to 3 October 2025 and the 34th Congress of the International Council for the Aeronautical Sciences (ICAS) to be held 13 to 17 September 2026. Both will take place at ICC Sydney, further solidifying Sydney’s status as a central hub for aerospace events.

Would you like to know more about Sydney’s credentials in Aerospace? Download our Aerospace eBook or visit besydney.com.au

Sydney proved to be the ideal location for Bennell-Pegg’s journey to begin. She studied at the University of Sydney, where she earned a Bachelor of Engineering (Honors) in Aeronautical Engineering (Space) and a Bachelor of Science (Advanced) in Physics.

Sydney’s universities are at the forefront of aerospace education and research. Institutions such as the University of Sydney (USYD), the University of New South Wales (UNSW Sydney) and the University of Technology Sydney (UTS) attract students from around the world. UNSW Sydney, with its School of Aerospace, Mechanical, and Mechatronic Engineering, is renowned for its innovative research in space technology and satellite systems, while UTS provides cutting-edge programs in aerospace engineering and physics, emphasizing practical applications and industry partnerships. USYD excels in aeronautical engineering and space science, supported by advanced facilities and strong ties to major aerospace organisations. Together, these universities offer comprehensive programs that integrate theoretical knowledge with hands-on experience, preparing students for dynamic careers in the rapidly evolving aerospace and space sectors.

Having excelled in her studies at USYD, Bennell-Pegg was awarded the Charles Kuller Graduation Prize for her top-placed undergraduate thesis. Subsequently, her quest for knowledge took her to Europe, where she earned two Master of Science degrees: one in Astronautics and Space Engineering from Cranfield University and another in Space Technology from Luleå University of Technology.

Reflecting on her educational path, Bennell-Pegg stated, “With the encouragement of my parents, I researched what it would take to become an astronaut and worked hard at school, participating in everything from aerobatic flying lessons to amateur astronomy.”

Inside the rigorous training regimen of an astronaut

Bennell-Pegg’s professional career began with roles at Airbus UK, where she contributed to numerous space missions and concept studies, such as Martian in-situ resource utilisation and space debris removal. Her expertise led her to the Australian Space Agency, where she became the Director of Space Technology.

In 2021, Bennell-Pegg was invited by the European Space Agency (ESA) to undertake Basic Astronaut Training at the European Astronaut Centre in Germany. When the ESA application opened in 2021, it was the first opening in 15 years. Bennell-Pegg jumped at the opportunity to apply alongside over 22,000 others from 22 countries. She endured six knock-out rounds, including medical, psychometrics, psychology and technical tests and made it to the group of 25 who passed.

This historic invitation marked the first time an international astronaut candidate was offered training by the ESA.

“The training was demanding, but it was also an incredible opportunity to learn from some of the best minds in the field and to be part of a team that is pushing the boundaries of human exploration.”—Katherine Bennell-Pegg

Bennell-Pegg’s training regimen was intense, encompassing physical conditioning, complex simulations, and theoretical classes designed to prepare candidates for long-duration missions to the International Space Station (ISS) and beyond. This included:

• Studies in biology, astronomy, earth sciences, meteorology, materials, medical and fluids, both in theory and in labs.
• Radiation research – an area of expertise for Australia. This will increase as humans travel back to the Moon.
• Medical operations: Astronauts need to be able to perform medical procedures on themselves and others.
• Training for expeditions: This included honing team dynamics through behavioral training, ocean and winter survival training, rescue and firefighting.

Sharing her thoughts on this transformative experience, Bennell-Pegg said, “The training was demanding, but it was also an incredible opportunity to learn from some of the best minds in the field and to be part of a team that is pushing the boundaries of human exploration.”

In April 2024, Bennell-Pegg completed her training, graduating with her ESA classmates from “The Hoppers” group. Upon graduation, she became fully qualified for assignments on long-duration missions to the ISS, making her the first Australian female astronaut and the first person to train as an astronaut under the Australian flag.

“I want to use this experience to open doors for Australian scientists and engineers to utilize space for their discoveries,” Bennell-Pegg said. “I hope to inspire the pursuit of STEM careers and show all Australians that they too can reach for the stars.”

Elevating Australia’s role in space exploration

Katherine Bennell-Pegg’s achievements represent a significant milestone. Her journey from the University of Sydney to the rigorous training programs at the European Astronaut Centre showcases the potential of Australian talent in the global space community.

“Being the first astronaut trained under the Australian flag is an incredible honor,” Bennell-Pegg said. “I’m grateful for the support that has fueled me through intense training and opened doors for more Australians in space exploration. Whether I fly or not, there is much to accomplish here on Earth. I’m excited to leverage this experience to inspire future generations in STEM and elevate Australia’s presence in the global space community. Becoming an astronaut is just the beginning.”

Bennell-Pegg’s dream to become an Australian astronaut is more than just a personal triumph; it is a win for anyone who aspires to a career in space or aerospace. Sydney, with its world-class educational institutions, advanced manufacturing facilities scheduled for the Western Sydney Aerotropolis and expanding opportunities in aerospace and defence, is an ideal starting point for anyone looking to make their mark in these sectors.

Would you like to know more about Sydney’s credentials in Aerospace? Download our Aerospace eBook or visit besydney.com.au

Last week the organization tasked with running the the biggest chunk of U.S. CHIPS Act’s US $13 billion R&D program made some significant strides: The National Semiconductor Technology Center (NSTC) released a strategic plan and selected the sites of two of three planned facilities and released a new strategic plan. The locations of the two sites—a “design and collaboration” center in Sunnyvale, Calif., and a lab devoted to advancing the leading edge of chipmaking, in Albany, N.Y.—build on an existing ecosystem at each location, experts say. The location of the third planned center—a chip prototyping and packaging site that could be especially critical for speeding semiconductor startups—is still a matter of speculation.

“The NSTC represents a once-in-a-generation opportunity for the U.S. to accelerate the pace of innovation in semiconductor technology,” Deirdre Hanford, CEO of Natcast, the nonprofit that runs the NSTC centers, said in a statement. According to the strategic plan, which covers 2025 to 2027, the NSTC is meant to accomplish three goals: extend U.S. technology leadership, reduce the time and cost to prototype, and build and sustain a semiconductor workforce development ecosystem. The three centers are meant to do a mix of all three.

New York gets extreme ultraviolet lithography

NSTC plans to direct $825 million into the Albany project. The site will be dedicated to extreme ultraviolet lithography, a technology that’s essential to making the most advanced logic chips. The Albany Nanotech Complex, which has already seen more than $25 billion in investments from the state and industry partners over two decades, will form the heart of the future NSTC center. It already has an EUV lithography machine on site and has begun an expansion to install a next-generation version, called high-NA EUV, which promises to produce even finer chip features. Working with a tool recently installed in Europe, IBM, a long-time tenant of the Albany research facility, reported record yields of copper interconnects built every 21 nanometers, a pitch several nanometers tighter than possible with ordinary EUV.

“It’s fulfilling to see that this ecosystem can be taken to the national and global level through CHIPS Act funding,” said Mukesh Khare, general manager of IBM’s semiconductors division, speaking from the future site of the NSTC EUV center. “It’s the right time, and we have all the ingredients.”

While only a few companies are capable of manufacturing cutting edge logic using EUV, the impact of the NSTC center will be much broader, Khare argues. It will extend down as far as early-stage startups with ideas or materials for improving the chipmaking process “An EUV R&D center doesn’t mean just one machine,” says Khare. “It needs so many machines around it… It’s a very large ecosystem.”

Silicon Valley lands the design center

The design center is tasked with conducting advanced research in chip design, electronic design automation (EDA), chip and system architectures, and hardware security. It will also host the NSTC’s design enablement gateway—a program that provides NSTC members with a secure, cloud-based access to design tools, reference processes and designs, and shared data sets, with the goal of reducing the time and cost of design. Additionally, it will house workforce development, member convening, and administration functions.

Situating the design center in Silicon Valley, with its concentration of research universities, venture capital, and workforce, seems like the obvious choice to many experts. “I can’t think of a better place,” says Patrick Soheili, co-founder of interconnect technology startup Eliyan, which is based in Santa Clara, Calif.

Abhijeet Chakraborty, vice president of engineering in the technology and product group at Silicon Valley-based Synopsys, a leading maker of EDA software, sees Silicon Valley’s expansive tech ecosystem as one of its main advantages in landing the NSTC’s design center. The region concentrates companies and researchers involved in the whole spectrum of the industry from semiconductor process technology to cloud software.

Access to such a broad range of industries is increasingly important for chip design startups, he says. “To design a chip or component these days you need to go from concept to design to validation in an environment that takes care of the entire stack,” he says. It’s prohibitively expensive for a startup to do that alone, so one of Chakraborty’s hopes for the design center is that it will help startups access the design kits and other data needed to operate in this new environment.

Packaging and prototyping still to come

A third promised center for prototyping and packaging is still to come. “The big question is where does the packaging and prototyping go?” says Mark Granahan, cofounder and CEO of Pennsylvania-based power semiconductor startup Ideal Semiconductor. “To me that’s a great opportunity.” He points out that because there is so little packaging technology infrastructure in the United States, any ambitious state or region should have a shot at hosting such a center. One of the original intentions of the act, after all, was to expand the number of regions of the country that are involved in the semiconductor industry.

But that hasn’t stopped some already tech-heavy regions from wanting it. “Oregon offers the strongest ecosystem for such a facility,” a spokesperson for Intel, whose technology development is done there. “The state is uniquely positioned to contribute to the success of the NSTC and help drive technological advancements in the U.S. semiconductor industry.”

As NSTC makes progress, Granahan’s concern is that bureaucracy will expand with it and slow efforts to boost the U.S. chip industry. Already the layers of control are multiplying. The Chips Office at the National Institute of Standards and Technology executes the Act. The NSTC is administered by the nonprofit Natcast, which directs the EUV center, which is in a facility run by another nonprofit, NY CREATES. “We want these things to be agile and make local decisions.”

Finished chips coming in from the foundry are subject to a battery of tests. For those destined for critical systems in cars, those tests are particularly extensive and can add 5 to 10 percent to the cost of a chip. But do you really need to do every single test?

Engineers at NXP have developed a machine-learning algorithm that learns the patterns of test results and figures out the subset of tests that are really needed and those that they could safely do without. The NXP engineers described the process at the IEEE International Test Conference in San Diego last week.

NXP makes a wide variety of chips with complex circuitry and advanced chip-making technology, including inverters for EV motors, audio chips for consumer electronics, and key-fob transponders to secure your car. These chips are tested with different signals at different voltages and at different temperatures in a test process called continue-on-fail. In that process, chips are tested in groups and are all subjected to the complete battery, even if some parts fail some of the tests along the way.

Chips were subject to between 41 and 164 tests, and the algorithm was able to recommend removing 42 to 74 percent of those tests.

“We have to ensure stringent quality requirements in the field, so we have to do a lot of testing,” says Mehul Shroff, an NXP Fellow who led the research. But with much of the actual production and packaging of chips outsourced to other companies, testing is one of the few knobs most chip companies can turn to control costs. “What we were trying to do here is come up with a way to reduce test cost in a way that was statistically rigorous and gave us good results without compromising field quality.”

A Test Recommender System

Shroff says the problem has certain similarities to the machine learning-based recommender systems used in e-commerce. “We took the concept from the retail world, where a data analyst can look at receipts and see what items people are buying together,” he says. “Instead of a transaction receipt, we have a unique part identifier and instead of the items that a consumer would purchase, we have a list of failing tests.”

The NXP algorithm then discovered which tests fail together. Of course, what’s at stake for whether a purchaser of bread will want to buy butter is quite different from whether a test of an automotive part at a particular temperature means other tests don’t need to be done. “We need to have 100 percent or near 100 percent certainty,” Shroff says. “We operate in a different space with respect to statistical rigor compared to the retail world, but it’s borrowing the same concept.”

As rigorous as the results are, Shroff says that they shouldn’t be relied upon on their own. You have to “make sure it makes sense from engineering perspective and that you can understand it in technical terms,” he says. “Only then, remove the test.”

Shroff and his colleagues analyzed data obtained from testing seven microcontrollers and applications processors built using advanced chipmaking processes. Depending on which chip was involved, they were subject to between 41 and 164 tests, and the algorithm was able to recommend removing 42 to 74 percent of those tests. Extending the analysis to data from other types of chips led to an even wider range of opportunities to trim testing.

The algorithm is a pilot project for now, and the NXP team is looking to expand it to a broader set of parts, reduce the computational overhead, and make it easier to use.

Waiting for each part of a 3D-printed project to finish, taking it out of the printer, and then installing it on location can be tedious for multi-part projects. What if there was a way for your printer to print its creation exactly where you needed it? That’s the promise of MobiPrint, a new 3D printing robot that can move around a room, printing designs directly onto the floor.

MobiPrint, designed by Daniel Campos Zamora at the University of Washington, consists of a modified off-the-shelf 3D printer atop a home vacuum robot. First it autonomously maps its space—be it a room, a hallway, or an entire floor of a house. Users can then choose from a prebuilt library or upload their own design to be printed anywhere in the mapped area. The robot then traverses the room and prints the design.

It’s “a new system that combines robotics and 3D printing that could actually go and print in the real world,” Campos Zamora says. He presented MobiPrint on 15 October at the ACM Symposium on User Interface Software and Technology.

Campos Zamora and his team started with a Roborock S5 vacuum robot and installed firmware that allowed it to communicate with the open source program Valetudo. Valetudo disconnects personal robots from their manufacturer’s cloud, connecting them to a local server instead. Data collected by the robot, such as environmental mapping, movement tracking, and path planning, can all be observed locally, enabling users to see the robot’s LIDAR-created map.

Campos Zamora built a layer of software that connects the robot’s perception of its environment to the 3D printer’s print commands. The printer, a modified Prusa Mini+, can print on carpet, hardwood, and vinyl, with maximum printing dimensions of 180 by 180 by 65 millimeters. The robot has printed pet food bowls, signage, and accessibility markers as sample objects.

MakeabilityLab/YouTube

Currently, MobiPrint can only “park and print.” The robot base cannot move during printing to make large objects, like a mobility ramp. Printing designs larger than the robot is one of Campos Zamora’s goals in the future. To learn more about the team’s vision for MobiPrint, Campos Zamora answered a few questions from IEEE Spectrum.

What was the inspiration for creating your mobile 3D printer?

Daniel Campos Zamora: My lab is focused on building systems with an eye towards accessibility. One of the things that really inspired this project was looking at the tactile surface indicators that help blind and low vision users find their way around a space. And so we were like, what if we made something that could automatically go and deploy these things? Especially in indoor environments, which are generally a little trickier and change more frequently over time.

We had to step back and build this entirely different thing, using the environment as a design element. We asked: how do you integrate the real world environment into the design process, and then what kind of things can you print out in the world? That’s how this printer was born.

What were some surprising moments in your design process?

Campos Zamora: When I was testing the robot on different surfaces, I was not expecting the 3D printed designs to stick extremely well to the carpet. It stuck way too well. Like, you know, just completely bonded down there.

I think there’s also just a lot of joy in seeing this printer move. When I was doing a demonstration of it at this conference last week, it almost seemed like the robot had a personality. A vacuum robot can seem to have a personality, but this printer can actually make objects in my environment, so I feel a different relationship to the machine.

Where do you hope to take MobiPrint in the future?

Campos Zamora: There’s several directions I think we could go. Instead of controlling the robot remotely, we could have it follow someone around and print accessibility markers along a path they walk. Or we could integrate an AI system that recommends objects be printed in different locations. I also want to explore having the robot remove and recycle the objects it prints.

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